[people/ms/u-boot.git] / cpu / mpc83xx / cpu_init.c

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc83xx.h>
#include <ioports.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
			 int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);

static void config_qe_ioports(void)
{
	u8	port, pin;
	int	dir, open_drain, assign;
	int	i;

	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
		port		= qe_iop_conf_tab[i].port;
		pin		= qe_iop_conf_tab[i].pin;
		dir		= qe_iop_conf_tab[i].dir;
		open_drain	= qe_iop_conf_tab[i].open_drain;
		assign		= qe_iop_conf_tab[i].assign;
		qe_config_iopin(port, pin, dir, open_drain, assign);
	}
}
#endif

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f (volatile immap_t * im)
{
	/* Pointer is writable since we allocated a register for it */
	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);

	/* Clear initial global data */
	memset ((void *) gd, 0, sizeof (gd_t));

	/* system performance tweaking */

#ifdef CFG_ACR_PIPE_DEP
	/* Arbiter pipeline depth */
	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
			  (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif

#ifdef CFG_SPCR_TSECEP
	/* eTSEC Emergency priority */
	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
#endif

#ifdef CFG_ACR_RPTCNT
	/* Arbiter repeat count */
	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
			  (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
#endif

#ifdef CFG_SPCR_TSECEP
	/* all TSEC's Emergency priority */
	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
			   (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
#endif

#ifdef CFG_SPCR_TSEC1EP
	/* TSEC1 Emergency priority */
	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
			   (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
#endif

#ifdef CFG_SPCR_TSEC2EP
	/* TSEC2 Emergency priority */
	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
			   (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
#endif

#ifdef CFG_SCCR_ENCCM
	/* Encryption clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
		       (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
#endif

#ifdef CFG_SCCR_PCICM
	/* PCI & DMA clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
		       (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
#endif

#ifdef CFG_SCCR_TSECCM
	/* all TSEC's clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
		       (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
#endif

#ifdef CFG_SCCR_TSEC1CM
	/* TSEC1 clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
		       (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
#endif

#ifdef CFG_SCCR_TSEC2CM
	/* TSEC2 clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
		       (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
#endif

#ifdef CFG_SCCR_TSEC1ON
	/* TSEC1 clock switch */
	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
		       (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
#endif

#ifdef CFG_SCCR_TSEC2ON
	/* TSEC2 clock switch */
	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
		       (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
#endif

#ifdef CFG_SCCR_USBMPHCM
	/* USB MPH clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
		       (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
#endif

#ifdef CFG_SCCR_USBDRCM
	/* USB DR clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
		       (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
#endif

#ifdef CFG_SCCR_SATACM
	/* SATA controller clock mode */
	im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
		       (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
#endif

	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
	gd->reset_status = im->reset.rsr;
	im->reset.rsr = ~(RSR_RES);

	/*
	 * RMR - Reset Mode Register
	 * contains checkstop reset enable (4.6.1.4)
	 */
	im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));

	/* LCRR - Clock Ratio Register (10.3.1.16) */
	im->lbus.lcrr = CFG_LCRR;

	/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
	im->sysconf.spcr |= SPCR_TBEN;

	/* System General Purpose Register */
#ifdef CFG_SICRH
	im->sysconf.sicrh = CFG_SICRH;
#endif
#ifdef CFG_SICRL
	im->sysconf.sicrl = CFG_SICRL;
#endif
	/* DDR control driver register */
#ifdef CFG_DDRCDR
	im->sysconf.ddrcdr = CFG_DDRCDR;
#endif
	/* Output buffer impedance register */
#ifdef CFG_OBIR
	im->sysconf.obir = CFG_OBIR;
#endif

#ifdef CONFIG_QE
	/* Config QE ioports */
	config_qe_ioports();
#endif

	/*
	 * Memory Controller:
	 */

	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	 * addresses - these have to be modified later when FLASH size
	 * has been determined
	 */

#if defined(CFG_BR0_PRELIM)  \
	&& defined(CFG_OR0_PRELIM) \
	&& defined(CFG_LBLAWBAR0_PRELIM) \
	&& defined(CFG_LBLAWAR0_PRELIM)
	im->lbus.bank[0].br = CFG_BR0_PRELIM;
	im->lbus.bank[0].or = CFG_OR0_PRELIM;
	im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
	im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
#else
#error 	CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
#endif

#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
	im->lbus.bank[1].br = CFG_BR1_PRELIM;
	im->lbus.bank[1].or = CFG_OR1_PRELIM;
#endif
#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
	im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
	im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
#endif
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
	im->lbus.bank[2].br = CFG_BR2_PRELIM;
	im->lbus.bank[2].or = CFG_OR2_PRELIM;
#endif
#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
	im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
	im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
#endif
#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
	im->lbus.bank[3].br = CFG_BR3_PRELIM;
	im->lbus.bank[3].or = CFG_OR3_PRELIM;
#endif
#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
	im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
	im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
#endif
#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
	im->lbus.bank[4].br = CFG_BR4_PRELIM;
	im->lbus.bank[4].or = CFG_OR4_PRELIM;
#endif
#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
	im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
	im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
#endif
#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
	im->lbus.bank[5].br = CFG_BR5_PRELIM;
	im->lbus.bank[5].or = CFG_OR5_PRELIM;
#endif
#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
	im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
	im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
#endif
#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
	im->lbus.bank[6].br = CFG_BR6_PRELIM;
	im->lbus.bank[6].or = CFG_OR6_PRELIM;
#endif
#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
	im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
	im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
#endif
#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
	im->lbus.bank[7].br = CFG_BR7_PRELIM;
	im->lbus.bank[7].or = CFG_OR7_PRELIM;
#endif
#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
	im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
#endif
#ifdef CFG_GPIO1_PRELIM
	im->gpio[0].dir = CFG_GPIO1_DIR;
	im->gpio[0].dat = CFG_GPIO1_DAT;
#endif
#ifdef CFG_GPIO2_PRELIM
	im->gpio[1].dir = CFG_GPIO2_DIR;
	im->gpio[1].dat = CFG_GPIO2_DAT;
#endif
}

int cpu_init_r (void)
{
#ifdef CONFIG_QE
	uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
	qe_init(qe_base);
	qe_reset();
#endif
	return 0;
}

/*
 * Figure out the cause of the reset
 */
int prt_83xx_rsr(void)
{
	static struct {
		ulong mask;
		char *desc;
	} bits[] = {
		{
		RSR_SWSR, "Software Soft"}, {
		RSR_SWHR, "Software Hard"}, {
		RSR_JSRS, "JTAG Soft"}, {
		RSR_CSHR, "Check Stop"}, {
		RSR_SWRS, "Software Watchdog"}, {
		RSR_BMRS, "Bus Monitor"}, {
		RSR_SRS,  "External/Internal Soft"}, {
		RSR_HRS,  "External/Internal Hard"}
	};
	static int n = sizeof bits / sizeof bits[0];
	ulong rsr = gd->reset_status;
	int i;
	char *sep;

	puts("Reset Status:");

	sep = " ";
	for (i = 0; i < n; i++)
		if (rsr & bits[i].mask) {
			printf("%s%s", sep, bits[i].desc);
			sep = ", ";
		}
	puts("\n\n");
	return 0;
}
Commit	Line	Data
f046ccd1	1	/*
19580e66	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
f046ccd1 EL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
f046ccd1 EL	21	*/
	22
	23	#include <common.h>
	24	#include <mpc83xx.h>
	25	#include <ioports.h>
	26
d87080b7 WD	27	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	28
7737d5c6 DL	29	#ifdef CONFIG_QE
	30	extern qe_iop_conf_t qe_iop_conf_tab[];
	31	extern void qe_config_iopin(u8 port, u8 pin, int dir,
	32	int open_drain, int assign);
	33	extern void qe_init(uint qe_base);
	34	extern void qe_reset(void);
	35
	36	static void config_qe_ioports(void)
	37	{
	38	u8 port, pin;
	39	int dir, open_drain, assign;
	40	int i;
	41
	42	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	43	port = qe_iop_conf_tab[i].port;
	44	pin = qe_iop_conf_tab[i].pin;
	45	dir = qe_iop_conf_tab[i].dir;
	46	open_drain = qe_iop_conf_tab[i].open_drain;
	47	assign = qe_iop_conf_tab[i].assign;
	48	qe_config_iopin(port, pin, dir, open_drain, assign);
	49	}
	50	}
	51	#endif
	52
f046ccd1 EL	53	/*
	54	* Breathe some life into the CPU...
	55	*
	56	* Set up the memory map,
	57	* initialize a bunch of registers,
	58	* initialize the UPM's
	59	*/
	60	void cpu_init_f (volatile immap_t * im)
	61	{
f046ccd1 EL	62	/* Pointer is writable since we allocated a register for it */
	63	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
	64
	65	/* Clear initial global data */
	66	memset ((void *) gd, 0, sizeof (gd_t));
	67
2ad6b513 TT	68	/* system performance tweaking */
	69
	70	#ifdef CFG_ACR_PIPE_DEP
	71	/* Arbiter pipeline depth */
4feab4de KG	72	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) \|
4feab4de KG	73	(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
2ad6b513 TT	74	#endif
2ad6b513 TT	75
b05884ef DL	76	#ifdef CFG_SPCR_TSECEP
	77	/* eTSEC Emergency priority */
	78	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) \| (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
	79	#endif
	80
9e896478 KP	81	#ifdef CFG_ACR_RPTCNT
	82	/* Arbiter repeat count */
	83	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) \|
	84	(CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
	85	#endif
	86
	87	#ifdef CFG_SPCR_TSECEP
	88	/* all TSEC's Emergency priority */
	89	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) \|
	90	(CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
	91	#endif
	92
2ad6b513 TT	93	#ifdef CFG_SPCR_TSEC1EP
2ad6b513 TT	94	/* TSEC1 Emergency priority */
9e896478 KP	95	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) \|
9e896478 KP	96	(CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
2ad6b513 TT	97	#endif
	98
	99	#ifdef CFG_SPCR_TSEC2EP
	100	/* TSEC2 Emergency priority */
9e896478 KP	101	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) \|
	102	(CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
	103	#endif
	104
	105	#ifdef CFG_SCCR_ENCCM
	106	/* Encryption clock mode */
	107	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) \|
	108	(CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
	109	#endif
	110
	111	#ifdef CFG_SCCR_PCICM
	112	/* PCI & DMA clock mode */
	113	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) \|
	114	(CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
	115	#endif
	116
	117	#ifdef CFG_SCCR_TSECCM
	118	/* all TSEC's clock mode */
	119	im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) \|
	120	(CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
2ad6b513 TT	121	#endif
	122
	123	#ifdef CFG_SCCR_TSEC1CM
	124	/* TSEC1 clock mode */
9e896478 KP	125	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) \|
9e896478 KP	126	(CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
2ad6b513	127	#endif
df33f6b4	128
2ad6b513	129	#ifdef CFG_SCCR_TSEC2CM
9e896478 KP	130	/* TSEC2 clock mode */
	131	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) \|
	132	(CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
4feab4de	133	#endif
df33f6b4 TT	134
	135	#ifdef CFG_SCCR_TSEC1ON
	136	/* TSEC1 clock switch */
9e896478 KP	137	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) \|
9e896478 KP	138	(CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
df33f6b4 TT	139	#endif
	140
	141	#ifdef CFG_SCCR_TSEC2ON
	142	/* TSEC2 clock switch */
9e896478 KP	143	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) \|
9e896478 KP	144	(CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
df33f6b4 TT	145	#endif
df33f6b4 TT	146
4feab4de KG	147	#ifdef CFG_SCCR_USBMPHCM
4feab4de KG	148	/* USB MPH clock mode */
9e896478 KP	149	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) \|
9e896478 KP	150	(CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
4feab4de KG	151	#endif
	152
	153	#ifdef CFG_SCCR_USBDRCM
	154	/* USB DR clock mode */
9e896478 KP	155	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) \|
9e896478 KP	156	(CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
4feab4de KG	157	#endif
4feab4de KG	158
9e896478 KP	159	#ifdef CFG_SCCR_SATACM
	160	/* SATA controller clock mode */
	161	im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) \|
	162	(CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
2ad6b513 TT	163	#endif
2ad6b513 TT	164
f046ccd1 EL	165	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
	166	gd->reset_status = im->reset.rsr;
	167	im->reset.rsr = ~(RSR_RES);
	168
	169	/*
	170	* RMR - Reset Mode Register
	171	* contains checkstop reset enable (4.6.1.4)
	172	*/
	173	im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
	174
	175	/* LCRR - Clock Ratio Register (10.3.1.16) */
	176	im->lbus.lcrr = CFG_LCRR;
	177
	178	/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
	179	im->sysconf.spcr \|= SPCR_TBEN;
	180
	181	/* System General Purpose Register */
9260a561 KG	182	#ifdef CFG_SICRH
	183	im->sysconf.sicrh = CFG_SICRH;
	184	#endif
	185	#ifdef CFG_SICRL
	186	im->sysconf.sicrl = CFG_SICRL;
	187	#endif
24c3aca3 DL	188	/* DDR control driver register */
	189	#ifdef CFG_DDRCDR
	190	im->sysconf.ddrcdr = CFG_DDRCDR;
	191	#endif
19580e66 DL	192	/* Output buffer impedance register */
	193	#ifdef CFG_OBIR
	194	im->sysconf.obir = CFG_OBIR;
	195	#endif
24c3aca3	196
7737d5c6 DL	197	#ifdef CONFIG_QE
	198	/* Config QE ioports */
	199	config_qe_ioports();
	200	#endif
f046ccd1 EL	201
	202	/*
	203	* Memory Controller:
	204	*/
	205
	206	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	207	* addresses - these have to be modified later when FLASH size
	208	* has been determined
	209	*/
	210
	211	#if defined(CFG_BR0_PRELIM) \
	212	&& defined(CFG_OR0_PRELIM) \
	213	&& defined(CFG_LBLAWBAR0_PRELIM) \
	214	&& defined(CFG_LBLAWAR0_PRELIM)
	215	im->lbus.bank[0].br = CFG_BR0_PRELIM;
	216	im->lbus.bank[0].or = CFG_OR0_PRELIM;
	217	im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
	218	im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
	219	#else
	220	#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
	221	#endif
	222
c99f384d	223	#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
f046ccd1 EL	224	im->lbus.bank[1].br = CFG_BR1_PRELIM;
f046ccd1 EL	225	im->lbus.bank[1].or = CFG_OR1_PRELIM;
c99f384d KG	226	#endif
c99f384d KG	227	#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
f046ccd1 EL	228	im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
	229	im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
	230	#endif
c99f384d	231	#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
f046ccd1 EL	232	im->lbus.bank[2].br = CFG_BR2_PRELIM;
f046ccd1 EL	233	im->lbus.bank[2].or = CFG_OR2_PRELIM;
c99f384d KG	234	#endif
c99f384d KG	235	#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
f046ccd1 EL	236	im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
	237	im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
	238	#endif
c99f384d	239	#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
f046ccd1 EL	240	im->lbus.bank[3].br = CFG_BR3_PRELIM;
f046ccd1 EL	241	im->lbus.bank[3].or = CFG_OR3_PRELIM;
c99f384d KG	242	#endif
c99f384d KG	243	#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
f046ccd1 EL	244	im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
	245	im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
	246	#endif
c99f384d	247	#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
f046ccd1 EL	248	im->lbus.bank[4].br = CFG_BR4_PRELIM;
f046ccd1 EL	249	im->lbus.bank[4].or = CFG_OR4_PRELIM;
c99f384d KG	250	#endif
c99f384d KG	251	#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
f046ccd1 EL	252	im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
	253	im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
	254	#endif
c99f384d	255	#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
f046ccd1 EL	256	im->lbus.bank[5].br = CFG_BR5_PRELIM;
f046ccd1 EL	257	im->lbus.bank[5].or = CFG_OR5_PRELIM;
c99f384d KG	258	#endif
c99f384d KG	259	#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
f046ccd1 EL	260	im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
	261	im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
	262	#endif
c99f384d	263	#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
f046ccd1 EL	264	im->lbus.bank[6].br = CFG_BR6_PRELIM;
f046ccd1 EL	265	im->lbus.bank[6].or = CFG_OR6_PRELIM;
c99f384d KG	266	#endif
c99f384d KG	267	#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
f046ccd1 EL	268	im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
	269	im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
	270	#endif
c99f384d	271	#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
f046ccd1 EL	272	im->lbus.bank[7].br = CFG_BR7_PRELIM;
f046ccd1 EL	273	im->lbus.bank[7].or = CFG_OR7_PRELIM;
c99f384d KG	274	#endif
c99f384d KG	275	#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
f046ccd1 EL	276	im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
	277	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
	278	#endif
a15b44db	279	#ifdef CFG_GPIO1_PRELIM
e080313c DL	280	im->gpio[0].dir = CFG_GPIO1_DIR;
e080313c DL	281	im->gpio[0].dat = CFG_GPIO1_DAT;
a15b44db KG	282	#endif
a15b44db KG	283	#ifdef CFG_GPIO2_PRELIM
e080313c DL	284	im->gpio[1].dir = CFG_GPIO2_DIR;
e080313c DL	285	im->gpio[1].dat = CFG_GPIO2_DAT;
a15b44db	286	#endif
f046ccd1 EL	287	}
f046ccd1 EL	288
f046ccd1 EL	289	int cpu_init_r (void)
f046ccd1 EL	290	{
7737d5c6	291	#ifdef CONFIG_QE
d239d74b	292	uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
7737d5c6 DL	293	qe_init(qe_base);
	294	qe_reset();
	295	#endif
f046ccd1 EL	296	return 0;
f046ccd1 EL	297	}
9be39a67 DL	298
	299	/*
	300	* Figure out the cause of the reset
	301	*/
	302	int prt_83xx_rsr(void)
	303	{
	304	static struct {
	305	ulong mask;
	306	char *desc;
	307	} bits[] = {
	308	{
	309	RSR_SWSR, "Software Soft"}, {
	310	RSR_SWHR, "Software Hard"}, {
	311	RSR_JSRS, "JTAG Soft"}, {
	312	RSR_CSHR, "Check Stop"}, {
	313	RSR_SWRS, "Software Watchdog"}, {
	314	RSR_BMRS, "Bus Monitor"}, {
	315	RSR_SRS, "External/Internal Soft"}, {
	316	RSR_HRS, "External/Internal Hard"}
	317	};
	318	static int n = sizeof bits / sizeof bits[0];
	319	ulong rsr = gd->reset_status;
	320	int i;
	321	char *sep;
	322
	323	puts("Reset Status:");
	324
	325	sep = " ";
	326	for (i = 0; i < n; i++)
	327	if (rsr & bits[i].mask) {
	328	printf("%s%s", sep, bits[i].desc);
	329	sep = ", ";
	330	}
	331	puts("\n\n");
	332	return 0;
	333	}