[people/ms/u-boot.git] / cpu / mpc83xx / pci.c

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2007
 *
 * Author: Scott Wood <scottwood@freescale.com>,
 * with some bits from older board-specific PCI initialization.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif

#include <asm/mpc8349_pci.h>

#define MAX_BUSES 2

DECLARE_GLOBAL_DATA_PTR;

static struct pci_controller pci_hose[MAX_BUSES];
static int pci_num_buses;

static void pci_init_bus(int bus, struct pci_region *reg)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile pot83xx_t *pot = immr->ios.pot;
	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
	struct pci_controller *hose = &pci_hose[bus];
	u32 dev;
	u16 reg16;
	int i;

	if (bus == 1)
		pot += 3;

	/* Setup outbound translation windows */
	for (i = 0; i < 3; i++, reg++, pot++) {
		if (reg->size == 0)
			break;

		hose->regions[i] = *reg;
		hose->region_count++;

		pot->potar = reg->bus_start >> 12;
		pot->pobar = reg->phys_start >> 12;
		pot->pocmr = ~(reg->size - 1) >> 12;

		if (reg->flags & PCI_REGION_IO)
			pot->pocmr |= POCMR_IO;
#ifdef CONFIG_83XX_PCI_STREAMING
		else if (reg->flags & PCI_REGION_PREFETCH)
			pot->pocmr |= POCMR_SE;
#endif

		if (bus == 1)
			pot->pocmr |= POCMR_DST;

		pot->pocmr |= POCMR_EN;
	}

	/* Point inbound translation at RAM */
	pci_ctrl->pitar1 = 0;
	pci_ctrl->pibar1 = 0;
	pci_ctrl->piebar1 = 0;
	pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
	                   PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);

	i = hose->region_count++;
	hose->regions[i].bus_start = 0;
	hose->regions[i].phys_start = 0;
	hose->regions[i].size = gd->ram_size;
	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
	                         CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
}

/*
 * The caller must have already set OCCR, and the PCI_LAW BARs
 * must have been set to cover all of the requested regions.
 *
 * If fewer than three regions are requested, then the region
 * list is terminated with a region of size 0.
 */
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	int i;

	if (num_buses > MAX_BUSES) {
		printf("%d PCI buses requsted, %d supported\n",
		       num_buses, MAX_BUSES);

		num_buses = MAX_BUSES;
	}

	pci_num_buses = num_buses;

	/*
	 * Release PCI RST Output signal.
	 * Power on to RST high must be at least 100 ms as per PCI spec.
	 * On warm boots only 1 ms is required.
	 */
	udelay(warmboot ? 1000 : 100000);

	for (i = 0; i < num_buses; i++)
		immr->pci_ctrl[i].gcr = 1;

	/*
	 * RST high to first config access must be at least 2^25 cycles
	 * as per PCI spec.  This could be cut in half if we know we're
	 * running at 66MHz.  This could be insufficiently long if we're
	 * running the PCI bus at significantly less than 33MHz.
	 */
	udelay(1020000);

	for (i = 0; i < num_buses; i++)
		pci_init_bus(i, reg[i]);
}

#ifdef CONFIG_PCISLAVE

#define PCI_FUNCTION_CONFIG	0x44
#define PCI_FUNCTION_CFG_LOCK	0x20

/*
 * Unlock the configuration bit so that the host system can begin booting
 *
 * This should be used after you have:
 * 1) Called mpc83xx_pci_init()
 * 2) Set up your inbound translation windows to the appropriate size
 */
void mpc83xx_pcislave_unlock(int bus)
{
	struct pci_controller *hose = &pci_hose[bus];
	u32 dev;
	u16 reg16;

	/* Unlock configuration lock in PCI function configuration register */
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
	pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
}
#endif

#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
	int nodeoffset;
	int tmp[2];
	const char *path;

	if (pci_num_buses < 1)
		return;

	nodeoffset = fdt_path_offset(blob, "/aliases");
	if (nodeoffset >= 0) {
		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
		if (path) {
			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
			do_fixup_by_path(blob, path, "bus-range",
				&tmp, sizeof(tmp), 1);

			tmp[0] = cpu_to_be32(gd->pci_clk);
			do_fixup_by_path(blob, path, "clock-frequency",
				&tmp, sizeof(tmp[0]), 1);
		}

		if (pci_num_buses < 2)
			return;

		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
		if (path) {
			tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
			tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
			do_fixup_by_path(blob, path, "bus-range",
				&tmp, sizeof(tmp), 1);

			tmp[0] = cpu_to_be32(gd->pci_clk);
			do_fixup_by_path(blob, path, "clock-frequency",
				&tmp, sizeof(tmp[0]), 1);
		}
	}
}
#endif /* CONFIG_OF_LIBFDT */
Commit	Line	Data
49ea3b6e SW	1	/*
	2	* Copyright (C) Freescale Semiconductor, Inc. 2007
	3	*
	4	* Author: Scott Wood <scottwood@freescale.com>,
	5	* with some bits from older board-specific PCI initialization.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <pci.h>
343d9100 KP	28
	29	#if defined(CONFIG_OF_LIBFDT)
	30	#include <libfdt.h>
5b8bc606	31	#include <fdt_support.h>
343d9100 KP	32	#endif
343d9100 KP	33
49ea3b6e SW	34	#include <asm/mpc8349_pci.h>
49ea3b6e SW	35
49ea3b6e SW	36	#define MAX_BUSES 2
	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	static struct pci_controller pci_hose[MAX_BUSES];
	41	static int pci_num_buses;
	42
	43	static void pci_init_bus(int bus, struct pci_region *reg)
	44	{
6d0f6bcf	45	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
49ea3b6e SW	46	volatile pot83xx_t *pot = immr->ios.pot;
	47	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
	48	struct pci_controller *hose = &pci_hose[bus];
	49	u32 dev;
	50	u16 reg16;
	51	int i;
	52
	53	if (bus == 1)
	54	pot += 3;
	55
	56	/* Setup outbound translation windows */
	57	for (i = 0; i < 3; i++, reg++, pot++) {
	58	if (reg->size == 0)
	59	break;
	60
	61	hose->regions[i] = *reg;
	62	hose->region_count++;
	63
	64	pot->potar = reg->bus_start >> 12;
	65	pot->pobar = reg->phys_start >> 12;
	66	pot->pocmr = ~(reg->size - 1) >> 12;
	67
	68	if (reg->flags & PCI_REGION_IO)
	69	pot->pocmr \|= POCMR_IO;
	70	#ifdef CONFIG_83XX_PCI_STREAMING
	71	else if (reg->flags & PCI_REGION_PREFETCH)
	72	pot->pocmr \|= POCMR_SE;
	73	#endif
	74
	75	if (bus == 1)
	76	pot->pocmr \|= POCMR_DST;
	77
	78	pot->pocmr \|= POCMR_EN;
	79	}
	80
	81	/* Point inbound translation at RAM */
	82	pci_ctrl->pitar1 = 0;
	83	pci_ctrl->pibar1 = 0;
	84	pci_ctrl->piebar1 = 0;
	85	pci_ctrl->piwar1 = PIWAR_EN \| PIWAR_PF \| PIWAR_RTT_SNOOP \|
	86	PIWAR_WTT_SNOOP \| (__ilog2(gd->ram_size) - 1);
	87
	88	i = hose->region_count++;
	89	hose->regions[i].bus_start = 0;
	90	hose->regions[i].phys_start = 0;
	91	hose->regions[i].size = gd->ram_size;
	92	hose->regions[i].flags = PCI_REGION_MEM \| PCI_REGION_MEMORY;
	93
	94	hose->first_busno = 0;
	95	hose->last_busno = 0xff;
	96
6d0f6bcf JCPV	97	pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
6d0f6bcf JCPV	98	CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
49ea3b6e SW	99
	100	pci_register_hose(hose);
	101
	102	/*
	103	* Write to Command register
	104	*/
	105	reg16 = 0xff;
	106	dev = PCI_BDF(hose->first_busno, 0, 0);
	107	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	108	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	109	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	110
	111	/*
	112	* Clear non-reserved bits in status register.
	113	*/
	114	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	115	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	116	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	117
	118	#ifdef CONFIG_PCI_SCAN_SHOW
	119	printf("PCI: Bus Dev VenId DevId Class Int\n");
	120	#endif
	121	/*
	122	* Hose scan.
	123	*/
	124	hose->last_busno = pci_hose_scan(hose);
	125	}
	126
	127	/*
	128	* The caller must have already set OCCR, and the PCI_LAW BARs
	129	* must have been set to cover all of the requested regions.
	130	*
	131	* If fewer than three regions are requested, then the region
	132	* list is terminated with a region of size 0.
	133	*/
	134	void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
	135	{
6d0f6bcf	136	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
49ea3b6e SW	137	int i;
	138
	139	if (num_buses > MAX_BUSES) {
	140	printf("%d PCI buses requsted, %d supported\n",
	141	num_buses, MAX_BUSES);
	142
	143	num_buses = MAX_BUSES;
	144	}
	145
	146	pci_num_buses = num_buses;
	147
	148	/*
	149	* Release PCI RST Output signal.
	150	* Power on to RST high must be at least 100 ms as per PCI spec.
	151	* On warm boots only 1 ms is required.
	152	*/
	153	udelay(warmboot ? 1000 : 100000);
	154
	155	for (i = 0; i < num_buses; i++)
	156	immr->pci_ctrl[i].gcr = 1;
	157
	158	/*
	159	* RST high to first config access must be at least 2^25 cycles
	160	* as per PCI spec. This could be cut in half if we know we're
	161	* running at 66MHz. This could be insufficiently long if we're
	162	* running the PCI bus at significantly less than 33MHz.
	163	*/
	164	udelay(1020000);
	165
	166	for (i = 0; i < num_buses; i++)
	167	pci_init_bus(i, reg[i]);
	168	}
	169
4ff9aea9 IS	170	#ifdef CONFIG_PCISLAVE
	171
	172	#define PCI_FUNCTION_CONFIG 0x44
	173	#define PCI_FUNCTION_CFG_LOCK 0x20
	174
	175	/*
	176	* Unlock the configuration bit so that the host system can begin booting
	177	*
	178	* This should be used after you have:
	179	* 1) Called mpc83xx_pci_init()
	180	* 2) Set up your inbound translation windows to the appropriate size
	181	*/
	182	void mpc83xx_pcislave_unlock(int bus)
	183	{
	184	struct pci_controller *hose = &pci_hose[bus];
	185	u32 dev;
	186	u16 reg16;
	187
	188	/* Unlock configuration lock in PCI function configuration register */
	189	dev = PCI_BDF(hose->first_busno, 0, 0);
	190	pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
	191	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
	192	pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
	193	}
	194	#endif
	195
343d9100 KP	196	#if defined(CONFIG_OF_LIBFDT)
	197	void ft_pci_setup(void blob, bd_t bd)
	198	{
	199	int nodeoffset;
343d9100	200	int tmp[2];
5b8bc606	201	const char *path;
343d9100 KP	202
	203	if (pci_num_buses < 1)
	204	return;
	205
5b8bc606	206	nodeoffset = fdt_path_offset(blob, "/aliases");
343d9100	207	if (nodeoffset >= 0) {
5b8bc606 KP	208	path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
	209	if (path) {
	210	tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
	211	tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
	212	do_fixup_by_path(blob, path, "bus-range",
	213	&tmp, sizeof(tmp), 1);
	214
	215	tmp[0] = cpu_to_be32(gd->pci_clk);
	216	do_fixup_by_path(blob, path, "clock-frequency",
	217	&tmp, sizeof(tmp[0]), 1);
	218	}
	219
	220	if (pci_num_buses < 2)
	221	return;
	222
	223	path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
	224	if (path) {
	225	tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
	226	tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
	227	do_fixup_by_path(blob, path, "bus-range",
	228	&tmp, sizeof(tmp), 1);
	229
	230	tmp[0] = cpu_to_be32(gd->pci_clk);
	231	do_fixup_by_path(blob, path, "clock-frequency",
	232	&tmp, sizeof(tmp[0]), 1);
	233	}
49ea3b6e SW	234	}
49ea3b6e SW	235	}
5b8bc606	236	#endif /* CONFIG_OF_LIBFDT */