[people/ms/u-boot.git] / cpu / mpc83xx / spd_sdram.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Change log:
 *
 * 20050101: Eran Liberty (liberty@freescale.com)
 *           Initial file creating (porting from 85XX & 8260)
 */

#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
#include <spd_sdram.h>

#ifdef CONFIG_SPD_EEPROM

#if defined(CONFIG_DDR_ECC)
extern void dma_init(void);
extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
#endif

#ifndef	CFG_READ_SPD
#define CFG_READ_SPD	i2c_read
#endif

/*
 * Convert picoseconds into clock cycles (rounding up if needed).
 */

int
picos_to_clk(int picos)
{
	int clks;

	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
	clks++;
	}

	return clks;
}

unsigned int
banksize(unsigned char row_dens)
{
	return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
}

long int spd_sdram(int(read_spd)(uint addr))
{
	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
	volatile ddr8349_t *ddr = &immap->ddr;
	volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
	spd_eeprom_t spd;
	unsigned tmp, tmp1;
	unsigned int memsize;
	unsigned int law_size;
	unsigned char caslat;
	unsigned int trfc, trfc_clk, trfc_low;

#warning Current spd_sdram does not fit its usage... adjust implementation or API...

	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));

	if (spd.nrows > 2) {
		puts("DDR:Only two chip selects are supported on ADS.\n");
		return 0;
	}

	if (spd.nrow_addr < 12
	    || spd.nrow_addr > 14
	    || spd.ncol_addr < 8
	    || spd.ncol_addr > 11) {
		puts("DDR:Row or Col number unsupported.\n");
		return 0;
	}

	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
	ddr->cs_config[2] = ( 1 << 31
			    | (spd.nrow_addr - 12) << 8
			    | (spd.ncol_addr - 8) );
	debug("\n");
	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);

	if (spd.nrows == 2) {
		ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
				  | ((banksize(spd.row_dens) >> 23) - 1) );
		ddr->cs_config[3] = ( 1<<31
				    | (spd.nrow_addr-12) << 8
				    | (spd.ncol_addr-8) );
		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
	}

	if (spd.mem_type != 0x07) {
		puts("No DDR module found!\n");
		return 0;
	}

	/*
	 * Figure out memory size in Megabytes.
	 */
	memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;

	/*
	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
	 */
	law_size = 19 + __ilog2(memsize);

	/*
	 * Set up LAWBAR for all of DDR.
	 */
	ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
	ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
	debug("DDR:bar=0x%08x\n", ecm->bar);
	debug("DDR:ar=0x%08x\n", ecm->ar);

	/*
	 * find the largest CAS
	 */
	if(spd.cas_lat & 0x40) {
		caslat = 7;
	} else if (spd.cas_lat & 0x20) {
		caslat = 6;
	} else if (spd.cas_lat & 0x10) {
		caslat = 5;
	} else if (spd.cas_lat & 0x08) {
		caslat = 4;
	} else if (spd.cas_lat & 0x04) {
		caslat = 3;
	} else if (spd.cas_lat & 0x02) {
		caslat = 2;
	} else if (spd.cas_lat & 0x01) {
		caslat = 1;
	} else {
		puts("DDR:no valid CAS Latency information.\n");
		return 0;
	}

	tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
		       + (spd.clk_cycle & 0x0f));
	debug("DDR:Module maximum data rate is: %dMhz\n", tmp);

	tmp1 = get_bus_freq(0) / 1000000;
	if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
		/* 90~230 range, treated as DDR 200 */
		if (spd.clk_cycle3 == 0xa0)
			caslat -= 2;
		else if(spd.clk_cycle2 == 0xa0)
			caslat--;
	} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
		/* 230-280 range, treated as DDR 266 */
		if (spd.clk_cycle3 == 0x75)
			caslat -= 2;
		else if (spd.clk_cycle2 == 0x75)
			caslat--;
	} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
		/* 280~350 range, treated as DDR 333 */
		if (spd.clk_cycle3 == 0x60)
			caslat -= 2;
		else if (spd.clk_cycle2 == 0x60)
			caslat--;
	} else if (tmp1 < 90 || tmp1 >= 350) {
		/* DDR rate out-of-range */
		puts("DDR:platform frequency is not fit for DDR rate\n");
		return 0;
	}

	/*
	 * note: caslat must also be programmed into ddr->sdram_mode
	 * register.
	 *
	 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
	 * use conservative value here.
	 */
	trfc = spd.trfc * 1000;         /* up to ps */
	trfc_clk = picos_to_clk(trfc);
	trfc_low = (trfc_clk - 8) & 0xf;

	ddr->timing_cfg_1 =
	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
	     ((caslat & 0x07) << 16 ) |
	     (trfc_low << 12 ) |
	     ( 0x300 ) |
	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);

	ddr->timing_cfg_2 = 0x00000800;

	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);

	/*
	 * Only DDR I is supported
	 * DDR I and II have different mode-register-set definition
	 */

	/* burst length is always 4 */
	switch(caslat) {
	case 2:
		ddr->sdram_mode = 0x52; /* 1.5 */
		break;
	case 3:
		ddr->sdram_mode = 0x22; /* 2.0 */
		break;
	case 4:
		ddr->sdram_mode = 0x62; /* 2.5 */
		break;
	case 5:
		ddr->sdram_mode = 0x32; /* 3.0 */
		break;
	default:
		puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
		return 0;
	}
	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);

	switch(spd.refresh) {
	case 0x00:
	case 0x80:
		tmp = picos_to_clk(15625000);
		break;
	case 0x01:
	case 0x81:
		tmp = picos_to_clk(3900000);
		break;
	case 0x02:
	case 0x82:
		tmp = picos_to_clk(7800000);
		break;
	case 0x03:
	case 0x83:
		tmp = picos_to_clk(31300000);
		break;
	case 0x04:
	case 0x84:
		tmp = picos_to_clk(62500000);
		break;
	case 0x05:
	case 0x85:
		tmp = picos_to_clk(125000000);
		break;
	default:
		tmp = 0x512;
		break;
	}

	/*
	 * Set BSTOPRE to 0x100 for page mode
	 * If auto-charge is used, set BSTOPRE = 0
	 */
	ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);

	/*
	 * Is this an ECC DDR chip?
	 */
#if defined(CONFIG_DDR_ECC)
	if (spd.config == 0x02) {
		ddr->err_disable = 0x0000000d;
		ddr->err_sbe = 0x00ff0000;
	}
	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
	asm("sync;isync");

	udelay(500);

	/*
	 * SS_EN=1,
	 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
	 * clock cycle after address/command
	 */
	ddr->sdram_clk_cntl = 0x82000000;

	/*
	 * Figure out the settings for the sdram_cfg register.  Build up
	 * the entire register in 'tmp' before writing since the write into
	 * the register will actually enable the memory controller, and all
	 * settings must be done before enabling.
	 *
	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
	 * sdram_cfg[1]   = 1 (self-refresh-enable)
	 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
	 */
	tmp = 0xc2000000;

	/*
	 * sdram_cfg[3] = RD_EN - registered DIMM enable
	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
	 */
	if (spd.mod_attr == 0x26) {
		tmp |= 0x10000000;
	}

#if defined(CONFIG_DDR_ECC)
	/*
	 * If the user wanted ECC (enabled via sdram_cfg[2])
	 */
	if (spd.config == 0x02) {
		tmp |= 0x20000000;
	}
#endif

#if defined(CONFIG_DDR_2T_TIMING)
	/*
	 * Enable 2T timing by setting sdram_cfg[16].
	 */
	tmp |= SDRAM_CFG_2T_EN;
#endif

	ddr->sdram_cfg = tmp;
	asm("sync;isync");
	udelay(500);

	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);

	return memsize;/*in MBytes*/
}
#endif /* CONFIG_SPD_EEPROM */


#if defined(CONFIG_DDR_ECC)
/*
 * Initialize all of memory for ECC, then enable errors.
 */

void
ddr_enable_ecc(unsigned int dram_size)
{
#ifndef FIXME
	uint *p = 0;
	uint i = 0;
	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
	volatile ccsr_ddr_t *ddr= &immap->im_ddr;

	dma_init();

	for (*p = 0; p < (uint *)(8 * 1024); p++) {
		if (((unsigned int)p & 0x1f) == 0) {
			ppcDcbz((unsigned long) p);
		}
		*p = (unsigned int)0xdeadbeef;
		if (((unsigned int)p & 0x1c) == 0x1c) {
			ppcDcbf((unsigned long) p);
		}
	}

	/* 8K */
	dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
	/* 16K */
	dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
	/* 32K */
	dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
	/* 64K */
	dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
	/* 128k */
	dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
	/* 256k */
	dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
	/* 512k */
	dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
	/* 1M */
	dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
	/* 2M */
	dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
	/* 4M */
	dma_xfer((uint *)0x400000, 0x400000, (uint *)0);

	for (i = 1; i < dram_size / 0x800000; i++) {
		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
	}

	/*
	 * Enable errors for ECC.
	 */
	ddr->err_disable = 0x00000000;
	asm("sync;isync");
#endif
}

#endif	/* CONFIG_DDR_ECC */
Commit	Line	Data
f046ccd1 EL	1	/*
	2	* Copyright 2004 Freescale Semiconductor.
	3	* (C) Copyright 2003 Motorola Inc.
	4	* Xianghua Xiao (X.Xiao@motorola.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*
	24	* Change log:
	25	*
	26	* 20050101: Eran Liberty (liberty@freescale.com)
	27	* Initial file creating (porting from 85XX & 8260)
	28	*/
	29
	30	#include <common.h>
	31	#include <asm/processor.h>
	32	#include <i2c.h>
	33	#include <spd.h>
	34	#include <asm/mmu.h>
	35	#include <spd_sdram.h>
	36
	37	#ifdef CONFIG_SPD_EEPROM
	38
f046ccd1 EL	39	#if defined(CONFIG_DDR_ECC)
	40	extern void dma_init(void);
	41	extern uint dma_check(void);
	42	extern int dma_xfer(void dest, uint count, void src);
	43	#endif
	44
f046ccd1 EL	45	#ifndef CFG_READ_SPD
	46	#define CFG_READ_SPD i2c_read
	47	#endif
	48
f046ccd1 EL	49	/*
	50	* Convert picoseconds into clock cycles (rounding up if needed).
	51	*/
	52
	53	int
	54	picos_to_clk(int picos)
	55	{
	56	int clks;
	57
	58	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
	59	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
	60	clks++;
	61	}
	62
	63	return clks;
	64	}
	65
f046ccd1 EL	66	unsigned int
	67	banksize(unsigned char row_dens)
	68	{
	69	return ((row_dens >> 2) \| ((row_dens & 3) << 6)) << 24;
	70	}
	71
f046ccd1 EL	72	long int spd_sdram(int(read_spd)(uint addr))
	73	{
	74	volatile immap_t immap = (immap_t )CFG_IMMRBAR;
	75	volatile ddr8349_t *ddr = &immap->ddr;
	76	volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
	77	spd_eeprom_t spd;
	78	unsigned tmp, tmp1;
	79	unsigned int memsize;
	80	unsigned int law_size;
	81	unsigned char caslat;
	82	unsigned int trfc, trfc_clk, trfc_low;
de1d0a69 JL	83
de1d0a69 JL	84	#warning Current spd_sdram does not fit its usage... adjust implementation or API...
f046ccd1 EL	85
	86	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
	87
	88	if (spd.nrows > 2) {
	89	puts("DDR:Only two chip selects are supported on ADS.\n");
	90	return 0;
	91	}
	92
	93	if (spd.nrow_addr < 12
	94	\|\| spd.nrow_addr > 14
	95	\|\| spd.ncol_addr < 8
	96	\|\| spd.ncol_addr > 11) {
	97	puts("DDR:Row or Col number unsupported.\n");
	98	return 0;
	99	}
	100
	101	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
	102	ddr->cs_config[2] = ( 1 << 31
	103	\| (spd.nrow_addr - 12) << 8
	104	\| (spd.ncol_addr - 8) );
	105	debug("\n");
	106	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
	107	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
de1d0a69	108
f046ccd1 EL	109	if (spd.nrows == 2) {
	110	ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
	111	\| ((banksize(spd.row_dens) >> 23) - 1) );
	112	ddr->cs_config[3] = ( 1<<31
	113	\| (spd.nrow_addr-12) << 8
	114	\| (spd.ncol_addr-8) );
	115	debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
	116	debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
	117	}
	118
	119	if (spd.mem_type != 0x07) {
	120	puts("No DDR module found!\n");
	121	return 0;
	122	}
	123
	124	/*
	125	* Figure out memory size in Megabytes.
	126	*/
	127	memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
	128
	129	/*
	130	* First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
	131	*/
	132	law_size = 19 + __ilog2(memsize);
	133
	134	/*
	135	* Set up LAWBAR for all of DDR.
	136	*/
	137	ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
	138	ecm->ar = (LAWAR_EN \| LAWAR_TRGT_IF_DDR \| (LAWAR_SIZE & law_size));
	139	debug("DDR:bar=0x%08x\n", ecm->bar);
	140	debug("DDR:ar=0x%08x\n", ecm->ar);
	141
	142	/*
	143	* find the largest CAS
	144	*/
	145	if(spd.cas_lat & 0x40) {
	146	caslat = 7;
	147	} else if (spd.cas_lat & 0x20) {
	148	caslat = 6;
	149	} else if (spd.cas_lat & 0x10) {
	150	caslat = 5;
	151	} else if (spd.cas_lat & 0x08) {
	152	caslat = 4;
	153	} else if (spd.cas_lat & 0x04) {
	154	caslat = 3;
	155	} else if (spd.cas_lat & 0x02) {
	156	caslat = 2;
	157	} else if (spd.cas_lat & 0x01) {
	158	caslat = 1;
	159	} else {
	160	puts("DDR:no valid CAS Latency information.\n");
	161	return 0;
	162	}
	163
	164	tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
	165	+ (spd.clk_cycle & 0x0f));
	166	debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
	167
	168	tmp1 = get_bus_freq(0) / 1000000;
	169	if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
	170	/* 90~230 range, treated as DDR 200 */
	171	if (spd.clk_cycle3 == 0xa0)
	172	caslat -= 2;
173	else if(spd.clk_cycle2 == 0xa0)
174	caslat--;
175	} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
176	/* 230-280 range, treated as DDR 266 */
177	if (spd.clk_cycle3 == 0x75)
178	caslat -= 2;
179	else if (spd.clk_cycle2 == 0x75)
180	caslat--;
181	} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
182	/* 280~350 range, treated as DDR 333 */
183	if (spd.clk_cycle3 == 0x60)
184	caslat -= 2;
185	else if (spd.clk_cycle2 == 0x60)
186	caslat--;
187	} else if (tmp1 < 90 \|\| tmp1 >= 350) {
188	/* DDR rate out-of-range */
189	puts("DDR:platform frequency is not fit for DDR rate\n");
190	return 0;
191	}
192
193	/*
194	* note: caslat must also be programmed into ddr->sdram_mode
195	* register.
196	*
197	* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
198	* use conservative value here.
199	*/
200	trfc = spd.trfc * 1000; /* up to ps */
201	trfc_clk = picos_to_clk(trfc);
202	trfc_low = (trfc_clk - 8) & 0xf;
203
204	ddr->timing_cfg_1 =
205	(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) \|
206	((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) \|
207	((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) \|
208	((caslat & 0x07) << 16 ) \|
209	(trfc_low << 12 ) \|
210	( 0x300 ) \|
211	((picos_to_clk(spd.trrd * 250) & 0x07) << 4) \| 1);
212
213	ddr->timing_cfg_2 = 0x00000800;
214
215	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
216	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
217
218	/*
219	* Only DDR I is supported
220	* DDR I and II have different mode-register-set definition
221	*/
222
223	/* burst length is always 4 */
224	switch(caslat) {
225	case 2:
226	ddr->sdram_mode = 0x52; /* 1.5 */
227	break;
228	case 3:
229	ddr->sdram_mode = 0x22; /* 2.0 */
230	break;
231	case 4:
232	ddr->sdram_mode = 0x62; /* 2.5 */
233	break;
234	case 5:
235	ddr->sdram_mode = 0x32; /* 3.0 */
236	break;
237	default:
238	puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
239	return 0;
240	}
241	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
242
243	switch(spd.refresh) {
244	case 0x00:
245	case 0x80:
246	tmp = picos_to_clk(15625000);
247	break;
248	case 0x01:
249	case 0x81:
250	tmp = picos_to_clk(3900000);
251	break;
252	case 0x02:
253	case 0x82:
254	tmp = picos_to_clk(7800000);
255	break;
256	case 0x03:
257	case 0x83:
258	tmp = picos_to_clk(31300000);
259	break;
260	case 0x04:
261	case 0x84:
262	tmp = picos_to_clk(62500000);
263	break;
264	case 0x05:
265	case 0x85:
266	tmp = picos_to_clk(125000000);
267	break;
268	default:
269	tmp = 0x512;
270	break;
271	}
272
273	/*
274	* Set BSTOPRE to 0x100 for page mode
275	* If auto-charge is used, set BSTOPRE = 0
276	*/
277	ddr->sdram_interval = ((tmp & 0x3fff) << 16) \| 0x100;
278	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
279
280	/*
281	* Is this an ECC DDR chip?
282	*/
283	#if defined(CONFIG_DDR_ECC)
284	if (spd.config == 0x02) {
285	ddr->err_disable = 0x0000000d;
286	ddr->err_sbe = 0x00ff0000;
287	}
288	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
289	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
290	#endif
291	asm("sync;isync");
292
293	udelay(500);
294
de1d0a69 JL	295	/*
	296	* SS_EN=1,
	297	* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
	298	* clock cycle after address/command
	299	*/
	300	ddr->sdram_clk_cntl = 0x82000000;
f046ccd1 EL	301
	302	/*
	303	* Figure out the settings for the sdram_cfg register. Build up
	304	* the entire register in 'tmp' before writing since the write into
	305	* the register will actually enable the memory controller, and all
	306	* settings must be done before enabling.
	307	*
	308	* sdram_cfg[0] = 1 (ddr sdram logic enable)
	309	* sdram_cfg[1] = 1 (self-refresh-enable)
	310	* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
	311	*/
	312	tmp = 0xc2000000;
	313
	314	/*
	315	* sdram_cfg[3] = RD_EN - registered DIMM enable
	316	* A value of 0x26 indicates micron registered DIMMS (micron.com)
	317	*/
	318	if (spd.mod_attr == 0x26) {
	319	tmp \|= 0x10000000;
	320	}
	321
	322	#if defined(CONFIG_DDR_ECC)
	323	/*
	324	* If the user wanted ECC (enabled via sdram_cfg[2])
	325	*/
	326	if (spd.config == 0x02) {
	327	tmp \|= 0x20000000;
	328	}
	329	#endif
	330
	331	#if defined(CONFIG_DDR_2T_TIMING)
	332	/*
	333	* Enable 2T timing by setting sdram_cfg[16].
	334	*/
	335	tmp \|= SDRAM_CFG_2T_EN;
	336	#endif
	337
	338	ddr->sdram_cfg = tmp;
f046ccd1 EL	339	asm("sync;isync");
	340	udelay(500);
	341
	342	debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
	343
	344	return memsize;/in MBytes/
	345	}
f046ccd1 EL	346	#endif /* CONFIG_SPD_EEPROM */
	347
	348
	349	#if defined(CONFIG_DDR_ECC)
	350	/*
	351	* Initialize all of memory for ECC, then enable errors.
	352	*/
	353
	354	void
	355	ddr_enable_ecc(unsigned int dram_size)
	356	{
	357	#ifndef FIXME
	358	uint *p = 0;
	359	uint i = 0;
	360	volatile immap_t immap = (immap_t )CFG_IMMRBAR;
	361	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
	362
	363	dma_init();
	364
	365	for (p = 0; p < (uint )(8 * 1024); p++) {
	366	if (((unsigned int)p & 0x1f) == 0) {
	367	ppcDcbz((unsigned long) p);
	368	}
	369	*p = (unsigned int)0xdeadbeef;
	370	if (((unsigned int)p & 0x1c) == 0x1c) {
	371	ppcDcbf((unsigned long) p);
	372	}
	373	}
	374
	375	/* 8K */
	376	dma_xfer((uint )0x2000, 0x2000, (uint )0);
	377	/* 16K */
	378	dma_xfer((uint )0x4000, 0x4000, (uint )0);
	379	/* 32K */
	380	dma_xfer((uint )0x8000, 0x8000, (uint )0);
	381	/* 64K */
	382	dma_xfer((uint )0x10000, 0x10000, (uint )0);
	383	/* 128k */
	384	dma_xfer((uint )0x20000, 0x20000, (uint )0);
	385	/* 256k */
	386	dma_xfer((uint )0x40000, 0x40000, (uint )0);
	387	/* 512k */
	388	dma_xfer((uint )0x80000, 0x80000, (uint )0);
	389	/* 1M */
	390	dma_xfer((uint )0x100000, 0x100000, (uint )0);
	391	/* 2M */
	392	dma_xfer((uint )0x200000, 0x200000, (uint )0);
	393	/* 4M */
	394	dma_xfer((uint )0x400000, 0x400000, (uint )0);
	395
	396	for (i = 1; i < dram_size / 0x800000; i++) {
	397	dma_xfer((uint )(0x800000i), 0x800000, (uint *)0);
	398	}
	399
	400	/*
	401	* Enable errors for ECC.
	402	*/
	403	ddr->err_disable = 0x00000000;
	404	asm("sync;isync");
de1d0a69	405	#endif
f046ccd1 EL	406	}
	407
	408	#endif /* CONFIG_DDR_ECC */