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f046ccd1 EL |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> | |
e4c09508 | 5 | * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. |
f046ccd1 EL |
6 | * |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
27 | * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards | |
28 | */ | |
29 | ||
30 | #include <config.h> | |
de1d0a69 | 31 | #include <mpc83xx.h> |
f046ccd1 EL |
32 | #include <version.h> |
33 | ||
34 | #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ | |
35 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
36 | ||
37 | #include <ppc_asm.tmpl> | |
38 | #include <ppc_defs.h> | |
39 | ||
40 | #include <asm/cache.h> | |
41 | #include <asm/mmu.h> | |
42 | ||
43 | #ifndef CONFIG_IDENT_STRING | |
44 | #define CONFIG_IDENT_STRING "MPC83XX" | |
45 | #endif | |
46 | ||
47 | /* We don't want the MMU yet. | |
48 | */ | |
49 | #undef MSR_KERNEL | |
50 | ||
51 | /* | |
52 | * Floating Point enable, Machine Check and Recoverable Interr. | |
53 | */ | |
54 | #ifdef DEBUG | |
55 | #define MSR_KERNEL (MSR_FP|MSR_RI) | |
56 | #else | |
57 | #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) | |
58 | #endif | |
59 | ||
6d0f6bcf JCPV |
60 | #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT) |
61 | #define CONFIG_SYS_FLASHBOOT | |
e4c09508 SW |
62 | #endif |
63 | ||
f046ccd1 EL |
64 | /* |
65 | * Set up GOT: Global Offset Table | |
66 | * | |
67 | * Use r14 to access the GOT | |
68 | */ | |
69 | START_GOT | |
70 | GOT_ENTRY(_GOT2_TABLE_) | |
e4c09508 SW |
71 | GOT_ENTRY(__bss_start) |
72 | GOT_ENTRY(_end) | |
f046ccd1 | 73 | |
e4c09508 SW |
74 | #ifndef CONFIG_NAND_SPL |
75 | GOT_ENTRY(_FIXUP_TABLE_) | |
f046ccd1 EL |
76 | GOT_ENTRY(_start) |
77 | GOT_ENTRY(_start_of_vectors) | |
78 | GOT_ENTRY(_end_of_vectors) | |
79 | GOT_ENTRY(transfer_to_handler) | |
e4c09508 | 80 | #endif |
f046ccd1 EL |
81 | END_GOT |
82 | ||
83 | /* | |
f35f3582 JVB |
84 | * The Hard Reset Configuration Word (HRCW) table is in the first 64 |
85 | * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 | |
86 | * times so the processor can fetch it out of flash whether the flash | |
87 | * is 8, 16, 32, or 64 bits wide (hardware trickery). | |
f046ccd1 | 88 | */ |
f046ccd1 EL |
89 | .text |
90 | #define _HRCW_TABLE_ENTRY(w) \ | |
91 | .fill 8,1,(((w)>>24)&0xff); \ | |
92 | .fill 8,1,(((w)>>16)&0xff); \ | |
93 | .fill 8,1,(((w)>> 8)&0xff); \ | |
94 | .fill 8,1,(((w) )&0xff) | |
95 | ||
6d0f6bcf JCPV |
96 | _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) |
97 | _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) | |
f046ccd1 | 98 | |
f35f3582 JVB |
99 | /* |
100 | * Magic number and version string - put it after the HRCW since it | |
101 | * cannot be first in flash like it is in many other processors. | |
102 | */ | |
103 | .long 0x27051956 /* U-Boot Magic Number */ | |
104 | ||
105 | .globl version_string | |
106 | version_string: | |
107 | .ascii U_BOOT_VERSION | |
108 | .ascii " (", __DATE__, " - ", __TIME__, ")" | |
109 | .ascii " ", CONFIG_IDENT_STRING, "\0" | |
110 | ||
f046ccd1 | 111 | |
f046ccd1 EL |
112 | #ifndef CONFIG_DEFAULT_IMMR |
113 | #error CONFIG_DEFAULT_IMMR must be defined | |
6d0f6bcf JCPV |
114 | #endif /* CONFIG_SYS_DEFAULT_IMMR */ |
115 | #ifndef CONFIG_SYS_IMMR | |
116 | #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR | |
117 | #endif /* CONFIG_SYS_IMMR */ | |
f046ccd1 EL |
118 | |
119 | /* | |
120 | * After configuration, a system reset exception is executed using the | |
121 | * vector at offset 0x100 relative to the base set by MSR[IP]. If | |
122 | * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the | |
123 | * base address is 0xfff00000. In the case of a Power On Reset or Hard | |
124 | * Reset, the value of MSR[IP] is determined by the CIP field in the | |
125 | * HRCW. | |
126 | * | |
127 | * Other bits in the HRCW set up the Base Address and Port Size in BR0. | |
128 | * This determines the location of the boot ROM (flash or EPROM) in the | |
129 | * processor's address space at boot time. As long as the HRCW is set up | |
130 | * so that we eventually end up executing the code below when the | |
131 | * processor executes the reset exception, the actual values used should | |
132 | * not matter. | |
133 | * | |
134 | * Once we have got here, the address mask in OR0 is cleared so that the | |
135 | * bottom 32K of the boot ROM is effectively repeated all throughout the | |
136 | * processor's address space, after which we can jump to the absolute | |
137 | * address at which the boot ROM was linked at compile time, and proceed | |
138 | * to initialise the memory controller without worrying if the rug will | |
139 | * be pulled out from under us, so to speak (it will be fine as long as | |
140 | * we configure BR0 with the same boot ROM link address). | |
141 | */ | |
142 | . = EXC_OFF_SYS_RESET | |
143 | ||
144 | .globl _start | |
145 | _start: /* time t 0 */ | |
146 | li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ | |
147 | nop | |
148 | b boot_cold | |
149 | ||
150 | . = EXC_OFF_SYS_RESET + 0x10 | |
151 | ||
152 | .globl _start_warm | |
de1d0a69 | 153 | _start_warm: |
f046ccd1 EL |
154 | li r21, BOOTFLAG_WARM /* Software reboot */ |
155 | b boot_warm | |
156 | ||
157 | ||
158 | boot_cold: /* time t 3 */ | |
159 | lis r4, CONFIG_DEFAULT_IMMR@h | |
160 | nop | |
161 | boot_warm: /* time t 5 */ | |
162 | mfmsr r5 /* save msr contents */ | |
6d0f6bcf JCPV |
163 | lis r3, CONFIG_SYS_IMMR@h |
164 | ori r3, r3, CONFIG_SYS_IMMR@l | |
f046ccd1 | 165 | stw r3, IMMRBAR(r4) |
de1d0a69 | 166 | |
f046ccd1 EL |
167 | /* Initialise the E300 processor core */ |
168 | /*------------------------------------------*/ | |
de1d0a69 | 169 | |
fa7b1c07 LS |
170 | #ifdef CONFIG_NAND_SPL |
171 | /* The FCM begins execution after only the first page | |
172 | * is loaded. Wait for the rest before branching | |
173 | * to another flash page. | |
174 | */ | |
175 | addi r7, r3, 0x50b0 | |
176 | 1: dcbi 0, r7 | |
177 | lwz r6, 0(r7) | |
178 | andi. r6, r6, 1 | |
179 | beq 1b | |
180 | #endif | |
181 | ||
f046ccd1 | 182 | bl init_e300_core |
de1d0a69 | 183 | |
6d0f6bcf | 184 | #ifdef CONFIG_SYS_FLASHBOOT |
f046ccd1 EL |
185 | |
186 | /* Inflate flash location so it appears everywhere, calculate */ | |
187 | /* the absolute address in final location of the FLASH, jump */ | |
188 | /* there and deflate the flash size back to minimal size */ | |
189 | /*------------------------------------------------------------*/ | |
190 | bl map_flash_by_law1 | |
6d0f6bcf JCPV |
191 | lis r4, (CONFIG_SYS_MONITOR_BASE)@h |
192 | ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l | |
f046ccd1 EL |
193 | addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET |
194 | mtlr r5 | |
195 | blr | |
196 | in_flash: | |
197 | #if 1 /* Remapping flash with LAW0. */ | |
198 | bl remap_flash_by_law0 | |
199 | #endif | |
6d0f6bcf | 200 | #endif /* CONFIG_SYS_FLASHBOOT */ |
f046ccd1 | 201 | |
2688e2f9 KG |
202 | /* setup the bats */ |
203 | bl setup_bats | |
204 | sync | |
205 | ||
206 | /* | |
207 | * Cache must be enabled here for stack-in-cache trick. | |
208 | * This means we need to enable the BATS. | |
209 | * This means: | |
210 | * 1) for the EVB, original gt regs need to be mapped | |
211 | * 2) need to have an IBAT for the 0xf region, | |
212 | * we are running there! | |
213 | * Cache should be turned on after BATs, since by default | |
214 | * everything is write-through. | |
215 | * The init-mem BAT can be reused after reloc. The old | |
216 | * gt-regs BAT can be reused after board_init_f calls | |
217 | * board_early_init_f (EVB only). | |
218 | */ | |
219 | /* enable address translation */ | |
220 | bl enable_addr_trans | |
221 | sync | |
222 | ||
6eb2a44e | 223 | /* enable the data cache */ |
2688e2f9 KG |
224 | bl dcache_enable |
225 | sync | |
6d0f6bcf | 226 | #ifdef CONFIG_SYS_INIT_RAM_LOCK |
2688e2f9 KG |
227 | bl lock_ram_in_cache |
228 | sync | |
229 | #endif | |
230 | ||
231 | /* set up the stack pointer in our newly created | |
232 | * cache-ram (r1) */ | |
6d0f6bcf JCPV |
233 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h |
234 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l | |
2688e2f9 KG |
235 | |
236 | li r0, 0 /* Make room for stack frame header and */ | |
237 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
238 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
239 | ||
f046ccd1 EL |
240 | |
241 | /* let the C-code set up the rest */ | |
2688e2f9 | 242 | /* */ |
f046ccd1 EL |
243 | /* Be careful to keep code relocatable & stack humble */ |
244 | /*------------------------------------------------------*/ | |
245 | ||
246 | GET_GOT /* initialize GOT access */ | |
247 | ||
248 | /* r3: IMMR */ | |
6d0f6bcf | 249 | lis r3, CONFIG_SYS_IMMR@h |
f046ccd1 EL |
250 | /* run low-level CPU init code (in Flash)*/ |
251 | bl cpu_init_f | |
252 | ||
253 | /* r3: BOOTFLAG */ | |
254 | mr r3, r21 | |
255 | /* run 1st part of board init code (in Flash)*/ | |
256 | bl board_init_f | |
257 | ||
e4c09508 | 258 | #ifndef CONFIG_NAND_SPL |
f046ccd1 EL |
259 | /* |
260 | * Vector Table | |
261 | */ | |
262 | ||
263 | .globl _start_of_vectors | |
264 | _start_of_vectors: | |
265 | ||
266 | /* Machine check */ | |
267 | STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) | |
268 | ||
269 | /* Data Storage exception. */ | |
270 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
271 | ||
272 | /* Instruction Storage exception. */ | |
273 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
274 | ||
275 | /* External Interrupt exception. */ | |
276 | #ifndef FIXME | |
277 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
de1d0a69 | 278 | #endif |
f046ccd1 EL |
279 | |
280 | /* Alignment exception. */ | |
281 | . = 0x600 | |
282 | Alignment: | |
02032e8f | 283 | EXCEPTION_PROLOG(SRR0, SRR1) |
f046ccd1 EL |
284 | mfspr r4,DAR |
285 | stw r4,_DAR(r21) | |
286 | mfspr r5,DSISR | |
287 | stw r5,_DSISR(r21) | |
288 | addi r3,r1,STACK_FRAME_OVERHEAD | |
289 | li r20,MSR_KERNEL | |
290 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
291 | rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ | |
292 | lwz r6,GOT(transfer_to_handler) | |
293 | mtlr r6 | |
294 | blrl | |
295 | .L_Alignment: | |
296 | .long AlignmentException - _start + EXC_OFF_SYS_RESET | |
297 | .long int_return - _start + EXC_OFF_SYS_RESET | |
298 | ||
299 | /* Program check exception */ | |
300 | . = 0x700 | |
301 | ProgramCheck: | |
02032e8f | 302 | EXCEPTION_PROLOG(SRR0, SRR1) |
f046ccd1 EL |
303 | addi r3,r1,STACK_FRAME_OVERHEAD |
304 | li r20,MSR_KERNEL | |
305 | rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ | |
306 | rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ | |
307 | lwz r6,GOT(transfer_to_handler) | |
308 | mtlr r6 | |
309 | blrl | |
310 | .L_ProgramCheck: | |
311 | .long ProgramCheckException - _start + EXC_OFF_SYS_RESET | |
312 | .long int_return - _start + EXC_OFF_SYS_RESET | |
313 | ||
314 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
315 | ||
316 | /* I guess we could implement decrementer, and may have | |
317 | * to someday for timekeeping. | |
318 | */ | |
319 | STD_EXCEPTION(0x900, Decrementer, timer_interrupt) | |
320 | ||
321 | STD_EXCEPTION(0xa00, Trap_0a, UnknownException) | |
322 | STD_EXCEPTION(0xb00, Trap_0b, UnknownException) | |
323 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) | |
324 | STD_EXCEPTION(0xd00, SingleStep, UnknownException) | |
325 | ||
326 | STD_EXCEPTION(0xe00, Trap_0e, UnknownException) | |
327 | STD_EXCEPTION(0xf00, Trap_0f, UnknownException) | |
328 | ||
329 | STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) | |
330 | STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) | |
331 | STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) | |
332 | #ifdef DEBUG | |
333 | . = 0x1300 | |
334 | /* | |
335 | * This exception occurs when the program counter matches the | |
336 | * Instruction Address Breakpoint Register (IABR). | |
337 | * | |
338 | * I want the cpu to halt if this occurs so I can hunt around | |
339 | * with the debugger and look at things. | |
340 | * | |
341 | * When DEBUG is defined, both machine check enable (in the MSR) | |
342 | * and checkstop reset enable (in the reset mode register) are | |
343 | * turned off and so a checkstop condition will result in the cpu | |
344 | * halting. | |
345 | * | |
346 | * I force the cpu into a checkstop condition by putting an illegal | |
347 | * instruction here (at least this is the theory). | |
348 | * | |
349 | * well - that didnt work, so just do an infinite loop! | |
350 | */ | |
351 | 1: b 1b | |
352 | #else | |
353 | STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) | |
354 | #endif | |
355 | STD_EXCEPTION(0x1400, SMI, UnknownException) | |
356 | ||
357 | STD_EXCEPTION(0x1500, Trap_15, UnknownException) | |
358 | STD_EXCEPTION(0x1600, Trap_16, UnknownException) | |
359 | STD_EXCEPTION(0x1700, Trap_17, UnknownException) | |
360 | STD_EXCEPTION(0x1800, Trap_18, UnknownException) | |
361 | STD_EXCEPTION(0x1900, Trap_19, UnknownException) | |
362 | STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) | |
363 | STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) | |
364 | STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) | |
365 | STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) | |
366 | STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) | |
367 | STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) | |
368 | STD_EXCEPTION(0x2000, Trap_20, UnknownException) | |
369 | STD_EXCEPTION(0x2100, Trap_21, UnknownException) | |
370 | STD_EXCEPTION(0x2200, Trap_22, UnknownException) | |
371 | STD_EXCEPTION(0x2300, Trap_23, UnknownException) | |
372 | STD_EXCEPTION(0x2400, Trap_24, UnknownException) | |
373 | STD_EXCEPTION(0x2500, Trap_25, UnknownException) | |
374 | STD_EXCEPTION(0x2600, Trap_26, UnknownException) | |
375 | STD_EXCEPTION(0x2700, Trap_27, UnknownException) | |
376 | STD_EXCEPTION(0x2800, Trap_28, UnknownException) | |
377 | STD_EXCEPTION(0x2900, Trap_29, UnknownException) | |
378 | STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) | |
379 | STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) | |
380 | STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) | |
381 | STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) | |
382 | STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) | |
383 | STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) | |
384 | ||
385 | ||
386 | .globl _end_of_vectors | |
387 | _end_of_vectors: | |
388 | ||
389 | . = 0x3000 | |
390 | ||
391 | /* | |
392 | * This code finishes saving the registers to the exception frame | |
393 | * and jumps to the appropriate handler for the exception. | |
394 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
395 | */ | |
396 | .globl transfer_to_handler | |
397 | transfer_to_handler: | |
398 | stw r22,_NIP(r21) | |
399 | lis r22,MSR_POW@h | |
400 | andc r23,r23,r22 | |
401 | stw r23,_MSR(r21) | |
402 | SAVE_GPR(7, r21) | |
403 | SAVE_4GPRS(8, r21) | |
404 | SAVE_8GPRS(12, r21) | |
405 | SAVE_8GPRS(24, r21) | |
406 | mflr r23 | |
407 | andi. r24,r23,0x3f00 /* get vector offset */ | |
408 | stw r24,TRAP(r21) | |
409 | li r22,0 | |
410 | stw r22,RESULT(r21) | |
411 | lwz r24,0(r23) /* virtual address of handler */ | |
412 | lwz r23,4(r23) /* where to go when done */ | |
413 | mtspr SRR0,r24 | |
414 | mtspr SRR1,r20 | |
415 | mtlr r23 | |
416 | SYNC | |
417 | rfi /* jump to handler, enable MMU */ | |
418 | ||
419 | int_return: | |
420 | mfmsr r28 /* Disable interrupts */ | |
421 | li r4,0 | |
422 | ori r4,r4,MSR_EE | |
423 | andc r28,r28,r4 | |
424 | SYNC /* Some chip revs need this... */ | |
425 | mtmsr r28 | |
426 | SYNC | |
427 | lwz r2,_CTR(r1) | |
428 | lwz r0,_LINK(r1) | |
429 | mtctr r2 | |
430 | mtlr r0 | |
431 | lwz r2,_XER(r1) | |
432 | lwz r0,_CCR(r1) | |
433 | mtspr XER,r2 | |
434 | mtcrf 0xFF,r0 | |
435 | REST_10GPRS(3, r1) | |
436 | REST_10GPRS(13, r1) | |
437 | REST_8GPRS(23, r1) | |
438 | REST_GPR(31, r1) | |
439 | lwz r2,_NIP(r1) /* Restore environment */ | |
440 | lwz r0,_MSR(r1) | |
441 | mtspr SRR0,r2 | |
442 | mtspr SRR1,r0 | |
443 | lwz r0,GPR0(r1) | |
444 | lwz r2,GPR2(r1) | |
445 | lwz r1,GPR1(r1) | |
446 | SYNC | |
447 | rfi | |
e4c09508 | 448 | #endif /* !CONFIG_NAND_SPL */ |
f046ccd1 EL |
449 | |
450 | /* | |
451 | * This code initialises the E300 processor core | |
452 | * (conforms to PowerPC 603e spec) | |
453 | * Note: expects original MSR contents to be in r5. | |
454 | */ | |
455 | .globl init_e300_core | |
456 | init_e300_core: /* time t 10 */ | |
457 | /* Initialize machine status; enable machine check interrupt */ | |
458 | /*-----------------------------------------------------------*/ | |
459 | ||
460 | li r3, MSR_KERNEL /* Set ME and RI flags */ | |
461 | rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ | |
462 | #ifdef DEBUG | |
463 | rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ | |
464 | #endif | |
465 | SYNC /* Some chip revs need this... */ | |
466 | mtmsr r3 | |
467 | SYNC | |
468 | mtspr SRR1, r3 /* Make SRR1 match MSR */ | |
469 | ||
470 | ||
6d0f6bcf | 471 | lis r3, CONFIG_SYS_IMMR@h |
f046ccd1 EL |
472 | #if defined(CONFIG_WATCHDOG) |
473 | /* Initialise the Wathcdog values and reset it (if req) */ | |
474 | /*------------------------------------------------------*/ | |
6d0f6bcf | 475 | lis r4, CONFIG_SYS_WATCHDOG_VALUE |
f046ccd1 EL |
476 | ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) |
477 | stw r4, SWCRR(r3) | |
de1d0a69 | 478 | |
f046ccd1 | 479 | /* and reset it */ |
de1d0a69 | 480 | |
f046ccd1 EL |
481 | li r4, 0x556C |
482 | sth r4, SWSRR@l(r3) | |
f6db9456 | 483 | li r4, -0x55C7 |
f046ccd1 EL |
484 | sth r4, SWSRR@l(r3) |
485 | #else | |
486 | /* Disable Wathcdog */ | |
487 | /*-------------------*/ | |
ec00c335 KG |
488 | lwz r4, SWCRR(r3) |
489 | /* Check to see if its enabled for disabling | |
490 | once disabled by SW you can't re-enable */ | |
491 | andi. r4, r4, 0x4 | |
492 | beq 1f | |
f046ccd1 EL |
493 | xor r4, r4, r4 |
494 | stw r4, SWCRR(r3) | |
ec00c335 | 495 | 1: |
f046ccd1 EL |
496 | #endif /* CONFIG_WATCHDOG */ |
497 | ||
46497056 NS |
498 | #if defined(CONFIG_MASK_AER_AO) |
499 | /* Write the Arbiter Event Enable to mask Address Only traps. */ | |
500 | /* This prevents the dcbz instruction from being trapped when */ | |
501 | /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ | |
502 | /* COHERENCY bit is set in the WIMG bits, which is often */ | |
503 | /* needed for PCI operation. */ | |
504 | lwz r4, 0x0808(r3) | |
505 | rlwinm r0, r4, 0, ~AER_AO | |
506 | stw r0, 0x0808(r3) | |
507 | #endif /* CONFIG_MASK_AER_AO */ | |
508 | ||
f046ccd1 EL |
509 | /* Initialize the Hardware Implementation-dependent Registers */ |
510 | /* HID0 also contains cache control */ | |
6eb2a44e | 511 | /* - force invalidation of data and instruction caches */ |
f046ccd1 EL |
512 | /*------------------------------------------------------*/ |
513 | ||
6d0f6bcf JCPV |
514 | lis r3, CONFIG_SYS_HID0_INIT@h |
515 | ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l | |
f046ccd1 EL |
516 | SYNC |
517 | mtspr HID0, r3 | |
518 | ||
6d0f6bcf JCPV |
519 | lis r3, CONFIG_SYS_HID0_FINAL@h |
520 | ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l | |
f046ccd1 EL |
521 | SYNC |
522 | mtspr HID0, r3 | |
523 | ||
6d0f6bcf JCPV |
524 | lis r3, CONFIG_SYS_HID2@h |
525 | ori r3, r3, CONFIG_SYS_HID2@l | |
f046ccd1 EL |
526 | SYNC |
527 | mtspr HID2, r3 | |
528 | ||
f046ccd1 EL |
529 | /* Done! */ |
530 | /*------------------------------*/ | |
de1d0a69 | 531 | blr |
f046ccd1 | 532 | |
2688e2f9 KG |
533 | /* setup_bats - set them up to some initial state */ |
534 | .globl setup_bats | |
535 | setup_bats: | |
536 | addis r0, r0, 0x0000 | |
537 | ||
538 | /* IBAT 0 */ | |
6d0f6bcf JCPV |
539 | addis r4, r0, CONFIG_SYS_IBAT0L@h |
540 | ori r4, r4, CONFIG_SYS_IBAT0L@l | |
541 | addis r3, r0, CONFIG_SYS_IBAT0U@h | |
542 | ori r3, r3, CONFIG_SYS_IBAT0U@l | |
2688e2f9 KG |
543 | mtspr IBAT0L, r4 |
544 | mtspr IBAT0U, r3 | |
2688e2f9 KG |
545 | |
546 | /* DBAT 0 */ | |
6d0f6bcf JCPV |
547 | addis r4, r0, CONFIG_SYS_DBAT0L@h |
548 | ori r4, r4, CONFIG_SYS_DBAT0L@l | |
549 | addis r3, r0, CONFIG_SYS_DBAT0U@h | |
550 | ori r3, r3, CONFIG_SYS_DBAT0U@l | |
2688e2f9 KG |
551 | mtspr DBAT0L, r4 |
552 | mtspr DBAT0U, r3 | |
2688e2f9 KG |
553 | |
554 | /* IBAT 1 */ | |
6d0f6bcf JCPV |
555 | addis r4, r0, CONFIG_SYS_IBAT1L@h |
556 | ori r4, r4, CONFIG_SYS_IBAT1L@l | |
557 | addis r3, r0, CONFIG_SYS_IBAT1U@h | |
558 | ori r3, r3, CONFIG_SYS_IBAT1U@l | |
2688e2f9 KG |
559 | mtspr IBAT1L, r4 |
560 | mtspr IBAT1U, r3 | |
2688e2f9 KG |
561 | |
562 | /* DBAT 1 */ | |
6d0f6bcf JCPV |
563 | addis r4, r0, CONFIG_SYS_DBAT1L@h |
564 | ori r4, r4, CONFIG_SYS_DBAT1L@l | |
565 | addis r3, r0, CONFIG_SYS_DBAT1U@h | |
566 | ori r3, r3, CONFIG_SYS_DBAT1U@l | |
2688e2f9 KG |
567 | mtspr DBAT1L, r4 |
568 | mtspr DBAT1U, r3 | |
2688e2f9 KG |
569 | |
570 | /* IBAT 2 */ | |
6d0f6bcf JCPV |
571 | addis r4, r0, CONFIG_SYS_IBAT2L@h |
572 | ori r4, r4, CONFIG_SYS_IBAT2L@l | |
573 | addis r3, r0, CONFIG_SYS_IBAT2U@h | |
574 | ori r3, r3, CONFIG_SYS_IBAT2U@l | |
2688e2f9 KG |
575 | mtspr IBAT2L, r4 |
576 | mtspr IBAT2U, r3 | |
2688e2f9 KG |
577 | |
578 | /* DBAT 2 */ | |
6d0f6bcf JCPV |
579 | addis r4, r0, CONFIG_SYS_DBAT2L@h |
580 | ori r4, r4, CONFIG_SYS_DBAT2L@l | |
581 | addis r3, r0, CONFIG_SYS_DBAT2U@h | |
582 | ori r3, r3, CONFIG_SYS_DBAT2U@l | |
2688e2f9 KG |
583 | mtspr DBAT2L, r4 |
584 | mtspr DBAT2U, r3 | |
2688e2f9 KG |
585 | |
586 | /* IBAT 3 */ | |
6d0f6bcf JCPV |
587 | addis r4, r0, CONFIG_SYS_IBAT3L@h |
588 | ori r4, r4, CONFIG_SYS_IBAT3L@l | |
589 | addis r3, r0, CONFIG_SYS_IBAT3U@h | |
590 | ori r3, r3, CONFIG_SYS_IBAT3U@l | |
2688e2f9 KG |
591 | mtspr IBAT3L, r4 |
592 | mtspr IBAT3U, r3 | |
2688e2f9 KG |
593 | |
594 | /* DBAT 3 */ | |
6d0f6bcf JCPV |
595 | addis r4, r0, CONFIG_SYS_DBAT3L@h |
596 | ori r4, r4, CONFIG_SYS_DBAT3L@l | |
597 | addis r3, r0, CONFIG_SYS_DBAT3U@h | |
598 | ori r3, r3, CONFIG_SYS_DBAT3U@l | |
2688e2f9 KG |
599 | mtspr DBAT3L, r4 |
600 | mtspr DBAT3U, r3 | |
2688e2f9 | 601 | |
31d82672 | 602 | #ifdef CONFIG_HIGH_BATS |
2688e2f9 | 603 | /* IBAT 4 */ |
6d0f6bcf JCPV |
604 | addis r4, r0, CONFIG_SYS_IBAT4L@h |
605 | ori r4, r4, CONFIG_SYS_IBAT4L@l | |
606 | addis r3, r0, CONFIG_SYS_IBAT4U@h | |
607 | ori r3, r3, CONFIG_SYS_IBAT4U@l | |
2688e2f9 KG |
608 | mtspr IBAT4L, r4 |
609 | mtspr IBAT4U, r3 | |
2688e2f9 KG |
610 | |
611 | /* DBAT 4 */ | |
6d0f6bcf JCPV |
612 | addis r4, r0, CONFIG_SYS_DBAT4L@h |
613 | ori r4, r4, CONFIG_SYS_DBAT4L@l | |
614 | addis r3, r0, CONFIG_SYS_DBAT4U@h | |
615 | ori r3, r3, CONFIG_SYS_DBAT4U@l | |
2688e2f9 KG |
616 | mtspr DBAT4L, r4 |
617 | mtspr DBAT4U, r3 | |
2688e2f9 KG |
618 | |
619 | /* IBAT 5 */ | |
6d0f6bcf JCPV |
620 | addis r4, r0, CONFIG_SYS_IBAT5L@h |
621 | ori r4, r4, CONFIG_SYS_IBAT5L@l | |
622 | addis r3, r0, CONFIG_SYS_IBAT5U@h | |
623 | ori r3, r3, CONFIG_SYS_IBAT5U@l | |
2688e2f9 KG |
624 | mtspr IBAT5L, r4 |
625 | mtspr IBAT5U, r3 | |
2688e2f9 KG |
626 | |
627 | /* DBAT 5 */ | |
6d0f6bcf JCPV |
628 | addis r4, r0, CONFIG_SYS_DBAT5L@h |
629 | ori r4, r4, CONFIG_SYS_DBAT5L@l | |
630 | addis r3, r0, CONFIG_SYS_DBAT5U@h | |
631 | ori r3, r3, CONFIG_SYS_DBAT5U@l | |
2688e2f9 KG |
632 | mtspr DBAT5L, r4 |
633 | mtspr DBAT5U, r3 | |
2688e2f9 KG |
634 | |
635 | /* IBAT 6 */ | |
6d0f6bcf JCPV |
636 | addis r4, r0, CONFIG_SYS_IBAT6L@h |
637 | ori r4, r4, CONFIG_SYS_IBAT6L@l | |
638 | addis r3, r0, CONFIG_SYS_IBAT6U@h | |
639 | ori r3, r3, CONFIG_SYS_IBAT6U@l | |
2688e2f9 KG |
640 | mtspr IBAT6L, r4 |
641 | mtspr IBAT6U, r3 | |
2688e2f9 KG |
642 | |
643 | /* DBAT 6 */ | |
6d0f6bcf JCPV |
644 | addis r4, r0, CONFIG_SYS_DBAT6L@h |
645 | ori r4, r4, CONFIG_SYS_DBAT6L@l | |
646 | addis r3, r0, CONFIG_SYS_DBAT6U@h | |
647 | ori r3, r3, CONFIG_SYS_DBAT6U@l | |
2688e2f9 KG |
648 | mtspr DBAT6L, r4 |
649 | mtspr DBAT6U, r3 | |
2688e2f9 KG |
650 | |
651 | /* IBAT 7 */ | |
6d0f6bcf JCPV |
652 | addis r4, r0, CONFIG_SYS_IBAT7L@h |
653 | ori r4, r4, CONFIG_SYS_IBAT7L@l | |
654 | addis r3, r0, CONFIG_SYS_IBAT7U@h | |
655 | ori r3, r3, CONFIG_SYS_IBAT7U@l | |
2688e2f9 KG |
656 | mtspr IBAT7L, r4 |
657 | mtspr IBAT7U, r3 | |
2688e2f9 KG |
658 | |
659 | /* DBAT 7 */ | |
6d0f6bcf JCPV |
660 | addis r4, r0, CONFIG_SYS_DBAT7L@h |
661 | ori r4, r4, CONFIG_SYS_DBAT7L@l | |
662 | addis r3, r0, CONFIG_SYS_DBAT7U@h | |
663 | ori r3, r3, CONFIG_SYS_DBAT7U@l | |
2688e2f9 KG |
664 | mtspr DBAT7L, r4 |
665 | mtspr DBAT7U, r3 | |
2688e2f9 KG |
666 | #endif |
667 | ||
e4c09508 SW |
668 | isync |
669 | ||
670 | /* invalidate all tlb's | |
671 | * | |
672 | * From the 603e User Manual: "The 603e provides the ability to | |
673 | * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) | |
674 | * instruction invalidates the TLB entry indexed by the EA, and | |
675 | * operates on both the instruction and data TLBs simultaneously | |
676 | * invalidating four TLB entries (both sets in each TLB). The | |
677 | * index corresponds to bits 15-19 of the EA. To invalidate all | |
678 | * entries within both TLBs, 32 tlbie instructions should be | |
679 | * issued, incrementing this field by one each time." | |
680 | * | |
681 | * "Note that the tlbia instruction is not implemented on the | |
682 | * 603e." | |
683 | * | |
684 | * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 | |
685 | * incrementing by 0x1000 each time. The code below is sort of | |
686 | * based on code in "flush_tlbs" from arch/ppc/kernel/head.S | |
687 | * | |
2688e2f9 KG |
688 | */ |
689 | lis r3, 0 | |
690 | lis r5, 2 | |
691 | ||
692 | 1: | |
693 | tlbie r3 | |
694 | addi r3, r3, 0x1000 | |
695 | cmp 0, 0, r3, r5 | |
696 | blt 1b | |
697 | ||
698 | blr | |
699 | ||
700 | .globl enable_addr_trans | |
701 | enable_addr_trans: | |
702 | /* enable address translation */ | |
703 | mfmsr r5 | |
704 | ori r5, r5, (MSR_IR | MSR_DR) | |
705 | mtmsr r5 | |
706 | isync | |
707 | blr | |
708 | ||
709 | .globl disable_addr_trans | |
710 | disable_addr_trans: | |
711 | /* disable address translation */ | |
712 | mflr r4 | |
713 | mfmsr r3 | |
714 | andi. r0, r3, (MSR_IR | MSR_DR) | |
715 | beqlr | |
716 | andc r3, r3, r0 | |
717 | mtspr SRR0, r4 | |
718 | mtspr SRR1, r3 | |
719 | rfi | |
720 | ||
f046ccd1 EL |
721 | /* Cache functions. |
722 | * | |
723 | * Note: requires that all cache bits in | |
724 | * HID0 are in the low half word. | |
725 | */ | |
726 | .globl icache_enable | |
727 | icache_enable: | |
728 | mfspr r3, HID0 | |
729 | ori r3, r3, HID0_ICE | |
6eb2a44e | 730 | li r4, HID0_ICFI|HID0_ILOCK |
f046ccd1 EL |
731 | andc r3, r3, r4 |
732 | ori r4, r3, HID0_ICFI | |
733 | isync | |
734 | mtspr HID0, r4 /* sets enable and invalidate, clears lock */ | |
735 | isync | |
736 | mtspr HID0, r3 /* clears invalidate */ | |
737 | blr | |
738 | ||
739 | .globl icache_disable | |
740 | icache_disable: | |
741 | mfspr r3, HID0 | |
742 | lis r4, 0 | |
6eb2a44e | 743 | ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK |
f046ccd1 | 744 | andc r3, r3, r4 |
f046ccd1 | 745 | isync |
6eb2a44e | 746 | mtspr HID0, r3 /* clears invalidate, enable and lock */ |
f046ccd1 EL |
747 | blr |
748 | ||
749 | .globl icache_status | |
750 | icache_status: | |
751 | mfspr r3, HID0 | |
a7c66ad2 | 752 | rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 |
f046ccd1 EL |
753 | blr |
754 | ||
755 | .globl dcache_enable | |
756 | dcache_enable: | |
757 | mfspr r3, HID0 | |
2688e2f9 KG |
758 | li r5, HID0_DCFI|HID0_DLOCK |
759 | andc r3, r3, r5 | |
2688e2f9 | 760 | ori r3, r3, HID0_DCE |
f046ccd1 | 761 | sync |
6eb2a44e | 762 | mtspr HID0, r3 /* enable, no invalidate */ |
f046ccd1 EL |
763 | blr |
764 | ||
765 | .globl dcache_disable | |
766 | dcache_disable: | |
6eb2a44e NS |
767 | mflr r4 |
768 | bl flush_dcache /* uses r3 and r5 */ | |
f046ccd1 | 769 | mfspr r3, HID0 |
6eb2a44e NS |
770 | li r5, HID0_DCE|HID0_DLOCK |
771 | andc r3, r3, r5 | |
772 | ori r5, r3, HID0_DCFI | |
f046ccd1 | 773 | sync |
6eb2a44e | 774 | mtspr HID0, r5 /* sets invalidate, clears enable and lock */ |
f046ccd1 EL |
775 | sync |
776 | mtspr HID0, r3 /* clears invalidate */ | |
6eb2a44e | 777 | mtlr r4 |
f046ccd1 EL |
778 | blr |
779 | ||
780 | .globl dcache_status | |
781 | dcache_status: | |
782 | mfspr r3, HID0 | |
a7c66ad2 | 783 | rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 |
f046ccd1 EL |
784 | blr |
785 | ||
6eb2a44e NS |
786 | .globl flush_dcache |
787 | flush_dcache: | |
788 | lis r3, 0 | |
6d0f6bcf | 789 | lis r5, CONFIG_SYS_CACHELINE_SIZE |
6eb2a44e NS |
790 | 1: cmp 0, 1, r3, r5 |
791 | bge 2f | |
792 | lwz r5, 0(r3) | |
6d0f6bcf | 793 | lis r5, CONFIG_SYS_CACHELINE_SIZE |
6eb2a44e NS |
794 | addi r3, r3, 0x4 |
795 | b 1b | |
796 | 2: blr | |
797 | ||
f046ccd1 EL |
798 | .globl get_pvr |
799 | get_pvr: | |
800 | mfspr r3, PVR | |
801 | blr | |
802 | ||
90f30a71 DL |
803 | .globl ppcDWstore |
804 | ppcDWstore: | |
805 | lfd 1, 0(r4) | |
806 | stfd 1, 0(r3) | |
807 | blr | |
808 | ||
809 | .globl ppcDWload | |
810 | ppcDWload: | |
811 | lfd 1, 0(r3) | |
812 | stfd 1, 0(r4) | |
813 | blr | |
814 | ||
f046ccd1 EL |
815 | /*-------------------------------------------------------------------*/ |
816 | ||
817 | /* | |
818 | * void relocate_code (addr_sp, gd, addr_moni) | |
819 | * | |
820 | * This "function" does not return, instead it continues in RAM | |
821 | * after relocating the monitor code. | |
822 | * | |
823 | * r3 = dest | |
824 | * r4 = src | |
825 | * r5 = length in bytes | |
826 | * r6 = cachelinesize | |
827 | */ | |
828 | .globl relocate_code | |
829 | relocate_code: | |
830 | mr r1, r3 /* Set new stack pointer */ | |
831 | mr r9, r4 /* Save copy of Global Data pointer */ | |
832 | mr r10, r5 /* Save copy of Destination Address */ | |
833 | ||
834 | mr r3, r5 /* Destination Address */ | |
6d0f6bcf JCPV |
835 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
836 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
e4c09508 | 837 | lwz r5, GOT(__bss_start) |
f046ccd1 | 838 | sub r5, r5, r4 |
6d0f6bcf | 839 | li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ |
f046ccd1 EL |
840 | |
841 | /* | |
842 | * Fix GOT pointer: | |
843 | * | |
6d0f6bcf | 844 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) |
f046ccd1 EL |
845 | * + Destination Address |
846 | * | |
847 | * Offset: | |
848 | */ | |
849 | sub r15, r10, r4 | |
850 | ||
851 | /* First our own GOT */ | |
852 | add r14, r14, r15 | |
853 | /* then the one used by the C code */ | |
854 | add r30, r30, r15 | |
855 | ||
856 | /* | |
857 | * Now relocate code | |
858 | */ | |
859 | ||
860 | cmplw cr1,r3,r4 | |
861 | addi r0,r5,3 | |
862 | srwi. r0,r0,2 | |
863 | beq cr1,4f /* In place copy is not necessary */ | |
864 | beq 7f /* Protect against 0 count */ | |
865 | mtctr r0 | |
866 | bge cr1,2f | |
867 | la r8,-4(r4) | |
868 | la r7,-4(r3) | |
869 | ||
870 | /* copy */ | |
871 | 1: lwzu r0,4(r8) | |
872 | stwu r0,4(r7) | |
873 | bdnz 1b | |
874 | ||
875 | addi r0,r5,3 | |
876 | srwi. r0,r0,2 | |
877 | mtctr r0 | |
878 | la r8,-4(r4) | |
879 | la r7,-4(r3) | |
de1d0a69 JL |
880 | |
881 | /* and compare */ | |
f046ccd1 EL |
882 | 20: lwzu r20,4(r8) |
883 | lwzu r21,4(r7) | |
884 | xor. r22, r20, r21 | |
885 | bne 30f | |
886 | bdnz 20b | |
887 | b 4f | |
888 | ||
889 | /* compare failed */ | |
890 | 30: li r3, 0 | |
891 | blr | |
892 | ||
893 | 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ | |
894 | add r8,r4,r0 | |
895 | add r7,r3,r0 | |
896 | 3: lwzu r0,-4(r8) | |
897 | stwu r0,-4(r7) | |
898 | bdnz 3b | |
f046ccd1 EL |
899 | |
900 | /* | |
901 | * Now flush the cache: note that we must start from a cache aligned | |
902 | * address. Otherwise we might miss one cache line. | |
903 | */ | |
2688e2f9 | 904 | 4: cmpwi r6,0 |
f046ccd1 | 905 | add r5,r3,r5 |
2688e2f9 | 906 | beq 7f /* Always flush prefetch queue in any case */ |
f046ccd1 EL |
907 | subi r0,r6,1 |
908 | andc r3,r3,r0 | |
f046ccd1 EL |
909 | mr r4,r3 |
910 | 5: dcbst 0,r4 | |
911 | add r4,r4,r6 | |
912 | cmplw r4,r5 | |
913 | blt 5b | |
2688e2f9 | 914 | sync /* Wait for all dcbst to complete on bus */ |
f046ccd1 EL |
915 | mr r4,r3 |
916 | 6: icbi 0,r4 | |
917 | add r4,r4,r6 | |
918 | cmplw r4,r5 | |
919 | blt 6b | |
2688e2f9 | 920 | 7: sync /* Wait for all icbi to complete on bus */ |
f046ccd1 EL |
921 | isync |
922 | ||
923 | /* | |
924 | * We are done. Do not return, instead branch to second part of board | |
925 | * initialization, now running from RAM. | |
926 | */ | |
f046ccd1 EL |
927 | addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET |
928 | mtlr r0 | |
929 | blr | |
930 | ||
931 | in_ram: | |
932 | ||
933 | /* | |
934 | * Relocation Function, r14 point to got2+0x8000 | |
935 | * | |
936 | * Adjust got2 pointers, no need to check for 0, this code | |
937 | * already puts a few entries in the table. | |
938 | */ | |
939 | li r0,__got2_entries@sectoff@l | |
940 | la r3,GOT(_GOT2_TABLE_) | |
941 | lwz r11,GOT(_GOT2_TABLE_) | |
942 | mtctr r0 | |
943 | sub r11,r3,r11 | |
944 | addi r3,r3,-4 | |
945 | 1: lwzu r0,4(r3) | |
946 | add r0,r0,r11 | |
947 | stw r0,0(r3) | |
948 | bdnz 1b | |
949 | ||
e4c09508 | 950 | #ifndef CONFIG_NAND_SPL |
f046ccd1 EL |
951 | /* |
952 | * Now adjust the fixups and the pointers to the fixups | |
953 | * in case we need to move ourselves again. | |
954 | */ | |
955 | 2: li r0,__fixup_entries@sectoff@l | |
956 | lwz r3,GOT(_FIXUP_TABLE_) | |
957 | cmpwi r0,0 | |
958 | mtctr r0 | |
959 | addi r3,r3,-4 | |
960 | beq 4f | |
961 | 3: lwzu r4,4(r3) | |
962 | lwzux r0,r4,r11 | |
963 | add r0,r0,r11 | |
964 | stw r10,0(r3) | |
965 | stw r0,0(r4) | |
966 | bdnz 3b | |
967 | 4: | |
e4c09508 SW |
968 | #endif |
969 | ||
f046ccd1 EL |
970 | clear_bss: |
971 | /* | |
972 | * Now clear BSS segment | |
973 | */ | |
974 | lwz r3,GOT(__bss_start) | |
975 | #if defined(CONFIG_HYMOD) | |
976 | /* | |
977 | * For HYMOD - the environment is the very last item in flash. | |
978 | * The real .bss stops just before environment starts, so only | |
979 | * clear up to that point. | |
980 | * | |
981 | * taken from mods for FADS board | |
982 | */ | |
983 | lwz r4,GOT(environment) | |
984 | #else | |
985 | lwz r4,GOT(_end) | |
986 | #endif | |
987 | ||
988 | cmplw 0, r3, r4 | |
989 | beq 6f | |
990 | ||
991 | li r0, 0 | |
992 | 5: | |
993 | stw r0, 0(r3) | |
994 | addi r3, r3, 4 | |
995 | cmplw 0, r3, r4 | |
996 | bne 5b | |
997 | 6: | |
998 | ||
999 | mr r3, r9 /* Global Data pointer */ | |
1000 | mr r4, r10 /* Destination Address */ | |
1001 | bl board_init_r | |
1002 | ||
e4c09508 | 1003 | #ifndef CONFIG_NAND_SPL |
f046ccd1 EL |
1004 | /* |
1005 | * Copy exception vector code to low memory | |
1006 | * | |
1007 | * r3: dest_addr | |
1008 | * r7: source address, r8: end address, r9: target address | |
1009 | */ | |
1010 | .globl trap_init | |
1011 | trap_init: | |
1012 | lwz r7, GOT(_start) | |
1013 | lwz r8, GOT(_end_of_vectors) | |
1014 | ||
1015 | li r9, 0x100 /* reset vector always at 0x100 */ | |
1016 | ||
1017 | cmplw 0, r7, r8 | |
1018 | bgelr /* return if r7>=r8 - just in case */ | |
1019 | ||
1020 | mflr r4 /* save link register */ | |
1021 | 1: | |
1022 | lwz r0, 0(r7) | |
1023 | stw r0, 0(r9) | |
1024 | addi r7, r7, 4 | |
1025 | addi r9, r9, 4 | |
1026 | cmplw 0, r7, r8 | |
1027 | bne 1b | |
1028 | ||
1029 | /* | |
1030 | * relocate `hdlr' and `int_return' entries | |
1031 | */ | |
1032 | li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET | |
1033 | li r8, Alignment - _start + EXC_OFF_SYS_RESET | |
1034 | 2: | |
1035 | bl trap_reloc | |
1036 | addi r7, r7, 0x100 /* next exception vector */ | |
1037 | cmplw 0, r7, r8 | |
1038 | blt 2b | |
1039 | ||
1040 | li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET | |
1041 | bl trap_reloc | |
1042 | ||
1043 | li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET | |
1044 | bl trap_reloc | |
1045 | ||
1046 | li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET | |
1047 | li r8, SystemCall - _start + EXC_OFF_SYS_RESET | |
1048 | 3: | |
1049 | bl trap_reloc | |
1050 | addi r7, r7, 0x100 /* next exception vector */ | |
1051 | cmplw 0, r7, r8 | |
1052 | blt 3b | |
1053 | ||
1054 | li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET | |
1055 | li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET | |
1056 | 4: | |
1057 | bl trap_reloc | |
1058 | addi r7, r7, 0x100 /* next exception vector */ | |
1059 | cmplw 0, r7, r8 | |
1060 | blt 4b | |
1061 | ||
1062 | mfmsr r3 /* now that the vectors have */ | |
1063 | lis r7, MSR_IP@h /* relocated into low memory */ | |
1064 | ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ | |
1065 | andc r3, r3, r7 /* (if it was on) */ | |
1066 | SYNC /* Some chip revs need this... */ | |
1067 | mtmsr r3 | |
1068 | SYNC | |
1069 | ||
1070 | mtlr r4 /* restore link register */ | |
1071 | blr | |
1072 | ||
1073 | /* | |
1074 | * Function: relocate entries for one exception vector | |
1075 | */ | |
1076 | trap_reloc: | |
1077 | lwz r0, 0(r7) /* hdlr ... */ | |
1078 | add r0, r0, r3 /* ... += dest_addr */ | |
1079 | stw r0, 0(r7) | |
1080 | ||
1081 | lwz r0, 4(r7) /* int_return ... */ | |
1082 | add r0, r0, r3 /* ... += dest_addr */ | |
1083 | stw r0, 4(r7) | |
1084 | ||
1085 | blr | |
e4c09508 | 1086 | #endif /* !CONFIG_NAND_SPL */ |
f046ccd1 | 1087 | |
6d0f6bcf | 1088 | #ifdef CONFIG_SYS_INIT_RAM_LOCK |
2688e2f9 KG |
1089 | lock_ram_in_cache: |
1090 | /* Allocate Initial RAM in data cache. | |
1091 | */ | |
6d0f6bcf JCPV |
1092 | lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h |
1093 | ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l | |
1094 | li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ | |
1095 | (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 | |
ade50c7f | 1096 | mtctr r4 |
2688e2f9 KG |
1097 | 1: |
1098 | dcbz r0, r3 | |
1099 | addi r3, r3, 32 | |
1100 | bdnz 1b | |
1101 | ||
1102 | /* Lock the data cache */ | |
1103 | mfspr r0, HID0 | |
6eb2a44e | 1104 | ori r0, r0, HID0_DLOCK |
2688e2f9 KG |
1105 | sync |
1106 | mtspr HID0, r0 | |
1107 | sync | |
1108 | blr | |
1109 | ||
e4c09508 | 1110 | #ifndef CONFIG_NAND_SPL |
f046ccd1 EL |
1111 | .globl unlock_ram_in_cache |
1112 | unlock_ram_in_cache: | |
1113 | /* invalidate the INIT_RAM section */ | |
6d0f6bcf JCPV |
1114 | lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h |
1115 | ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l | |
1116 | li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \ | |
1117 | (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 | |
ade50c7f | 1118 | mtctr r4 |
f046ccd1 EL |
1119 | 1: icbi r0, r3 |
1120 | dcbi r0, r3 | |
1121 | addi r3, r3, 32 | |
1122 | bdnz 1b | |
1123 | sync /* Wait for all icbi to complete on bus */ | |
1124 | isync | |
2688e2f9 KG |
1125 | |
1126 | /* Unlock the data cache and invalidate it */ | |
1127 | mfspr r3, HID0 | |
1128 | li r5, HID0_DLOCK|HID0_DCFI | |
1129 | andc r3, r3, r5 /* no invalidate, unlock */ | |
1130 | ori r5, r3, HID0_DCFI /* invalidate, unlock */ | |
6eb2a44e | 1131 | sync |
2688e2f9 | 1132 | mtspr HID0, r5 /* invalidate, unlock */ |
2688e2f9 | 1133 | sync |
6eb2a44e | 1134 | mtspr HID0, r3 /* no invalidate, unlock */ |
f046ccd1 | 1135 | blr |
e4c09508 | 1136 | #endif /* !CONFIG_NAND_SPL */ |
6d0f6bcf | 1137 | #endif /* CONFIG_SYS_INIT_RAM_LOCK */ |
f046ccd1 | 1138 | |
6d0f6bcf | 1139 | #ifdef CONFIG_SYS_FLASHBOOT |
f046ccd1 EL |
1140 | map_flash_by_law1: |
1141 | /* When booting from ROM (Flash or EPROM), clear the */ | |
1142 | /* Address Mask in OR0 so ROM appears everywhere */ | |
1143 | /*----------------------------------------------------*/ | |
6d0f6bcf | 1144 | lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ |
de1d0a69 | 1145 | lwz r4, OR0@l(r3) |
f046ccd1 | 1146 | li r5, 0x7fff /* r5 <= 0x00007FFFF */ |
de1d0a69 | 1147 | and r4, r4, r5 |
f046ccd1 EL |
1148 | stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ |
1149 | ||
1150 | /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, | |
1151 | * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] | |
1152 | * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot | |
1153 | * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is | |
1154 | * 0xFF800. From the hard resetting to here, the processor fetched and | |
1155 | * executed the instructions one by one. There is not absolutely | |
1156 | * jumping happened. Laterly, the u-boot code has to do an absolutely | |
1157 | * jumping to tell the CPU instruction fetching component what the | |
1158 | * u-boot TEXT base address is. Because the TEXT base resides in the | |
1159 | * boot ROM memory space, to garantee the code can run smoothly after | |
1160 | * that jumping, we must map in the entire boot ROM by Local Access | |
1161 | * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting | |
1162 | * address for boot ROM, such as 0xFE000000. In this case, the default | |
1163 | * LBIU Local Access Widow 0 will not cover this memory space. So, we | |
1164 | * need another window to map in it. | |
1165 | */ | |
6d0f6bcf JCPV |
1166 | lis r4, (CONFIG_SYS_FLASH_BASE)@h |
1167 | ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l | |
1168 | stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ | |
31068b7c | 1169 | |
6d0f6bcf | 1170 | /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ |
31068b7c TT |
1171 | lis r4, (0x80000012)@h |
1172 | ori r4, r4, (0x80000012)@l | |
6d0f6bcf | 1173 | li r5, CONFIG_SYS_FLASH_SIZE |
31068b7c TT |
1174 | 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ |
1175 | addi r4, r4, 1 | |
1176 | bne 1b | |
1177 | ||
f046ccd1 EL |
1178 | stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ |
1179 | blr | |
1180 | ||
1181 | /* Though all the LBIU Local Access Windows and LBC Banks will be | |
1182 | * initialized in the C code, we'd better configure boot ROM's | |
1183 | * window 0 and bank 0 correctly at here. | |
1184 | */ | |
1185 | remap_flash_by_law0: | |
1186 | /* Initialize the BR0 with the boot ROM starting address. */ | |
1187 | lwz r4, BR0(r3) | |
1188 | li r5, 0x7FFF | |
de1d0a69 | 1189 | and r4, r4, r5 |
6d0f6bcf JCPV |
1190 | lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h |
1191 | ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l | |
f046ccd1 | 1192 | or r5, r5, r4 |
6d0f6bcf | 1193 | stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ |
f046ccd1 EL |
1194 | |
1195 | lwz r4, OR0(r3) | |
6d0f6bcf | 1196 | lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) |
f046ccd1 | 1197 | or r4, r4, r5 |
31068b7c | 1198 | stw r4, OR0(r3) |
f046ccd1 | 1199 | |
6d0f6bcf JCPV |
1200 | lis r4, (CONFIG_SYS_FLASH_BASE)@h |
1201 | ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l | |
1202 | stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ | |
f046ccd1 | 1203 | |
6d0f6bcf | 1204 | /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ |
31068b7c TT |
1205 | lis r4, (0x80000012)@h |
1206 | ori r4, r4, (0x80000012)@l | |
6d0f6bcf | 1207 | li r5, CONFIG_SYS_FLASH_SIZE |
31068b7c TT |
1208 | 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ |
1209 | addi r4, r4, 1 | |
1210 | bne 1b | |
1211 | stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ | |
1212 | ||
f046ccd1 EL |
1213 | |
1214 | xor r4, r4, r4 | |
1215 | stw r4, LBLAWBAR1(r3) | |
1216 | stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ | |
1217 | blr | |
6d0f6bcf | 1218 | #endif /* CONFIG_SYS_FLASHBOOT */ |