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42d1f039 | 1 | /* |
1ced1216 | 2 | * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. |
42d1f039 WD |
3 | * (C) Copyright 2002, 2003 Motorola Inc. |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2000 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <watchdog.h> | |
30 | #include <command.h> | |
31 | #include <asm/cache.h> | |
32 | ||
591933ca JY |
33 | DECLARE_GLOBAL_DATA_PTR; |
34 | ||
1ced1216 AF |
35 | struct cpu_type { |
36 | char name[15]; | |
37 | u32 soc_ver; | |
38 | }; | |
39 | ||
40 | #define CPU_TYPE_ENTRY(x) {#x, SVR_##x} | |
41 | ||
42 | struct cpu_type cpu_type_list [] = { | |
43 | CPU_TYPE_ENTRY(8533), | |
44 | CPU_TYPE_ENTRY(8533_E), | |
45 | CPU_TYPE_ENTRY(8540), | |
46 | CPU_TYPE_ENTRY(8541), | |
47 | CPU_TYPE_ENTRY(8541_E), | |
48 | CPU_TYPE_ENTRY(8543), | |
49 | CPU_TYPE_ENTRY(8543_E), | |
50 | CPU_TYPE_ENTRY(8544), | |
51 | CPU_TYPE_ENTRY(8544_E), | |
52 | CPU_TYPE_ENTRY(8545), | |
53 | CPU_TYPE_ENTRY(8545_E), | |
54 | CPU_TYPE_ENTRY(8547_E), | |
55 | CPU_TYPE_ENTRY(8548), | |
56 | CPU_TYPE_ENTRY(8548_E), | |
57 | CPU_TYPE_ENTRY(8555), | |
58 | CPU_TYPE_ENTRY(8555_E), | |
59 | CPU_TYPE_ENTRY(8560), | |
60 | CPU_TYPE_ENTRY(8567), | |
61 | CPU_TYPE_ENTRY(8567_E), | |
62 | CPU_TYPE_ENTRY(8568), | |
63 | CPU_TYPE_ENTRY(8568_E), | |
64 | CPU_TYPE_ENTRY(8572), | |
65 | CPU_TYPE_ENTRY(8572_E), | |
66 | }; | |
67 | ||
42d1f039 WD |
68 | int checkcpu (void) |
69 | { | |
97d80fc3 WD |
70 | sys_info_t sysinfo; |
71 | uint lcrr; /* local bus clock ratio register */ | |
72 | uint clkdiv; /* clock divider portion of lcrr */ | |
73 | uint pvr, svr; | |
d9b94f28 | 74 | uint fam; |
97d80fc3 WD |
75 | uint ver; |
76 | uint major, minor; | |
1ced1216 | 77 | int i; |
d4357932 KG |
78 | u32 ddr_ratio; |
79 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
97d80fc3 | 80 | |
97d80fc3 | 81 | svr = get_svr(); |
1ced1216 | 82 | ver = SVR_SOC_VER(svr); |
97d80fc3 WD |
83 | major = SVR_MAJ(svr); |
84 | minor = SVR_MIN(svr); | |
42d1f039 | 85 | |
6c9e789e | 86 | puts("CPU: "); |
1ced1216 AF |
87 | |
88 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) | |
89 | if (cpu_type_list[i].soc_ver == ver) { | |
90 | puts(cpu_type_list[i].name); | |
91 | break; | |
92 | } | |
93 | ||
94 | if (i == ARRAY_SIZE(cpu_type_list)) | |
97d80fc3 | 95 | puts("Unknown"); |
1ced1216 | 96 | |
97d80fc3 WD |
97 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
98 | ||
6c9e789e | 99 | pvr = get_pvr(); |
d9b94f28 | 100 | fam = PVR_FAM(pvr); |
6c9e789e WD |
101 | ver = PVR_VER(pvr); |
102 | major = PVR_MAJ(pvr); | |
103 | minor = PVR_MIN(pvr); | |
104 | ||
105 | printf("Core: "); | |
d9b94f28 JL |
106 | switch (fam) { |
107 | case PVR_FAM(PVR_85xx): | |
6c9e789e WD |
108 | puts("E500"); |
109 | break; | |
110 | default: | |
111 | puts("Unknown"); | |
112 | break; | |
113 | } | |
114 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); | |
115 | ||
97d80fc3 WD |
116 | get_sys_info(&sysinfo); |
117 | ||
d9b94f28 | 118 | puts("Clock Configuration:\n"); |
022f1216 KG |
119 | printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); |
120 | printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); | |
d4357932 KG |
121 | ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; |
122 | switch (ddr_ratio) { | |
123 | case 0x0: | |
e9ea6799 | 124 | printf(" DDR:%4lu MHz (%lu MT/s data rate), ", |
022f1216 | 125 | DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); |
d4357932 KG |
126 | break; |
127 | case 0x7: | |
e9ea6799 | 128 | printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", |
022f1216 | 129 | DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); |
d4357932 KG |
130 | break; |
131 | default: | |
e9ea6799 | 132 | printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", |
022f1216 | 133 | DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); |
d4357932 KG |
134 | break; |
135 | } | |
97d80fc3 WD |
136 | |
137 | #if defined(CFG_LBC_LCRR) | |
138 | lcrr = CFG_LBC_LCRR; | |
139 | #else | |
140 | { | |
04db4008 | 141 | volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); |
97d80fc3 WD |
142 | |
143 | lcrr = lbc->lcrr; | |
144 | } | |
145 | #endif | |
146 | clkdiv = lcrr & 0x0f; | |
147 | if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { | |
151d5d99 | 148 | #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) |
d9b94f28 JL |
149 | /* |
150 | * Yes, the entire PQ38 family use the same | |
151 | * bit-representation for twice the clock divider values. | |
152 | */ | |
153 | clkdiv *= 2; | |
154 | #endif | |
97d80fc3 | 155 | printf("LBC:%4lu MHz\n", |
022f1216 | 156 | DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); |
97d80fc3 | 157 | } else { |
6c9e789e | 158 | printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); |
97d80fc3 | 159 | } |
42d1f039 | 160 | |
1ced1216 AF |
161 | #ifdef CONFIG_CPM2 |
162 | printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); | |
163 | #endif | |
97d80fc3 | 164 | |
6c9e789e | 165 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
42d1f039 WD |
166 | |
167 | return 0; | |
168 | } | |
169 | ||
170 | ||
171 | /* ------------------------------------------------------------------------- */ | |
172 | ||
173 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) | |
174 | { | |
96629cba ZR |
175 | uint pvr; |
176 | uint ver; | |
177 | pvr = get_pvr(); | |
178 | ver = PVR_VER(pvr); | |
179 | if (ver & 1){ | |
180 | /* e500 v2 core has reset control register */ | |
181 | volatile unsigned int * rstcr; | |
182 | rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); | |
2f15278c | 183 | *rstcr = 0x2; /* HRESET_REQ */ |
96629cba | 184 | }else{ |
42d1f039 WD |
185 | /* |
186 | * Initiate hard reset in debug control register DBCR0 | |
187 | * Make sure MSR[DE] = 1 | |
188 | */ | |
df90968b | 189 | unsigned long val, msr; |
190 | ||
191 | msr = mfmsr (); | |
192 | msr |= MSR_DE; | |
193 | mtmsr (msr); | |
194 | ||
96629cba ZR |
195 | val = mfspr(DBCR0); |
196 | val |= 0x70000000; | |
197 | mtspr(DBCR0,val); | |
198 | } | |
42d1f039 WD |
199 | return 1; |
200 | } | |
201 | ||
202 | ||
203 | /* | |
204 | * Get timebase clock frequency | |
205 | */ | |
206 | unsigned long get_tbclk (void) | |
207 | { | |
591933ca | 208 | return (gd->bus_clk + 4UL)/8UL; |
42d1f039 WD |
209 | } |
210 | ||
211 | ||
212 | #if defined(CONFIG_WATCHDOG) | |
213 | void | |
214 | watchdog_reset(void) | |
215 | { | |
216 | int re_enable = disable_interrupts(); | |
217 | reset_85xx_watchdog(); | |
218 | if (re_enable) enable_interrupts(); | |
219 | } | |
220 | ||
221 | void | |
222 | reset_85xx_watchdog(void) | |
223 | { | |
224 | /* | |
225 | * Clear TSR(WIS) bit by writing 1 | |
226 | */ | |
227 | unsigned long val; | |
03b81b48 AF |
228 | val = mfspr(SPRN_TSR); |
229 | val |= TSR_WIS; | |
230 | mtspr(SPRN_TSR, val); | |
42d1f039 WD |
231 | } |
232 | #endif /* CONFIG_WATCHDOG */ | |
233 | ||
234 | #if defined(CONFIG_DDR_ECC) | |
42d1f039 | 235 | void dma_init(void) { |
04db4008 | 236 | volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); |
42d1f039 WD |
237 | |
238 | dma->satr0 = 0x02c40000; | |
239 | dma->datr0 = 0x02c40000; | |
03b81b48 | 240 | dma->sr0 = 0xfffffff; /* clear any errors */ |
42d1f039 WD |
241 | asm("sync; isync; msync"); |
242 | return; | |
243 | } | |
244 | ||
245 | uint dma_check(void) { | |
04db4008 | 246 | volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); |
42d1f039 WD |
247 | volatile uint status = dma->sr0; |
248 | ||
249 | /* While the channel is busy, spin */ | |
250 | while((status & 4) == 4) { | |
251 | status = dma->sr0; | |
252 | } | |
253 | ||
03b81b48 AF |
254 | /* clear MR0[CS] channel start bit */ |
255 | dma->mr0 &= 0x00000001; | |
256 | asm("sync;isync;msync"); | |
257 | ||
42d1f039 WD |
258 | if (status != 0) { |
259 | printf ("DMA Error: status = %x\n", status); | |
260 | } | |
261 | return status; | |
262 | } | |
263 | ||
264 | int dma_xfer(void *dest, uint count, void *src) { | |
04db4008 | 265 | volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); |
42d1f039 WD |
266 | |
267 | dma->dar0 = (uint) dest; | |
268 | dma->sar0 = (uint) src; | |
269 | dma->bcr0 = count; | |
270 | dma->mr0 = 0xf000004; | |
271 | asm("sync;isync;msync"); | |
272 | dma->mr0 = 0xf000005; | |
273 | asm("sync;isync;msync"); | |
274 | return dma_check(); | |
275 | } | |
276 | #endif |