[people/ms/u-boot.git] / cpu / mpc85xx / cpu.c

/*
 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
 * (C) Copyright 2002, 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>

struct cpu_type {
	char name[15];
	u32 soc_ver;
};

#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}

struct cpu_type cpu_type_list [] = {
	CPU_TYPE_ENTRY(8533),
	CPU_TYPE_ENTRY(8533_E),
	CPU_TYPE_ENTRY(8540),
	CPU_TYPE_ENTRY(8541),
	CPU_TYPE_ENTRY(8541_E),
	CPU_TYPE_ENTRY(8543),
	CPU_TYPE_ENTRY(8543_E),
	CPU_TYPE_ENTRY(8544),
	CPU_TYPE_ENTRY(8544_E),
	CPU_TYPE_ENTRY(8545),
	CPU_TYPE_ENTRY(8545_E),
	CPU_TYPE_ENTRY(8547_E),
	CPU_TYPE_ENTRY(8548),
	CPU_TYPE_ENTRY(8548_E),
	CPU_TYPE_ENTRY(8555),
	CPU_TYPE_ENTRY(8555_E),
	CPU_TYPE_ENTRY(8560),
	CPU_TYPE_ENTRY(8567),
	CPU_TYPE_ENTRY(8567_E),
	CPU_TYPE_ENTRY(8568),
	CPU_TYPE_ENTRY(8568_E),
	CPU_TYPE_ENTRY(8572),
	CPU_TYPE_ENTRY(8572_E),
};

int checkcpu (void)
{
	sys_info_t sysinfo;
	uint lcrr;		/* local bus clock ratio register */
	uint clkdiv;		/* clock divider portion of lcrr */
	uint pvr, svr;
	uint fam;
	uint ver;
	uint major, minor;
	int i;
	u32 ddr_ratio;
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);

	svr = get_svr();
	ver = SVR_SOC_VER(svr);
	major = SVR_MAJ(svr);
	minor = SVR_MIN(svr);

	puts("CPU:   ");

	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
		if (cpu_type_list[i].soc_ver == ver) {
			puts(cpu_type_list[i].name);
			break;
		}

	if (i == ARRAY_SIZE(cpu_type_list))
		puts("Unknown");

	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);

	pvr = get_pvr();
	fam = PVR_FAM(pvr);
	ver = PVR_VER(pvr);
	major = PVR_MAJ(pvr);
	minor = PVR_MIN(pvr);

	printf("Core:  ");
	switch (fam) {
	case PVR_FAM(PVR_85xx):
	    puts("E500");
	    break;
	default:
	    puts("Unknown");
	    break;
	}
	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);

	get_sys_info(&sysinfo);

	puts("Clock Configuration:\n");
	printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);

	ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
	switch (ddr_ratio) {
	case 0x0:
		printf("       DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
		break;
	case 0x7:
		printf("       DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
		break;
	default:
		printf("       DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
		break;
	}

#if defined(CFG_LBC_LCRR)
	lcrr = CFG_LBC_LCRR;
#else
	{
	    volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	    lcrr = lbc->lcrr;
	}
#endif
	clkdiv = lcrr & 0x0f;
	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		 clkdiv *= 2;
#endif
		printf("LBC:%4lu MHz\n",
		       sysinfo.freqSystemBus / 1000000 / clkdiv);
	} else {
		printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
	}

#ifdef CONFIG_CPM2
	printf("CPM:  %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif

	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	uint pvr;
	uint ver;
	pvr = get_pvr();
	ver = PVR_VER(pvr);
	if (ver & 1){
	/* e500 v2 core has reset control register */
		volatile unsigned int * rstcr;
		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
		*rstcr = 0x2;		/* HRESET_REQ */
	}else{
	/*
	 * Initiate hard reset in debug control register DBCR0
	 * Make sure MSR[DE] = 1
	 */
		unsigned long val, msr;

		msr = mfmsr ();
		msr |= MSR_DE;
		mtmsr (msr);

		val = mfspr(DBCR0);
		val |= 0x70000000;
		mtspr(DBCR0,val);
	}
	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{

	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return ((sys_info.freqSystemBus + 7L) / 8L);
}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_85xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_85xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit by writing 1
	 */
	unsigned long val;
	val = mfspr(SPRN_TSR);
	val |= TSR_WIS;
	mtspr(SPRN_TSR, val);
}
#endif	/* CONFIG_WATCHDOG */

#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);

	dma->satr0 = 0x02c40000;
	dma->datr0 = 0x02c40000;
	dma->sr0 = 0xfffffff; /* clear any errors */
	asm("sync; isync; msync");
	return;
}

uint dma_check(void) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
	volatile uint status = dma->sr0;

	/* While the channel is busy, spin */
	while((status & 4) == 4) {
		status = dma->sr0;
	}

	/* clear MR0[CS] channel start bit */
	dma->mr0 &= 0x00000001;
	asm("sync;isync;msync");

	if (status != 0) {
		printf ("DMA Error: status = %x\n", status);
	}
	return status;
}

int dma_xfer(void *dest, uint count, void *src) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);

	dma->dar0 = (uint) dest;
	dma->sar0 = (uint) src;
	dma->bcr0 = count;
	dma->mr0 = 0xf000004;
	asm("sync;isync;msync");
	dma->mr0 = 0xf000005;
	asm("sync;isync;msync");
	return dma_check();
}
#endif
Commit	Line	Data
42d1f039	1	/*
1ced1216	2	* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
42d1f039 WD	3	* (C) Copyright 2002, 2003 Motorola Inc.
	4	* Xianghua Xiao (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2000
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
	30	#include <command.h>
	31	#include <asm/cache.h>
	32
1ced1216 AF	33	struct cpu_type {
	34	char name[15];
	35	u32 soc_ver;
	36	};
	37
	38	#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
	39
	40	struct cpu_type cpu_type_list [] = {
	41	CPU_TYPE_ENTRY(8533),
	42	CPU_TYPE_ENTRY(8533_E),
	43	CPU_TYPE_ENTRY(8540),
	44	CPU_TYPE_ENTRY(8541),
	45	CPU_TYPE_ENTRY(8541_E),
	46	CPU_TYPE_ENTRY(8543),
	47	CPU_TYPE_ENTRY(8543_E),
	48	CPU_TYPE_ENTRY(8544),
	49	CPU_TYPE_ENTRY(8544_E),
	50	CPU_TYPE_ENTRY(8545),
	51	CPU_TYPE_ENTRY(8545_E),
	52	CPU_TYPE_ENTRY(8547_E),
	53	CPU_TYPE_ENTRY(8548),
	54	CPU_TYPE_ENTRY(8548_E),
	55	CPU_TYPE_ENTRY(8555),
	56	CPU_TYPE_ENTRY(8555_E),
	57	CPU_TYPE_ENTRY(8560),
	58	CPU_TYPE_ENTRY(8567),
	59	CPU_TYPE_ENTRY(8567_E),
	60	CPU_TYPE_ENTRY(8568),
	61	CPU_TYPE_ENTRY(8568_E),
	62	CPU_TYPE_ENTRY(8572),
	63	CPU_TYPE_ENTRY(8572_E),
	64	};
	65
42d1f039 WD	66	int checkcpu (void)
42d1f039 WD	67	{
97d80fc3 WD	68	sys_info_t sysinfo;
	69	uint lcrr; /* local bus clock ratio register */
	70	uint clkdiv; /* clock divider portion of lcrr */
	71	uint pvr, svr;
d9b94f28	72	uint fam;
97d80fc3 WD	73	uint ver;
97d80fc3 WD	74	uint major, minor;
1ced1216	75	int i;
d4357932 KG	76	u32 ddr_ratio;
d4357932 KG	77	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
97d80fc3	78
97d80fc3	79	svr = get_svr();
1ced1216	80	ver = SVR_SOC_VER(svr);
97d80fc3 WD	81	major = SVR_MAJ(svr);
97d80fc3 WD	82	minor = SVR_MIN(svr);
42d1f039	83
6c9e789e	84	puts("CPU: ");
1ced1216 AF	85
	86	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
	87	if (cpu_type_list[i].soc_ver == ver) {
	88	puts(cpu_type_list[i].name);
	89	break;
	90	}
	91
	92	if (i == ARRAY_SIZE(cpu_type_list))
97d80fc3	93	puts("Unknown");
1ced1216	94
97d80fc3 WD	95	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
97d80fc3 WD	96
6c9e789e	97	pvr = get_pvr();
d9b94f28	98	fam = PVR_FAM(pvr);
6c9e789e WD	99	ver = PVR_VER(pvr);
	100	major = PVR_MAJ(pvr);
	101	minor = PVR_MIN(pvr);
	102
	103	printf("Core: ");
d9b94f28 JL	104	switch (fam) {
d9b94f28 JL	105	case PVR_FAM(PVR_85xx):
6c9e789e WD	106	puts("E500");
	107	break;
	108	default:
	109	puts("Unknown");
	110	break;
	111	}
	112	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
	113
97d80fc3 WD	114	get_sys_info(&sysinfo);
97d80fc3 WD	115
d9b94f28	116	puts("Clock Configuration:\n");
6c9e789e WD	117	printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
6c9e789e WD	118	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
d4357932 KG	119
	120	ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
	121	switch (ddr_ratio) {
	122	case 0x0:
	123	printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
	124	break;
	125	case 0x7:
	126	printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
	127	break;
	128	default:
	129	printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
	130	break;
	131	}
97d80fc3 WD	132
	133	#if defined(CFG_LBC_LCRR)
	134	lcrr = CFG_LBC_LCRR;
	135	#else
	136	{
04db4008	137	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
97d80fc3 WD	138
	139	lcrr = lbc->lcrr;
	140	}
	141	#endif
	142	clkdiv = lcrr & 0x0f;
	143	if (clkdiv == 2 \|\| clkdiv == 4 \|\| clkdiv == 8) {
151d5d99	144	#if defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8544)
d9b94f28 JL	145	/*
	146	* Yes, the entire PQ38 family use the same
	147	* bit-representation for twice the clock divider values.
	148	*/
	149	clkdiv *= 2;
	150	#endif
97d80fc3 WD	151	printf("LBC:%4lu MHz\n",
	152	sysinfo.freqSystemBus / 1000000 / clkdiv);
	153	} else {
6c9e789e	154	printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
97d80fc3	155	}
42d1f039	156
1ced1216 AF	157	#ifdef CONFIG_CPM2
	158	printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
	159	#endif
97d80fc3	160
6c9e789e	161	puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
42d1f039 WD	162
	163	return 0;
	164	}
	165
	166
	167	/* ------------------------------------------------------------------------- */
	168
	169	int do_reset (cmd_tbl_t cmdtp, bd_t bd, int flag, int argc, char *argv[])
	170	{
96629cba ZR	171	uint pvr;
	172	uint ver;
	173	pvr = get_pvr();
	174	ver = PVR_VER(pvr);
	175	if (ver & 1){
	176	/* e500 v2 core has reset control register */
	177	volatile unsigned int * rstcr;
	178	rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
2f15278c	179	rstcr = 0x2; / HRESET_REQ */
96629cba	180	}else{
42d1f039 WD	181	/*
	182	* Initiate hard reset in debug control register DBCR0
	183	* Make sure MSR[DE] = 1
	184	*/
df90968b	185	unsigned long val, msr;
	186
	187	msr = mfmsr ();
	188	msr \|= MSR_DE;
	189	mtmsr (msr);
	190
96629cba ZR	191	val = mfspr(DBCR0);
	192	val \|= 0x70000000;
	193	mtspr(DBCR0,val);
	194	}
42d1f039 WD	195	return 1;
	196	}
	197
	198
	199	/*
	200	* Get timebase clock frequency
	201	*/
	202	unsigned long get_tbclk (void)
	203	{
	204
	205	sys_info_t sys_info;
	206
	207	get_sys_info(&sys_info);
2a8af187	208	return ((sys_info.freqSystemBus + 7L) / 8L);
42d1f039 WD	209	}
	210
	211
	212	#if defined(CONFIG_WATCHDOG)
	213	void
	214	watchdog_reset(void)
	215	{
	216	int re_enable = disable_interrupts();
	217	reset_85xx_watchdog();
	218	if (re_enable) enable_interrupts();
	219	}
	220
	221	void
	222	reset_85xx_watchdog(void)
	223	{
	224	/*
	225	* Clear TSR(WIS) bit by writing 1
	226	*/
	227	unsigned long val;
03b81b48 AF	228	val = mfspr(SPRN_TSR);
	229	val \|= TSR_WIS;
	230	mtspr(SPRN_TSR, val);
42d1f039 WD	231	}
	232	#endif /* CONFIG_WATCHDOG */
	233
	234	#if defined(CONFIG_DDR_ECC)
42d1f039	235	void dma_init(void) {
04db4008	236	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	237
	238	dma->satr0 = 0x02c40000;
	239	dma->datr0 = 0x02c40000;
03b81b48	240	dma->sr0 = 0xfffffff; /* clear any errors */
42d1f039 WD	241	asm("sync; isync; msync");
	242	return;
	243	}
	244
	245	uint dma_check(void) {
04db4008	246	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	247	volatile uint status = dma->sr0;
	248
	249	/* While the channel is busy, spin */
	250	while((status & 4) == 4) {
	251	status = dma->sr0;
	252	}
	253
03b81b48 AF	254	/* clear MR0[CS] channel start bit */
	255	dma->mr0 &= 0x00000001;
	256	asm("sync;isync;msync");
	257
42d1f039 WD	258	if (status != 0) {
	259	printf ("DMA Error: status = %x\n", status);
	260	}
	261	return status;
	262	}
	263
	264	int dma_xfer(void dest, uint count, void src) {
04db4008	265	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	266
	267	dma->dar0 = (uint) dest;
	268	dma->sar0 = (uint) src;
	269	dma->bcr0 = count;
	270	dma->mr0 = 0xf000004;
	271	asm("sync;isync;msync");
	272	dma->mr0 = 0xf000005;
	273	asm("sync;isync;msync");
	274	return dma_check();
	275	}
	276	#endif