[people/ms/u-boot.git] / cpu / mpc85xx / cpu.c

/*
 * Copyright 2004,2007 Freescale Semiconductor, Inc.
 * (C) Copyright 2002, 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>

#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif


int checkcpu (void)
{
	sys_info_t sysinfo;
	uint lcrr;		/* local bus clock ratio register */
	uint clkdiv;		/* clock divider portion of lcrr */
	uint pvr, svr;
	uint fam;
	uint ver;
	uint major, minor;

	svr = get_svr();
	ver = SVR_VER(svr);
	major = SVR_MAJ(svr);
	minor = SVR_MIN(svr);

	puts("CPU:   ");
	switch (ver) {
	case SVR_8540:
		puts("8540");
		break;
	case SVR_8541:
		puts("8541");
		break;
	case SVR_8555:
		puts("8555");
		break;
	case SVR_8560:
		puts("8560");
		break;
	case SVR_8548:
		puts("8548");
		break;
	case SVR_8548_E:
		puts("8548_E");
		break;
	case SVR_8544:
		puts("8544");
		break;
	case SVR_8544_E:
		puts("8544_E");
		break;
	case SVR_8568_E:
		puts("8568_E");
		break;
	default:
		puts("Unknown");
		break;
	}
	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);

	pvr = get_pvr();
	fam = PVR_FAM(pvr);
	ver = PVR_VER(pvr);
	major = PVR_MAJ(pvr);
	minor = PVR_MIN(pvr);

	printf("Core:  ");
	switch (fam) {
	case PVR_FAM(PVR_85xx):
	    puts("E500");
	    break;
	default:
	    puts("Unknown");
	    break;
	}
	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);

	get_sys_info(&sysinfo);

	puts("Clock Configuration:\n");
	printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
	printf("       DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);

#if defined(CFG_LBC_LCRR)
	lcrr = CFG_LBC_LCRR;
#else
	{
	    volatile immap_t *immap = (immap_t *)CFG_IMMR;
	    volatile ccsr_lbc_t *lbc= &immap->im_lbc;

	    lcrr = lbc->lcrr;
	}
#endif
	clkdiv = lcrr & 0x0f;
	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		 clkdiv *= 2;
#endif
		printf("LBC:%4lu MHz\n",
		       sysinfo.freqSystemBus / 1000000 / clkdiv);
	} else {
		printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
	}

	if (ver == SVR_8560) {
		printf("CPM:  %lu Mhz\n",
		       sysinfo.freqSystemBus / 1000000);
	}

	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	uint pvr;
	uint ver;
	pvr = get_pvr();
	ver = PVR_VER(pvr);
	if (ver & 1){
	/* e500 v2 core has reset control register */
		volatile unsigned int * rstcr;
		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
		*rstcr = 0x2;		/* HRESET_REQ */
	}else{
	/*
	 * Initiate hard reset in debug control register DBCR0
	 * Make sure MSR[DE] = 1
	 */
		unsigned long val;
		val = mfspr(DBCR0);
		val |= 0x70000000;
		mtspr(DBCR0,val);
	}
	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{

	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return ((sys_info.freqSystemBus + 7L) / 8L);
}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_85xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_85xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit by writing 1
	 */
	unsigned long val;
	val = mfspr(SPRN_TSR);
	val |= TSR_WIS;
	mtspr(SPRN_TSR, val);
}
#endif	/* CONFIG_WATCHDOG */

#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_dma_t *dma = &immap->im_dma;

	dma->satr0 = 0x02c40000;
	dma->datr0 = 0x02c40000;
	dma->sr0 = 0xfffffff; /* clear any errors */
	asm("sync; isync; msync");
	return;
}

uint dma_check(void) {
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_dma_t *dma = &immap->im_dma;
	volatile uint status = dma->sr0;

	/* While the channel is busy, spin */
	while((status & 4) == 4) {
		status = dma->sr0;
	}

	/* clear MR0[CS] channel start bit */
	dma->mr0 &= 0x00000001;
	asm("sync;isync;msync");

	if (status != 0) {
		printf ("DMA Error: status = %x\n", status);
	}
	return status;
}

int dma_xfer(void *dest, uint count, void *src) {
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_dma_t *dma = &immap->im_dma;

	dma->dar0 = (uint) dest;
	dma->sar0 = (uint) src;
	dma->bcr0 = count;
	dma->mr0 = 0xf000004;
	asm("sync;isync;msync");
	dma->mr0 = 0xf000005;
	asm("sync;isync;msync");
	return dma_check();
}
#endif


#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup(void *blob, bd_t *bd)
{
	u32 *p;
	ulong clock;
	int len;

	clock = bd->bi_busfreq;
	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

	p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

	p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
	if (p != NULL)
		*p = cpu_to_be32(clock);

#if defined(CONFIG_TSEC1)
	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enetaddr, 6);

	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enetaddr, 6);
#endif

#if defined(CONFIG_HAS_ETH1)
	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enet1addr, 6);

	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enet1addr, 6);
#endif

#if defined(CONFIG_HAS_ETH2)
	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enet2addr, 6);

	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enet2addr, 6);
#endif

#if defined(CONFIG_HAS_ETH3)
	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enet3addr, 6);

	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
	if (p)
		memcpy(p, bd->bi_enet3addr, 6);
#endif

}
#endif
Commit	Line	Data
42d1f039	1	/*
151d5d99	2	* Copyright 2004,2007 Freescale Semiconductor, Inc.
42d1f039 WD	3	* (C) Copyright 2002, 2003 Motorola Inc.
	4	* Xianghua Xiao (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2000
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
	30	#include <command.h>
	31	#include <asm/cache.h>
	32
40d5fa35 MM	33	#if defined(CONFIG_OF_FLAT_TREE)
	34	#include <ft_build.h>
	35	#endif
	36
42d1f039 WD	37
	38	int checkcpu (void)
	39	{
97d80fc3 WD	40	sys_info_t sysinfo;
	41	uint lcrr; /* local bus clock ratio register */
	42	uint clkdiv; /* clock divider portion of lcrr */
	43	uint pvr, svr;
d9b94f28	44	uint fam;
97d80fc3 WD	45	uint ver;
	46	uint major, minor;
	47
97d80fc3 WD	48	svr = get_svr();
	49	ver = SVR_VER(svr);
	50	major = SVR_MAJ(svr);
	51	minor = SVR_MIN(svr);
42d1f039	52
6c9e789e	53	puts("CPU: ");
97d80fc3 WD	54	switch (ver) {
	55	case SVR_8540:
	56	puts("8540");
	57	break;
	58	case SVR_8541:
	59	puts("8541");
	60	break;
	61	case SVR_8555:
	62	puts("8555");
	63	break;
	64	case SVR_8560:
	65	puts("8560");
	66	break;
d9b94f28 JL	67	case SVR_8548:
	68	puts("8548");
	69	break;
	70	case SVR_8548_E:
	71	puts("8548_E");
	72	break;
151d5d99	73	case SVR_8544:
2f15278c WD	74	puts("8544");
	75	break;
	76	case SVR_8544_E:
	77	puts("8544_E");
	78	break;
	79	case SVR_8568_E:
	80	puts("8568_E");
	81	break;
42d1f039	82	default:
97d80fc3	83	puts("Unknown");
42d1f039 WD	84	break;
42d1f039 WD	85	}
97d80fc3 WD	86	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
97d80fc3 WD	87
6c9e789e	88	pvr = get_pvr();
d9b94f28	89	fam = PVR_FAM(pvr);
6c9e789e WD	90	ver = PVR_VER(pvr);
	91	major = PVR_MAJ(pvr);
	92	minor = PVR_MIN(pvr);
	93
	94	printf("Core: ");
d9b94f28 JL	95	switch (fam) {
d9b94f28 JL	96	case PVR_FAM(PVR_85xx):
6c9e789e WD	97	puts("E500");
	98	break;
	99	default:
	100	puts("Unknown");
	101	break;
	102	}
	103	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
	104
97d80fc3 WD	105	get_sys_info(&sysinfo);
97d80fc3 WD	106
d9b94f28	107	puts("Clock Configuration:\n");
6c9e789e WD	108	printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
	109	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
	110	printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
97d80fc3 WD	111
	112	#if defined(CFG_LBC_LCRR)
	113	lcrr = CFG_LBC_LCRR;
	114	#else
	115	{
	116	volatile immap_t immap = (immap_t )CFG_IMMR;
	117	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
	118
	119	lcrr = lbc->lcrr;
	120	}
	121	#endif
	122	clkdiv = lcrr & 0x0f;
	123	if (clkdiv == 2 \|\| clkdiv == 4 \|\| clkdiv == 8) {
151d5d99	124	#if defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8544)
d9b94f28 JL	125	/*
	126	* Yes, the entire PQ38 family use the same
	127	* bit-representation for twice the clock divider values.
	128	*/
	129	clkdiv *= 2;
	130	#endif
97d80fc3 WD	131	printf("LBC:%4lu MHz\n",
	132	sysinfo.freqSystemBus / 1000000 / clkdiv);
	133	} else {
6c9e789e	134	printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
97d80fc3	135	}
42d1f039	136
97d80fc3	137	if (ver == SVR_8560) {
6c9e789e	138	printf("CPM: %lu Mhz\n",
97d80fc3 WD	139	sysinfo.freqSystemBus / 1000000);
	140	}
	141
6c9e789e	142	puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
42d1f039 WD	143
	144	return 0;
	145	}
	146
	147
	148	/* ------------------------------------------------------------------------- */
	149
	150	int do_reset (cmd_tbl_t cmdtp, bd_t bd, int flag, int argc, char *argv[])
	151	{
96629cba ZR	152	uint pvr;
	153	uint ver;
	154	pvr = get_pvr();
	155	ver = PVR_VER(pvr);
	156	if (ver & 1){
	157	/* e500 v2 core has reset control register */
	158	volatile unsigned int * rstcr;
	159	rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
2f15278c	160	rstcr = 0x2; / HRESET_REQ */
96629cba	161	}else{
42d1f039 WD	162	/*
	163	* Initiate hard reset in debug control register DBCR0
	164	* Make sure MSR[DE] = 1
	165	*/
96629cba ZR	166	unsigned long val;
	167	val = mfspr(DBCR0);
	168	val \|= 0x70000000;
	169	mtspr(DBCR0,val);
	170	}
42d1f039 WD	171	return 1;
	172	}
	173
	174
	175	/*
	176	* Get timebase clock frequency
	177	*/
	178	unsigned long get_tbclk (void)
	179	{
	180
	181	sys_info_t sys_info;
	182
	183	get_sys_info(&sys_info);
2a8af187	184	return ((sys_info.freqSystemBus + 7L) / 8L);
42d1f039 WD	185	}
	186
	187
	188	#if defined(CONFIG_WATCHDOG)
	189	void
	190	watchdog_reset(void)
	191	{
	192	int re_enable = disable_interrupts();
	193	reset_85xx_watchdog();
	194	if (re_enable) enable_interrupts();
	195	}
	196
	197	void
	198	reset_85xx_watchdog(void)
	199	{
	200	/*
	201	* Clear TSR(WIS) bit by writing 1
	202	*/
	203	unsigned long val;
03b81b48 AF	204	val = mfspr(SPRN_TSR);
	205	val \|= TSR_WIS;
	206	mtspr(SPRN_TSR, val);
42d1f039 WD	207	}
	208	#endif /* CONFIG_WATCHDOG */
	209
	210	#if defined(CONFIG_DDR_ECC)
42d1f039 WD	211	void dma_init(void) {
	212	volatile immap_t immap = (immap_t )CFG_IMMR;
	213	volatile ccsr_dma_t *dma = &immap->im_dma;
	214
	215	dma->satr0 = 0x02c40000;
	216	dma->datr0 = 0x02c40000;
03b81b48	217	dma->sr0 = 0xfffffff; /* clear any errors */
42d1f039 WD	218	asm("sync; isync; msync");
	219	return;
	220	}
	221
	222	uint dma_check(void) {
	223	volatile immap_t immap = (immap_t )CFG_IMMR;
	224	volatile ccsr_dma_t *dma = &immap->im_dma;
	225	volatile uint status = dma->sr0;
	226
	227	/* While the channel is busy, spin */
	228	while((status & 4) == 4) {
	229	status = dma->sr0;
	230	}
	231
03b81b48 AF	232	/* clear MR0[CS] channel start bit */
	233	dma->mr0 &= 0x00000001;
	234	asm("sync;isync;msync");
	235
42d1f039 WD	236	if (status != 0) {
	237	printf ("DMA Error: status = %x\n", status);
	238	}
	239	return status;
	240	}
	241
	242	int dma_xfer(void dest, uint count, void src) {
	243	volatile immap_t immap = (immap_t )CFG_IMMR;
	244	volatile ccsr_dma_t *dma = &immap->im_dma;
	245
	246	dma->dar0 = (uint) dest;
	247	dma->sar0 = (uint) src;
	248	dma->bcr0 = count;
	249	dma->mr0 = 0xf000004;
	250	asm("sync;isync;msync");
	251	dma->mr0 = 0xf000005;
	252	asm("sync;isync;msync");
	253	return dma_check();
	254	}
	255	#endif
40d5fa35 MM	256
	257
	258	#ifdef CONFIG_OF_FLAT_TREE
	259	void
	260	ft_cpu_setup(void blob, bd_t bd)
	261	{
	262	u32 *p;
	263	ulong clock;
	264	int len;
	265
	266	clock = bd->bi_busfreq;
	267	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
	268	if (p != NULL)
	269	*p = cpu_to_be32(clock);
	270
67431059 AF	271	p = ft_get_prop(blob, "/qe@e0080000/" OF_CPU "/bus-frequency", &len);
	272	if (p != NULL)
	273	*p = cpu_to_be32(clock);
	274
40d5fa35 MM	275	p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
	276	if (p != NULL)
	277	*p = cpu_to_be32(clock);
	278
	279	p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
	280	if (p != NULL)
	281	*p = cpu_to_be32(clock);
	282
255a3577	283	#if defined(CONFIG_TSEC1)
40d5fa35	284	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
85e7c7a4 TT	285	if (p)
	286	memcpy(p, bd->bi_enetaddr, 6);
	287
	288	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
	289	if (p)
40d5fa35 MM	290	memcpy(p, bd->bi_enetaddr, 6);
	291	#endif
	292
	293	#if defined(CONFIG_HAS_ETH1)
	294	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
85e7c7a4 TT	295	if (p)
	296	memcpy(p, bd->bi_enet1addr, 6);
	297
	298	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
	299	if (p)
40d5fa35 MM	300	memcpy(p, bd->bi_enet1addr, 6);
	301	#endif
	302
	303	#if defined(CONFIG_HAS_ETH2)
	304	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
85e7c7a4 TT	305	if (p)
	306	memcpy(p, bd->bi_enet2addr, 6);
	307
	308	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
	309	if (p)
40d5fa35 MM	310	memcpy(p, bd->bi_enet2addr, 6);
	311	#endif
	312
	313	#if defined(CONFIG_HAS_ETH3)
	314	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
85e7c7a4 TT	315	if (p)
	316	memcpy(p, bd->bi_enet3addr, 6);
	317
	318	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
	319	if (p)
40d5fa35 MM	320	memcpy(p, bd->bi_enet3addr, 6);
	321	#endif
	322
	323	}
	324	#endif