[people/ms/u-boot.git] / cpu / mpc85xx / cpu.c

/*
 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
 * (C) Copyright 2002, 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>

DECLARE_GLOBAL_DATA_PTR;

struct cpu_type cpu_type_list [] = {
	CPU_TYPE_ENTRY(8533, 8533),
	CPU_TYPE_ENTRY(8533, 8533_E),
	CPU_TYPE_ENTRY(8540, 8540),
	CPU_TYPE_ENTRY(8541, 8541),
	CPU_TYPE_ENTRY(8541, 8541_E),
	CPU_TYPE_ENTRY(8543, 8543),
	CPU_TYPE_ENTRY(8543, 8543_E),
	CPU_TYPE_ENTRY(8544, 8544),
	CPU_TYPE_ENTRY(8544, 8544_E),
	CPU_TYPE_ENTRY(8545, 8545),
	CPU_TYPE_ENTRY(8545, 8545_E),
	CPU_TYPE_ENTRY(8547, 8547_E),
	CPU_TYPE_ENTRY(8548, 8548),
	CPU_TYPE_ENTRY(8548, 8548_E),
	CPU_TYPE_ENTRY(8555, 8555),
	CPU_TYPE_ENTRY(8555, 8555_E),
	CPU_TYPE_ENTRY(8560, 8560),
	CPU_TYPE_ENTRY(8567, 8567),
	CPU_TYPE_ENTRY(8567, 8567_E),
	CPU_TYPE_ENTRY(8568, 8568),
	CPU_TYPE_ENTRY(8568, 8568_E),
	CPU_TYPE_ENTRY(8572, 8572),
	CPU_TYPE_ENTRY(8572, 8572_E),
};

struct cpu_type *identify_cpu(uint ver)
{
	int i;
	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
		if (cpu_type_list[i].soc_ver == ver)
			return &cpu_type_list[i];

	return NULL;
}

int checkcpu (void)
{
	sys_info_t sysinfo;
	uint lcrr;		/* local bus clock ratio register */
	uint clkdiv;		/* clock divider portion of lcrr */
	uint pvr, svr;
	uint fam;
	uint ver;
	uint major, minor;
	struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
#else
	u32 ddr_ratio = 0;
#endif

	svr = get_svr();
	ver = SVR_SOC_VER(svr);
	major = SVR_MAJ(svr);
	minor = SVR_MIN(svr);

	puts("CPU:   ");

	cpu = identify_cpu(ver);
	if (cpu) {
		puts(cpu->name);

		if (svr & 0x80000)
			puts("E");
	} else {
		puts("Unknown");
	}

	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);

	pvr = get_pvr();
	fam = PVR_FAM(pvr);
	ver = PVR_VER(pvr);
	major = PVR_MAJ(pvr);
	minor = PVR_MIN(pvr);

	printf("Core:  ");
	switch (fam) {
	case PVR_FAM(PVR_85xx):
	    puts("E500");
	    break;
	default:
	    puts("Unknown");
	    break;
	}
	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);

	get_sys_info(&sysinfo);

	puts("Clock Configuration:\n");
	printf("       CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
	printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));

	switch (ddr_ratio) {
	case 0x0:
		printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
		DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
		break;
	case 0x7:
		printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
		DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
		break;
	default:
		printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
		DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
		break;
	}

#if defined(CFG_LBC_LCRR)
	lcrr = CFG_LBC_LCRR;
#else
	{
	    volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	    lcrr = lbc->lcrr;
	}
#endif
	clkdiv = lcrr & 0x0f;
	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		 clkdiv *= 2;
#endif
		printf("LBC:%4lu MHz\n",
		       DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
	} else {
		printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
	}

#ifdef CONFIG_CPM2
	printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif

	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	uint pvr;
	uint ver;
	unsigned long val, msr;

	pvr = get_pvr();
	ver = PVR_VER(pvr);

	if (ver & 1){
	/* e500 v2 core has reset control register */
		volatile unsigned int * rstcr;
		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
		*rstcr = 0x2;		/* HRESET_REQ */
		udelay(100);
	}

	/*
	 * Fallthrough if the code above failed
	 * Initiate hard reset in debug control register DBCR0
	 * Make sure MSR[DE] = 1
	 */

	msr = mfmsr ();
	msr |= MSR_DE;
	mtmsr (msr);

	val = mfspr(DBCR0);
	val |= 0x70000000;
	mtspr(DBCR0,val);

	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
	return (gd->bus_clk + 4UL)/8UL;
}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_85xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_85xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit by writing 1
	 */
	unsigned long val;
	val = mfspr(SPRN_TSR);
	val |= TSR_WIS;
	mtspr(SPRN_TSR, val);
}
#endif	/* CONFIG_WATCHDOG */

#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);

	dma->satr0 = 0x02c40000;
	dma->datr0 = 0x02c40000;
	dma->sr0 = 0xfffffff; /* clear any errors */
	asm("sync; isync; msync");
	return;
}

uint dma_check(void) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
	volatile uint status = dma->sr0;

	/* While the channel is busy, spin */
	while((status & 4) == 4) {
		status = dma->sr0;
	}

	/* clear MR0[CS] channel start bit */
	dma->mr0 &= 0x00000001;
	asm("sync;isync;msync");

	if (status != 0) {
		printf ("DMA Error: status = %x\n", status);
	}
	return status;
}

int dma_xfer(void *dest, uint count, void *src) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);

	dma->dar0 = (uint) dest;
	dma->sar0 = (uint) src;
	dma->bcr0 = count;
	dma->mr0 = 0xf000004;
	asm("sync;isync;msync");
	dma->mr0 = 0xf000005;
	asm("sync;isync;msync");
	return dma_check();
}
#endif
Commit	Line	Data
42d1f039	1	/*
1ced1216	2	* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
42d1f039 WD	3	* (C) Copyright 2002, 2003 Motorola Inc.
	4	* Xianghua Xiao (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2000
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
	30	#include <command.h>
	31	#include <asm/cache.h>
	32
591933ca JY	33	DECLARE_GLOBAL_DATA_PTR;
591933ca JY	34
4dbdb768 KG	35	struct cpu_type cpu_type_list [] = {
	36	CPU_TYPE_ENTRY(8533, 8533),
	37	CPU_TYPE_ENTRY(8533, 8533_E),
	38	CPU_TYPE_ENTRY(8540, 8540),
	39	CPU_TYPE_ENTRY(8541, 8541),
	40	CPU_TYPE_ENTRY(8541, 8541_E),
	41	CPU_TYPE_ENTRY(8543, 8543),
	42	CPU_TYPE_ENTRY(8543, 8543_E),
	43	CPU_TYPE_ENTRY(8544, 8544),
	44	CPU_TYPE_ENTRY(8544, 8544_E),
	45	CPU_TYPE_ENTRY(8545, 8545),
	46	CPU_TYPE_ENTRY(8545, 8545_E),
	47	CPU_TYPE_ENTRY(8547, 8547_E),
	48	CPU_TYPE_ENTRY(8548, 8548),
	49	CPU_TYPE_ENTRY(8548, 8548_E),
	50	CPU_TYPE_ENTRY(8555, 8555),
	51	CPU_TYPE_ENTRY(8555, 8555_E),
	52	CPU_TYPE_ENTRY(8560, 8560),
	53	CPU_TYPE_ENTRY(8567, 8567),
	54	CPU_TYPE_ENTRY(8567, 8567_E),
	55	CPU_TYPE_ENTRY(8568, 8568),
	56	CPU_TYPE_ENTRY(8568, 8568_E),
	57	CPU_TYPE_ENTRY(8572, 8572),
	58	CPU_TYPE_ENTRY(8572, 8572_E),
1ced1216 AF	59	};
1ced1216 AF	60
4dbdb768 KG	61	struct cpu_type *identify_cpu(uint ver)
	62	{
	63	int i;
	64	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
	65	if (cpu_type_list[i].soc_ver == ver)
	66	return &cpu_type_list[i];
1ced1216	67
4dbdb768 KG	68	return NULL;
4dbdb768 KG	69	}
1ced1216	70
42d1f039 WD	71	int checkcpu (void)
42d1f039 WD	72	{
97d80fc3 WD	73	sys_info_t sysinfo;
	74	uint lcrr; /* local bus clock ratio register */
	75	uint clkdiv; /* clock divider portion of lcrr */
	76	uint pvr, svr;
d9b94f28	77	uint fam;
97d80fc3 WD	78	uint ver;
97d80fc3 WD	79	uint major, minor;
4dbdb768	80	struct cpu_type *cpu;
ee1e35be	81	#ifdef CONFIG_DDR_CLK_FREQ
d4357932	82	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
ee1e35be KG	83	u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
	84	#else
	85	u32 ddr_ratio = 0;
	86	#endif
97d80fc3	87
97d80fc3	88	svr = get_svr();
1ced1216	89	ver = SVR_SOC_VER(svr);
97d80fc3 WD	90	major = SVR_MAJ(svr);
97d80fc3 WD	91	minor = SVR_MIN(svr);
42d1f039	92
6c9e789e	93	puts("CPU: ");
1ced1216	94
4dbdb768 KG	95	cpu = identify_cpu(ver);
	96	if (cpu) {
	97	puts(cpu->name);
1ced1216	98
4dbdb768 KG	99	if (svr & 0x80000)
	100	puts("E");
	101	} else {
97d80fc3	102	puts("Unknown");
4dbdb768	103	}
1ced1216	104
97d80fc3 WD	105	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
97d80fc3 WD	106
6c9e789e	107	pvr = get_pvr();
d9b94f28	108	fam = PVR_FAM(pvr);
6c9e789e WD	109	ver = PVR_VER(pvr);
	110	major = PVR_MAJ(pvr);
	111	minor = PVR_MIN(pvr);
	112
	113	printf("Core: ");
d9b94f28 JL	114	switch (fam) {
d9b94f28 JL	115	case PVR_FAM(PVR_85xx):
6c9e789e WD	116	puts("E500");
	117	break;
	118	default:
	119	puts("Unknown");
	120	break;
	121	}
	122	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
	123
97d80fc3 WD	124	get_sys_info(&sysinfo);
97d80fc3 WD	125
d9b94f28	126	puts("Clock Configuration:\n");
022f1216 KG	127	printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
022f1216 KG	128	printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
ee1e35be	129
d4357932 KG	130	switch (ddr_ratio) {
d4357932 KG	131	case 0x0:
e9ea6799	132	printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
022f1216	133	DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
d4357932 KG	134	break;
d4357932 KG	135	case 0x7:
e9ea6799	136	printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
022f1216	137	DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
d4357932 KG	138	break;
d4357932 KG	139	default:
e9ea6799	140	printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
022f1216	141	DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
d4357932 KG	142	break;
d4357932 KG	143	}
97d80fc3 WD	144
	145	#if defined(CFG_LBC_LCRR)
	146	lcrr = CFG_LBC_LCRR;
	147	#else
	148	{
04db4008	149	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
97d80fc3 WD	150
	151	lcrr = lbc->lcrr;
	152	}
	153	#endif
	154	clkdiv = lcrr & 0x0f;
	155	if (clkdiv == 2 \|\| clkdiv == 4 \|\| clkdiv == 8) {
151d5d99	156	#if defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8544)
d9b94f28 JL	157	/*
	158	* Yes, the entire PQ38 family use the same
	159	* bit-representation for twice the clock divider values.
	160	*/
	161	clkdiv *= 2;
	162	#endif
97d80fc3	163	printf("LBC:%4lu MHz\n",
022f1216	164	DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
97d80fc3	165	} else {
6c9e789e	166	printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
97d80fc3	167	}
42d1f039	168
1ced1216	169	#ifdef CONFIG_CPM2
6beecfbb	170	printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
1ced1216	171	#endif
97d80fc3	172
6c9e789e	173	puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
42d1f039 WD	174
	175	return 0;
	176	}
	177
	178
	179	/* ------------------------------------------------------------------------- */
	180
	181	int do_reset (cmd_tbl_t cmdtp, bd_t bd, int flag, int argc, char *argv[])
	182	{
96629cba ZR	183	uint pvr;
96629cba ZR	184	uint ver;
793670c3 SP	185	unsigned long val, msr;
793670c3 SP	186
96629cba ZR	187	pvr = get_pvr();
96629cba ZR	188	ver = PVR_VER(pvr);
793670c3	189
96629cba ZR	190	if (ver & 1){
	191	/* e500 v2 core has reset control register */
	192	volatile unsigned int * rstcr;
	193	rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
2f15278c	194	rstcr = 0x2; / HRESET_REQ */
793670c3 SP	195	udelay(100);
	196	}
	197
42d1f039	198	/*
793670c3	199	* Fallthrough if the code above failed
42d1f039 WD	200	* Initiate hard reset in debug control register DBCR0
	201	* Make sure MSR[DE] = 1
	202	*/
df90968b	203
793670c3 SP	204	msr = mfmsr ();
	205	msr \|= MSR_DE;
	206	mtmsr (msr);
	207
	208	val = mfspr(DBCR0);
	209	val \|= 0x70000000;
	210	mtspr(DBCR0,val);
df90968b	211
42d1f039 WD	212	return 1;
	213	}
	214
	215
	216	/*
	217	* Get timebase clock frequency
	218	*/
	219	unsigned long get_tbclk (void)
	220	{
591933ca	221	return (gd->bus_clk + 4UL)/8UL;
42d1f039 WD	222	}
	223
	224
	225	#if defined(CONFIG_WATCHDOG)
	226	void
	227	watchdog_reset(void)
	228	{
	229	int re_enable = disable_interrupts();
	230	reset_85xx_watchdog();
	231	if (re_enable) enable_interrupts();
	232	}
	233
	234	void
	235	reset_85xx_watchdog(void)
	236	{
	237	/*
	238	* Clear TSR(WIS) bit by writing 1
	239	*/
	240	unsigned long val;
03b81b48 AF	241	val = mfspr(SPRN_TSR);
	242	val \|= TSR_WIS;
	243	mtspr(SPRN_TSR, val);
42d1f039 WD	244	}
	245	#endif /* CONFIG_WATCHDOG */
	246
	247	#if defined(CONFIG_DDR_ECC)
42d1f039	248	void dma_init(void) {
04db4008	249	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	250
	251	dma->satr0 = 0x02c40000;
	252	dma->datr0 = 0x02c40000;
03b81b48	253	dma->sr0 = 0xfffffff; /* clear any errors */
42d1f039 WD	254	asm("sync; isync; msync");
	255	return;
	256	}
	257
	258	uint dma_check(void) {
04db4008	259	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	260	volatile uint status = dma->sr0;
	261
	262	/* While the channel is busy, spin */
	263	while((status & 4) == 4) {
	264	status = dma->sr0;
	265	}
	266
03b81b48 AF	267	/* clear MR0[CS] channel start bit */
	268	dma->mr0 &= 0x00000001;
	269	asm("sync;isync;msync");
	270
42d1f039 WD	271	if (status != 0) {
	272	printf ("DMA Error: status = %x\n", status);
	273	}
	274	return status;
	275	}
	276
	277	int dma_xfer(void dest, uint count, void src) {
04db4008	278	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	279
	280	dma->dar0 = (uint) dest;
	281	dma->sar0 = (uint) src;
	282	dma->bcr0 = count;
	283	dma->mr0 = 0xf000004;
	284	asm("sync;isync;msync");
	285	dma->mr0 = 0xf000005;
	286	asm("sync;isync;msync");
	287	return dma_check();
	288	}
	289	#endif