[people/ms/u-boot.git] / cpu / mpc85xx / cpu.c

/*
 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
 * (C) Copyright 2002, 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <tsec.h>
#include <asm/cache.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct cpu_type cpu_type_list [] = {
	CPU_TYPE_ENTRY(8533, 8533),
	CPU_TYPE_ENTRY(8533, 8533_E),
	CPU_TYPE_ENTRY(8536, 8536),
	CPU_TYPE_ENTRY(8536, 8536_E),
	CPU_TYPE_ENTRY(8540, 8540),
	CPU_TYPE_ENTRY(8541, 8541),
	CPU_TYPE_ENTRY(8541, 8541_E),
	CPU_TYPE_ENTRY(8543, 8543),
	CPU_TYPE_ENTRY(8543, 8543_E),
	CPU_TYPE_ENTRY(8544, 8544),
	CPU_TYPE_ENTRY(8544, 8544_E),
	CPU_TYPE_ENTRY(8545, 8545),
	CPU_TYPE_ENTRY(8545, 8545_E),
	CPU_TYPE_ENTRY(8547, 8547_E),
	CPU_TYPE_ENTRY(8548, 8548),
	CPU_TYPE_ENTRY(8548, 8548_E),
	CPU_TYPE_ENTRY(8555, 8555),
	CPU_TYPE_ENTRY(8555, 8555_E),
	CPU_TYPE_ENTRY(8560, 8560),
	CPU_TYPE_ENTRY(8567, 8567),
	CPU_TYPE_ENTRY(8567, 8567_E),
	CPU_TYPE_ENTRY(8568, 8568),
	CPU_TYPE_ENTRY(8568, 8568_E),
	CPU_TYPE_ENTRY(8572, 8572),
	CPU_TYPE_ENTRY(8572, 8572_E),
};

struct cpu_type *identify_cpu(u32 ver)
{
	int i;
	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
		if (cpu_type_list[i].soc_ver == ver)
			return &cpu_type_list[i];

	return NULL;
}

int checkcpu (void)
{
	sys_info_t sysinfo;
	uint lcrr;		/* local bus clock ratio register */
	uint clkdiv;		/* clock divider portion of lcrr */
	uint pvr, svr;
	uint fam;
	uint ver;
	uint major, minor;
	struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
#else
	u32 ddr_ratio = 0;
#endif

	svr = get_svr();
	ver = SVR_SOC_VER(svr);
	major = SVR_MAJ(svr);
#ifdef CONFIG_MPC8536
	major &= 0x7; /* the msb of this nibble is a mfg code */
#endif
	minor = SVR_MIN(svr);

	puts("CPU:   ");

	cpu = identify_cpu(ver);
	if (cpu) {
		puts(cpu->name);

		if (IS_E_PROCESSOR(svr))
			puts("E");
	} else {
		puts("Unknown");
	}

	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);

	pvr = get_pvr();
	fam = PVR_FAM(pvr);
	ver = PVR_VER(pvr);
	major = PVR_MAJ(pvr);
	minor = PVR_MIN(pvr);

	printf("Core:  ");
	switch (fam) {
	case PVR_FAM(PVR_85xx):
	    puts("E500");
	    break;
	default:
	    puts("Unknown");
	    break;
	}
	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);

	get_sys_info(&sysinfo);

	puts("Clock Configuration:\n");
	printf("       CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
	printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));

	switch (ddr_ratio) {
	case 0x0:
		printf("       DDR:%4lu MHz (%lu MT/s data rate), ",
		DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
		break;
	case 0x7:
		printf("       DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
		DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
		break;
	default:
		printf("       DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
		DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
		break;
	}

#if defined(CFG_LBC_LCRR)
	lcrr = CFG_LBC_LCRR;
#else
	{
	    volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	    lcrr = lbc->lcrr;
	}
#endif
	clkdiv = lcrr & 0x0f;
	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
    defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		 clkdiv *= 2;
#endif
		printf("LBC:%4lu MHz\n",
		       DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
	} else {
		printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
	}

#ifdef CONFIG_CPM2
	printf("CPM:   %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif

	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	uint pvr;
	uint ver;
	unsigned long val, msr;

	pvr = get_pvr();
	ver = PVR_VER(pvr);

	if (ver & 1){
	/* e500 v2 core has reset control register */
		volatile unsigned int * rstcr;
		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
		*rstcr = 0x2;		/* HRESET_REQ */
		udelay(100);
	}

	/*
	 * Fallthrough if the code above failed
	 * Initiate hard reset in debug control register DBCR0
	 * Make sure MSR[DE] = 1
	 */

	msr = mfmsr ();
	msr |= MSR_DE;
	mtmsr (msr);

	val = mfspr(DBCR0);
	val |= 0x70000000;
	mtspr(DBCR0,val);

	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
	return (gd->bus_clk + 4UL)/8UL;
}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_85xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_85xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit by writing 1
	 */
	unsigned long val;
	val = mfspr(SPRN_TSR);
	val |= TSR_WIS;
	mtspr(SPRN_TSR, val);
}
#endif	/* CONFIG_WATCHDOG */

#if defined(CONFIG_DDR_ECC)
void dma_init(void) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);

	dma->satr0 = 0x02c40000;
	dma->datr0 = 0x02c40000;
	dma->sr0 = 0xfffffff; /* clear any errors */
	asm("sync; isync; msync");
	return;
}

uint dma_check(void) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
	volatile uint status = dma->sr0;

	/* While the channel is busy, spin */
	while((status & 4) == 4) {
		status = dma->sr0;
	}

	/* clear MR0[CS] channel start bit */
	dma->mr0 &= 0x00000001;
	asm("sync;isync;msync");

	if (status != 0) {
		printf ("DMA Error: status = %x\n", status);
	}
	return status;
}

int dma_xfer(void *dest, uint count, void *src) {
	volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);

	dma->dar0 = (uint) dest;
	dma->sar0 = (uint) src;
	dma->bcr0 = count;
	dma->mr0 = 0xf000004;
	asm("sync;isync;msync");
	dma->mr0 = 0xf000005;
	asm("sync;isync;msync");
	return dma_check();
}
#endif

/*
 * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
 * are hardcoded as "1"."size" is the number or entries, not a sizeof.
 */
void upmconfig (uint upm, uint * table, uint size)
{
	int i, mdr, mad, old_mad = 0;
	volatile u32 *mxmr;
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
	int loopval = 0x00004440;
	volatile u32 *brp,*orp;
	volatile u8* dummy = NULL;
	int upmmask;

	switch (upm) {
	case UPMA:
		mxmr = &lbc->mamr;
		upmmask = BR_MS_UPMA;
		break;
	case UPMB:
		mxmr = &lbc->mbmr;
		upmmask = BR_MS_UPMB;
		break;
	case UPMC:
		mxmr = &lbc->mcmr;
		upmmask = BR_MS_UPMC;
		break;
	default:
		printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
		hang();
	}

	/* Find the address for the dummy write transaction */
	for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
		 i++, brp += 2, orp += 2) {

		/* Look for a valid BR with selected UPM */
		if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
			dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
			break;
		}
	}

	if (i == 8) {
		printf("Error: %s() could not find matching BR\n", __FUNCTION__);
		hang();
	}

	for (i = 0; i < size; i++) {
		/* 1 */
		out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
		/* 2 */
		out_be32(&lbc->mdr, table[i]);
		/* 3 */
		mdr = in_be32(&lbc->mdr);
		/* 4 */
		*(volatile u8 *)dummy = 0;
		/* 5 */
		do {
			mad = in_be32(mxmr) & 0x3f;
		} while (mad <= old_mad && !(!mad && i == (size-1)));
		old_mad = mad;
	}
	out_be32(mxmr, loopval); /* OP_NORMAL */
}


/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
	tsec_standard_init(bis);
#endif

	return 0;
}
Commit	Line	Data
42d1f039	1	/*
1ced1216	2	* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
42d1f039 WD	3	* (C) Copyright 2002, 2003 Motorola Inc.
	4	* Xianghua Xiao (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2000
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
75b9d4ae	28	#include <config.h>
42d1f039 WD	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <command.h>
75b9d4ae	32	#include <tsec.h>
42d1f039	33	#include <asm/cache.h>
740280e6	34	#include <asm/io.h>
42d1f039	35
591933ca JY	36	DECLARE_GLOBAL_DATA_PTR;
591933ca JY	37
4dbdb768 KG	38	struct cpu_type cpu_type_list [] = {
	39	CPU_TYPE_ENTRY(8533, 8533),
	40	CPU_TYPE_ENTRY(8533, 8533_E),
ef50d6c0 KG	41	CPU_TYPE_ENTRY(8536, 8536),
ef50d6c0 KG	42	CPU_TYPE_ENTRY(8536, 8536_E),
4dbdb768 KG	43	CPU_TYPE_ENTRY(8540, 8540),
	44	CPU_TYPE_ENTRY(8541, 8541),
	45	CPU_TYPE_ENTRY(8541, 8541_E),
	46	CPU_TYPE_ENTRY(8543, 8543),
	47	CPU_TYPE_ENTRY(8543, 8543_E),
	48	CPU_TYPE_ENTRY(8544, 8544),
	49	CPU_TYPE_ENTRY(8544, 8544_E),
	50	CPU_TYPE_ENTRY(8545, 8545),
	51	CPU_TYPE_ENTRY(8545, 8545_E),
	52	CPU_TYPE_ENTRY(8547, 8547_E),
	53	CPU_TYPE_ENTRY(8548, 8548),
	54	CPU_TYPE_ENTRY(8548, 8548_E),
	55	CPU_TYPE_ENTRY(8555, 8555),
	56	CPU_TYPE_ENTRY(8555, 8555_E),
	57	CPU_TYPE_ENTRY(8560, 8560),
	58	CPU_TYPE_ENTRY(8567, 8567),
	59	CPU_TYPE_ENTRY(8567, 8567_E),
	60	CPU_TYPE_ENTRY(8568, 8568),
	61	CPU_TYPE_ENTRY(8568, 8568_E),
	62	CPU_TYPE_ENTRY(8572, 8572),
	63	CPU_TYPE_ENTRY(8572, 8572_E),
1ced1216 AF	64	};
1ced1216 AF	65
96026d42	66	struct cpu_type *identify_cpu(u32 ver)
4dbdb768 KG	67	{
	68	int i;
	69	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
	70	if (cpu_type_list[i].soc_ver == ver)
	71	return &cpu_type_list[i];
1ced1216	72
4dbdb768 KG	73	return NULL;
4dbdb768 KG	74	}
1ced1216	75
42d1f039 WD	76	int checkcpu (void)
42d1f039 WD	77	{
97d80fc3 WD	78	sys_info_t sysinfo;
	79	uint lcrr; /* local bus clock ratio register */
	80	uint clkdiv; /* clock divider portion of lcrr */
	81	uint pvr, svr;
d9b94f28	82	uint fam;
97d80fc3 WD	83	uint ver;
97d80fc3 WD	84	uint major, minor;
4dbdb768	85	struct cpu_type *cpu;
ee1e35be	86	#ifdef CONFIG_DDR_CLK_FREQ
d4357932	87	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
ee1e35be KG	88	u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
	89	#else
	90	u32 ddr_ratio = 0;
	91	#endif
97d80fc3	92
97d80fc3	93	svr = get_svr();
1ced1216	94	ver = SVR_SOC_VER(svr);
97d80fc3	95	major = SVR_MAJ(svr);
ef50d6c0 KG	96	#ifdef CONFIG_MPC8536
	97	major &= 0x7; /* the msb of this nibble is a mfg code */
	98	#endif
97d80fc3	99	minor = SVR_MIN(svr);
42d1f039	100
6c9e789e	101	puts("CPU: ");
1ced1216	102
4dbdb768 KG	103	cpu = identify_cpu(ver);
	104	if (cpu) {
	105	puts(cpu->name);
1ced1216	106
06b4186c	107	if (IS_E_PROCESSOR(svr))
4dbdb768 KG	108	puts("E");
4dbdb768 KG	109	} else {
97d80fc3	110	puts("Unknown");
4dbdb768	111	}
1ced1216	112
97d80fc3 WD	113	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
97d80fc3 WD	114
6c9e789e	115	pvr = get_pvr();
d9b94f28	116	fam = PVR_FAM(pvr);
6c9e789e WD	117	ver = PVR_VER(pvr);
	118	major = PVR_MAJ(pvr);
	119	minor = PVR_MIN(pvr);
	120
	121	printf("Core: ");
d9b94f28 JL	122	switch (fam) {
d9b94f28 JL	123	case PVR_FAM(PVR_85xx):
6c9e789e WD	124	puts("E500");
	125	break;
	126	default:
	127	puts("Unknown");
	128	break;
	129	}
	130	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
	131
97d80fc3 WD	132	get_sys_info(&sysinfo);
97d80fc3 WD	133
d9b94f28	134	puts("Clock Configuration:\n");
022f1216 KG	135	printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
022f1216 KG	136	printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
ee1e35be	137
d4357932 KG	138	switch (ddr_ratio) {
d4357932 KG	139	case 0x0:
e9ea6799	140	printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
022f1216	141	DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
d4357932 KG	142	break;
d4357932 KG	143	case 0x7:
e9ea6799	144	printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
022f1216	145	DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
d4357932 KG	146	break;
d4357932 KG	147	default:
e9ea6799	148	printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
022f1216	149	DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
d4357932 KG	150	break;
d4357932 KG	151	}
97d80fc3 WD	152
	153	#if defined(CFG_LBC_LCRR)
	154	lcrr = CFG_LBC_LCRR;
	155	#else
	156	{
04db4008	157	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
97d80fc3 WD	158
	159	lcrr = lbc->lcrr;
	160	}
	161	#endif
	162	clkdiv = lcrr & 0x0f;
	163	if (clkdiv == 2 \|\| clkdiv == 4 \|\| clkdiv == 8) {
ef50d6c0 KG	164	#if defined(CONFIG_MPC8548) \|\| defined(CONFIG_MPC8544) \|\| \
ef50d6c0 KG	165	defined(CONFIG_MPC8572) \|\| defined(CONFIG_MPC8536)
d9b94f28 JL	166	/*
	167	* Yes, the entire PQ38 family use the same
	168	* bit-representation for twice the clock divider values.
	169	*/
	170	clkdiv *= 2;
	171	#endif
97d80fc3	172	printf("LBC:%4lu MHz\n",
022f1216	173	DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
97d80fc3	174	} else {
6c9e789e	175	printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
97d80fc3	176	}
42d1f039	177
1ced1216	178	#ifdef CONFIG_CPM2
6beecfbb	179	printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
1ced1216	180	#endif
97d80fc3	181
6c9e789e	182	puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
42d1f039 WD	183
	184	return 0;
	185	}
	186
	187
	188	/* ------------------------------------------------------------------------- */
	189
	190	int do_reset (cmd_tbl_t cmdtp, bd_t bd, int flag, int argc, char *argv[])
	191	{
96629cba ZR	192	uint pvr;
96629cba ZR	193	uint ver;
793670c3 SP	194	unsigned long val, msr;
793670c3 SP	195
96629cba ZR	196	pvr = get_pvr();
96629cba ZR	197	ver = PVR_VER(pvr);
793670c3	198
96629cba ZR	199	if (ver & 1){
	200	/* e500 v2 core has reset control register */
	201	volatile unsigned int * rstcr;
	202	rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
2f15278c	203	rstcr = 0x2; / HRESET_REQ */
793670c3 SP	204	udelay(100);
	205	}
	206
42d1f039	207	/*
793670c3	208	* Fallthrough if the code above failed
42d1f039 WD	209	* Initiate hard reset in debug control register DBCR0
	210	* Make sure MSR[DE] = 1
	211	*/
df90968b	212
793670c3 SP	213	msr = mfmsr ();
	214	msr \|= MSR_DE;
	215	mtmsr (msr);
	216
	217	val = mfspr(DBCR0);
	218	val \|= 0x70000000;
	219	mtspr(DBCR0,val);
df90968b	220
42d1f039 WD	221	return 1;
	222	}
	223
	224
	225	/*
	226	* Get timebase clock frequency
	227	*/
	228	unsigned long get_tbclk (void)
	229	{
591933ca	230	return (gd->bus_clk + 4UL)/8UL;
42d1f039 WD	231	}
	232
	233
	234	#if defined(CONFIG_WATCHDOG)
	235	void
	236	watchdog_reset(void)
	237	{
	238	int re_enable = disable_interrupts();
	239	reset_85xx_watchdog();
	240	if (re_enable) enable_interrupts();
	241	}
	242
	243	void
	244	reset_85xx_watchdog(void)
	245	{
	246	/*
	247	* Clear TSR(WIS) bit by writing 1
	248	*/
	249	unsigned long val;
03b81b48 AF	250	val = mfspr(SPRN_TSR);
	251	val \|= TSR_WIS;
	252	mtspr(SPRN_TSR, val);
42d1f039 WD	253	}
	254	#endif /* CONFIG_WATCHDOG */
	255
	256	#if defined(CONFIG_DDR_ECC)
42d1f039	257	void dma_init(void) {
04db4008	258	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	259
	260	dma->satr0 = 0x02c40000;
	261	dma->datr0 = 0x02c40000;
03b81b48	262	dma->sr0 = 0xfffffff; /* clear any errors */
42d1f039 WD	263	asm("sync; isync; msync");
	264	return;
	265	}
	266
	267	uint dma_check(void) {
04db4008	268	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	269	volatile uint status = dma->sr0;
	270
	271	/* While the channel is busy, spin */
	272	while((status & 4) == 4) {
	273	status = dma->sr0;
	274	}
	275
03b81b48 AF	276	/* clear MR0[CS] channel start bit */
	277	dma->mr0 &= 0x00000001;
	278	asm("sync;isync;msync");
	279
42d1f039 WD	280	if (status != 0) {
	281	printf ("DMA Error: status = %x\n", status);
	282	}
	283	return status;
	284	}
	285
	286	int dma_xfer(void dest, uint count, void src) {
04db4008	287	volatile ccsr_dma_t dma = (void )(CFG_MPC85xx_DMA_ADDR);
42d1f039 WD	288
	289	dma->dar0 = (uint) dest;
	290	dma->sar0 = (uint) src;
	291	dma->bcr0 = count;
	292	dma->mr0 = 0xf000004;
	293	asm("sync;isync;msync");
	294	dma->mr0 = 0xf000005;
	295	asm("sync;isync;msync");
	296	return dma_check();
	297	}
	298	#endif
75b9d4ae	299
740280e6 SP	300	/*
	301	* Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
	302	* are hardcoded as "1"."size" is the number or entries, not a sizeof.
	303	*/
	304	void upmconfig (uint upm, uint * table, uint size)
	305	{
	306	int i, mdr, mad, old_mad = 0;
	307	volatile u32 *mxmr;
	308	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
	309	int loopval = 0x00004440;
	310	volatile u32 brp,orp;
	311	volatile u8* dummy = NULL;
	312	int upmmask;
	313
	314	switch (upm) {
	315	case UPMA:
	316	mxmr = &lbc->mamr;
	317	upmmask = BR_MS_UPMA;
	318	break;
	319	case UPMB:
	320	mxmr = &lbc->mbmr;
	321	upmmask = BR_MS_UPMB;
	322	break;
	323	case UPMC:
	324	mxmr = &lbc->mcmr;
	325	upmmask = BR_MS_UPMC;
	326	break;
	327	default:
	328	printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
	329	hang();
	330	}
	331
	332	/* Find the address for the dummy write transaction */
	333	for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
	334	i++, brp += 2, orp += 2) {
e093a247	335
740280e6 SP	336	/* Look for a valid BR with selected UPM */
	337	if ((in_be32(brp) & (BR_V \| upmmask)) == (BR_V \| upmmask)) {
	338	dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
	339	break;
	340	}
	341	}
	342
	343	if (i == 8) {
	344	printf("Error: %s() could not find matching BR\n", __FUNCTION__);
	345	hang();
	346	}
	347
	348	for (i = 0; i < size; i++) {
	349	/* 1 */
	350	out_be32(mxmr, loopval \| 0x10000000 \| i); /* OP_WRITE */
	351	/* 2 */
	352	out_be32(&lbc->mdr, table[i]);
	353	/* 3 */
	354	mdr = in_be32(&lbc->mdr);
	355	/* 4 */
	356	(volatile u8 )dummy = 0;
	357	/* 5 */
	358	do {
	359	mad = in_be32(mxmr) & 0x3f;
	360	} while (mad <= old_mad && !(!mad && i == (size-1)));
	361	old_mad = mad;
	362	}
	363	out_be32(mxmr, loopval); /* OP_NORMAL */
	364	}
dd35479a	365
dd35479a	366
75b9d4ae AF	367	/*
	368	* Initializes on-chip ethernet controllers.
	369	* to override, implement board_eth_init()
	370	*/
dd35479a BW	371	int cpu_eth_init(bd_t *bis)
dd35479a BW	372	{
75b9d4ae AF	373	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_MPC85xx_FEC)
75b9d4ae AF	374	tsec_standard_init(bis);
dd35479a	375	#endif
75b9d4ae	376
dd35479a BW	377	return 0;
dd35479a BW	378	}