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42d1f039 | 1 | /* |
18bacc20 | 2 | * Copyright 2004,2007-2009 Freescale Semiconductor, Inc. |
42d1f039 WD |
3 | * (C) Copyright 2002, 2003 Motorola Inc. |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2000 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
75b9d4ae | 28 | #include <config.h> |
42d1f039 WD |
29 | #include <common.h> |
30 | #include <watchdog.h> | |
31 | #include <command.h> | |
80522dc8 | 32 | #include <fsl_esdhc.h> |
42d1f039 | 33 | #include <asm/cache.h> |
740280e6 | 34 | #include <asm/io.h> |
42d1f039 | 35 | |
591933ca JY |
36 | DECLARE_GLOBAL_DATA_PTR; |
37 | ||
42d1f039 WD |
38 | int checkcpu (void) |
39 | { | |
97d80fc3 | 40 | sys_info_t sysinfo; |
97d80fc3 | 41 | uint pvr, svr; |
d9b94f28 | 42 | uint fam; |
97d80fc3 WD |
43 | uint ver; |
44 | uint major, minor; | |
4dbdb768 | 45 | struct cpu_type *cpu; |
08ef89ec | 46 | char buf1[32], buf2[32]; |
ee1e35be | 47 | #ifdef CONFIG_DDR_CLK_FREQ |
6d0f6bcf | 48 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
c0391111 JJ |
49 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
50 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; | |
ee1e35be KG |
51 | #else |
52 | u32 ddr_ratio = 0; | |
53 | #endif | |
2fc7eb0c | 54 | int i; |
97d80fc3 | 55 | |
97d80fc3 | 56 | svr = get_svr(); |
97d80fc3 | 57 | major = SVR_MAJ(svr); |
ef50d6c0 KG |
58 | #ifdef CONFIG_MPC8536 |
59 | major &= 0x7; /* the msb of this nibble is a mfg code */ | |
60 | #endif | |
97d80fc3 | 61 | minor = SVR_MIN(svr); |
42d1f039 | 62 | |
0e870980 PA |
63 | if (cpu_numcores() > 1) { |
64 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); | |
65 | printf("CPU%d: ", pic->whoami); | |
66 | } else { | |
67 | puts("CPU: "); | |
68 | } | |
1ced1216 | 69 | |
0e870980 | 70 | cpu = gd->cpu; |
1ced1216 | 71 | |
ea8be4a6 PA |
72 | puts(cpu->name); |
73 | if (IS_E_PROCESSOR(svr)) | |
74 | puts("E"); | |
1ced1216 | 75 | |
97d80fc3 WD |
76 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
77 | ||
6c9e789e | 78 | pvr = get_pvr(); |
d9b94f28 | 79 | fam = PVR_FAM(pvr); |
6c9e789e WD |
80 | ver = PVR_VER(pvr); |
81 | major = PVR_MAJ(pvr); | |
82 | minor = PVR_MIN(pvr); | |
83 | ||
84 | printf("Core: "); | |
d9b94f28 JL |
85 | switch (fam) { |
86 | case PVR_FAM(PVR_85xx): | |
6c9e789e WD |
87 | puts("E500"); |
88 | break; | |
89 | default: | |
90 | puts("Unknown"); | |
91 | break; | |
92 | } | |
0f060c3b KG |
93 | |
94 | if (PVR_MEM(pvr) == 0x03) | |
95 | puts("MC"); | |
96 | ||
6c9e789e WD |
97 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
98 | ||
97d80fc3 WD |
99 | get_sys_info(&sysinfo); |
100 | ||
b29dee3c | 101 | puts("Clock Configuration:"); |
0e870980 | 102 | for (i = 0; i < cpu_numcores(); i++) { |
1bba30ef WD |
103 | if (!(i & 3)) |
104 | printf ("\n "); | |
2fc7eb0c HW |
105 | printf("CPU%d:%-4s MHz, ", |
106 | i,strmhz(buf1, sysinfo.freqProcessor[i])); | |
b29dee3c KG |
107 | } |
108 | printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); | |
ee1e35be | 109 | |
d4357932 KG |
110 | switch (ddr_ratio) { |
111 | case 0x0: | |
08ef89ec WD |
112 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
113 | strmhz(buf1, sysinfo.freqDDRBus/2), | |
114 | strmhz(buf2, sysinfo.freqDDRBus)); | |
d4357932 KG |
115 | break; |
116 | case 0x7: | |
08ef89ec WD |
117 | printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", |
118 | strmhz(buf1, sysinfo.freqDDRBus/2), | |
119 | strmhz(buf2, sysinfo.freqDDRBus)); | |
d4357932 KG |
120 | break; |
121 | default: | |
08ef89ec WD |
122 | printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", |
123 | strmhz(buf1, sysinfo.freqDDRBus/2), | |
124 | strmhz(buf2, sysinfo.freqDDRBus)); | |
d4357932 KG |
125 | break; |
126 | } | |
97d80fc3 | 127 | |
ada591d2 TP |
128 | if (sysinfo.freqLocalBus > LCRR_CLKDIV) |
129 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); | |
130 | else | |
131 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", | |
132 | sysinfo.freqLocalBus); | |
42d1f039 | 133 | |
1ced1216 | 134 | #ifdef CONFIG_CPM2 |
08ef89ec | 135 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); |
1ced1216 | 136 | #endif |
97d80fc3 | 137 | |
b3d7f20f HW |
138 | #ifdef CONFIG_QE |
139 | printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); | |
140 | #endif | |
141 | ||
6c9e789e | 142 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
42d1f039 WD |
143 | |
144 | return 0; | |
145 | } | |
146 | ||
147 | ||
148 | /* ------------------------------------------------------------------------- */ | |
149 | ||
150 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) | |
151 | { | |
96629cba ZR |
152 | uint pvr; |
153 | uint ver; | |
793670c3 SP |
154 | unsigned long val, msr; |
155 | ||
96629cba ZR |
156 | pvr = get_pvr(); |
157 | ver = PVR_VER(pvr); | |
793670c3 | 158 | |
96629cba ZR |
159 | if (ver & 1){ |
160 | /* e500 v2 core has reset control register */ | |
161 | volatile unsigned int * rstcr; | |
6d0f6bcf | 162 | rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); |
2f15278c | 163 | *rstcr = 0x2; /* HRESET_REQ */ |
793670c3 SP |
164 | udelay(100); |
165 | } | |
166 | ||
42d1f039 | 167 | /* |
793670c3 | 168 | * Fallthrough if the code above failed |
42d1f039 WD |
169 | * Initiate hard reset in debug control register DBCR0 |
170 | * Make sure MSR[DE] = 1 | |
171 | */ | |
df90968b | 172 | |
793670c3 SP |
173 | msr = mfmsr (); |
174 | msr |= MSR_DE; | |
175 | mtmsr (msr); | |
176 | ||
177 | val = mfspr(DBCR0); | |
178 | val |= 0x70000000; | |
179 | mtspr(DBCR0,val); | |
df90968b | 180 | |
42d1f039 WD |
181 | return 1; |
182 | } | |
183 | ||
184 | ||
185 | /* | |
186 | * Get timebase clock frequency | |
187 | */ | |
188 | unsigned long get_tbclk (void) | |
189 | { | |
591933ca | 190 | return (gd->bus_clk + 4UL)/8UL; |
42d1f039 WD |
191 | } |
192 | ||
193 | ||
194 | #if defined(CONFIG_WATCHDOG) | |
195 | void | |
196 | watchdog_reset(void) | |
197 | { | |
198 | int re_enable = disable_interrupts(); | |
199 | reset_85xx_watchdog(); | |
200 | if (re_enable) enable_interrupts(); | |
201 | } | |
202 | ||
203 | void | |
204 | reset_85xx_watchdog(void) | |
205 | { | |
206 | /* | |
207 | * Clear TSR(WIS) bit by writing 1 | |
208 | */ | |
209 | unsigned long val; | |
03b81b48 AF |
210 | val = mfspr(SPRN_TSR); |
211 | val |= TSR_WIS; | |
212 | mtspr(SPRN_TSR, val); | |
42d1f039 WD |
213 | } |
214 | #endif /* CONFIG_WATCHDOG */ | |
215 | ||
740280e6 | 216 | /* |
59f63058 SP |
217 | * Configures a UPM. The function requires the respective MxMR to be set |
218 | * before calling this function. "size" is the number or entries, not a sizeof. | |
740280e6 SP |
219 | */ |
220 | void upmconfig (uint upm, uint * table, uint size) | |
221 | { | |
222 | int i, mdr, mad, old_mad = 0; | |
223 | volatile u32 *mxmr; | |
6d0f6bcf | 224 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
740280e6 SP |
225 | volatile u32 *brp,*orp; |
226 | volatile u8* dummy = NULL; | |
227 | int upmmask; | |
228 | ||
229 | switch (upm) { | |
230 | case UPMA: | |
231 | mxmr = &lbc->mamr; | |
232 | upmmask = BR_MS_UPMA; | |
233 | break; | |
234 | case UPMB: | |
235 | mxmr = &lbc->mbmr; | |
236 | upmmask = BR_MS_UPMB; | |
237 | break; | |
238 | case UPMC: | |
239 | mxmr = &lbc->mcmr; | |
240 | upmmask = BR_MS_UPMC; | |
241 | break; | |
242 | default: | |
243 | printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); | |
244 | hang(); | |
245 | } | |
246 | ||
247 | /* Find the address for the dummy write transaction */ | |
248 | for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; | |
249 | i++, brp += 2, orp += 2) { | |
e093a247 | 250 | |
740280e6 | 251 | /* Look for a valid BR with selected UPM */ |
59f63058 SP |
252 | if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { |
253 | dummy = (volatile u8*)(in_be32(brp) & BR_BA); | |
740280e6 SP |
254 | break; |
255 | } | |
256 | } | |
257 | ||
258 | if (i == 8) { | |
259 | printf("Error: %s() could not find matching BR\n", __FUNCTION__); | |
260 | hang(); | |
261 | } | |
262 | ||
263 | for (i = 0; i < size; i++) { | |
264 | /* 1 */ | |
59f63058 | 265 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); |
740280e6 SP |
266 | /* 2 */ |
267 | out_be32(&lbc->mdr, table[i]); | |
268 | /* 3 */ | |
269 | mdr = in_be32(&lbc->mdr); | |
270 | /* 4 */ | |
271 | *(volatile u8 *)dummy = 0; | |
272 | /* 5 */ | |
273 | do { | |
59f63058 | 274 | mad = in_be32(mxmr) & MxMR_MAD_MSK; |
740280e6 SP |
275 | } while (mad <= old_mad && !(!mad && i == (size-1))); |
276 | old_mad = mad; | |
277 | } | |
59f63058 | 278 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); |
740280e6 | 279 | } |
dd35479a | 280 | |
80522dc8 AF |
281 | /* |
282 | * Initializes on-chip MMC controllers. | |
283 | * to override, implement board_mmc_init() | |
284 | */ | |
285 | int cpu_mmc_init(bd_t *bis) | |
286 | { | |
287 | #ifdef CONFIG_FSL_ESDHC | |
288 | return fsl_esdhc_mmc_init(bis); | |
289 | #else | |
290 | return 0; | |
291 | #endif | |
292 | } |