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ec2b74ff | 1 | /* |
0e870980 | 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. |
ec2b74ff KG |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <asm/processor.h> | |
25 | #include <ioports.h> | |
dd6c910a | 26 | #include <lmb.h> |
ec2b74ff | 27 | #include <asm/io.h> |
c7259086 | 28 | #include <asm/mmu.h> |
ec2b74ff KG |
29 | #include "mp.h" |
30 | ||
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | ||
ec2b74ff KG |
33 | u32 get_my_id() |
34 | { | |
35 | return mfspr(SPRN_PIR); | |
36 | } | |
37 | ||
38 | int cpu_reset(int nr) | |
39 | { | |
6d0f6bcf | 40 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); |
ec2b74ff | 41 | out_be32(&pic->pir, 1 << nr); |
c840d26c | 42 | /* the dummy read works around an errata on early 85xx MP PICs */ |
ec2b74ff KG |
43 | (void)in_be32(&pic->pir); |
44 | out_be32(&pic->pir, 0x0); | |
45 | ||
46 | return 0; | |
47 | } | |
48 | ||
49 | int cpu_status(int nr) | |
50 | { | |
51 | u32 *table, id = get_my_id(); | |
52 | ||
53 | if (nr == id) { | |
54 | table = (u32 *)get_spin_addr(); | |
348753d4 | 55 | printf("table base @ 0x%p\n", table); |
ec2b74ff KG |
56 | } else { |
57 | table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; | |
58 | printf("Running on cpu %d\n", id); | |
59 | printf("\n"); | |
348753d4 | 60 | printf("table @ 0x%p\n", table); |
79679d80 | 61 | printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); |
ec2b74ff | 62 | printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); |
79679d80 KG |
63 | printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); |
64 | printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); | |
ec2b74ff KG |
65 | } |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
79679d80 KG |
70 | static u8 boot_entry_map[4] = { |
71 | 0, | |
72 | BOOT_ENTRY_PIR, | |
73 | BOOT_ENTRY_R3_LOWER, | |
74 | BOOT_ENTRY_R6_LOWER, | |
75 | }; | |
76 | ||
77 | int cpu_release(int nr, int argc, char *argv[]) | |
ec2b74ff KG |
78 | { |
79 | u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; | |
79679d80 | 80 | u64 boot_addr; |
ec2b74ff KG |
81 | |
82 | if (nr == get_my_id()) { | |
83 | printf("Invalid to release the boot core.\n\n"); | |
84 | return 1; | |
85 | } | |
86 | ||
79679d80 | 87 | if (argc != 4) { |
ec2b74ff KG |
88 | printf("Invalid number of arguments to release.\n\n"); |
89 | return 1; | |
90 | } | |
91 | ||
6d0f6bcf | 92 | #ifdef CONFIG_SYS_64BIT_STRTOUL |
79679d80 KG |
93 | boot_addr = simple_strtoull(argv[0], NULL, 16); |
94 | #else | |
95 | boot_addr = simple_strtoul(argv[0], NULL, 16); | |
96 | #endif | |
97 | ||
98 | /* handle pir, r3, r6 */ | |
99 | for (i = 1; i < 4; i++) { | |
ec2b74ff | 100 | if (argv[i][0] != '-') { |
79679d80 | 101 | u8 entry = boot_entry_map[i]; |
ec2b74ff | 102 | val = simple_strtoul(argv[i], NULL, 16); |
79679d80 | 103 | table[entry] = val; |
ec2b74ff KG |
104 | } |
105 | } | |
106 | ||
79679d80 | 107 | table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); |
cf6cc014 KG |
108 | |
109 | /* ensure all table updates complete before final address write */ | |
110 | eieio(); | |
111 | ||
79679d80 | 112 | table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); |
ec2b74ff KG |
113 | |
114 | return 0; | |
115 | } | |
116 | ||
c840d26c KG |
117 | u32 determine_mp_bootpg(void) |
118 | { | |
119 | /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ | |
120 | if ((u64)gd->ram_size > 0xfffff000) | |
121 | return (0xfffff000); | |
122 | ||
123 | return (gd->ram_size - 4096); | |
124 | } | |
125 | ||
ec2b74ff KG |
126 | ulong get_spin_addr(void) |
127 | { | |
128 | extern ulong __secondary_start_page; | |
129 | extern ulong __spin_table; | |
130 | ||
131 | ulong addr = | |
132 | (ulong)&__spin_table - (ulong)&__secondary_start_page; | |
133 | addr += 0xfffff000; | |
134 | ||
135 | return addr; | |
136 | } | |
137 | ||
138 | static void pq3_mp_up(unsigned long bootpg) | |
139 | { | |
140 | u32 up, cpu_up_mask, whoami; | |
141 | u32 *table = (u32 *)get_spin_addr(); | |
142 | volatile u32 bpcr; | |
6d0f6bcf JCPV |
143 | volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); |
144 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
145 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); | |
ec2b74ff KG |
146 | u32 devdisr; |
147 | int timeout = 10; | |
148 | ||
149 | whoami = in_be32(&pic->whoami); | |
150 | out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); | |
151 | ||
152 | /* disable time base at the platform */ | |
153 | devdisr = in_be32(&gur->devdisr); | |
154 | if (whoami) | |
155 | devdisr |= MPC85xx_DEVDISR_TB0; | |
156 | else | |
157 | devdisr |= MPC85xx_DEVDISR_TB1; | |
158 | out_be32(&gur->devdisr, devdisr); | |
159 | ||
160 | /* release the hounds */ | |
0e870980 | 161 | up = ((1 << cpu_numcores()) - 1); |
ec2b74ff KG |
162 | bpcr = in_be32(&ecm->eebpcr); |
163 | bpcr |= (up << 24); | |
164 | out_be32(&ecm->eebpcr, bpcr); | |
165 | asm("sync; isync; msync"); | |
166 | ||
167 | cpu_up_mask = 1 << whoami; | |
168 | /* wait for everyone */ | |
169 | while (timeout) { | |
170 | int i; | |
0e870980 | 171 | for (i = 0; i < cpu_numcores(); i++) { |
97b3ecb5 | 172 | if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) |
ec2b74ff KG |
173 | cpu_up_mask |= (1 << i); |
174 | }; | |
175 | ||
176 | if ((cpu_up_mask & up) == up) | |
177 | break; | |
178 | ||
179 | udelay(100); | |
180 | timeout--; | |
181 | } | |
182 | ||
97b3ecb5 KG |
183 | if (timeout == 0) |
184 | printf("CPU up timeout. CPU up mask is %x should be %x\n", | |
185 | cpu_up_mask, up); | |
186 | ||
ec2b74ff KG |
187 | /* enable time base at the platform */ |
188 | if (whoami) | |
189 | devdisr |= MPC85xx_DEVDISR_TB1; | |
190 | else | |
191 | devdisr |= MPC85xx_DEVDISR_TB0; | |
192 | out_be32(&gur->devdisr, devdisr); | |
193 | mtspr(SPRN_TBWU, 0); | |
194 | mtspr(SPRN_TBWL, 0); | |
195 | ||
196 | devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); | |
197 | out_be32(&gur->devdisr, devdisr); | |
198 | } | |
199 | ||
dd6c910a KG |
200 | void cpu_mp_lmb_reserve(struct lmb *lmb) |
201 | { | |
c840d26c | 202 | u32 bootpg = determine_mp_bootpg(); |
dd6c910a KG |
203 | |
204 | lmb_reserve(lmb, bootpg, 4096); | |
205 | } | |
206 | ||
ec2b74ff KG |
207 | void setup_mp(void) |
208 | { | |
209 | extern ulong __secondary_start_page; | |
210 | ulong fixup = (ulong)&__secondary_start_page; | |
c840d26c | 211 | u32 bootpg = determine_mp_bootpg(); |
ec2b74ff | 212 | |
c7259086 KG |
213 | /* look for the tlb covering the reset page, there better be one */ |
214 | int i = find_tlb_idx((void *)0xfffff000, 1); | |
ec2b74ff | 215 | |
c7259086 KG |
216 | /* we found a match */ |
217 | if (i != -1) { | |
218 | /* map reset page to bootpg so we can copy code there */ | |
219 | disable_tlb(i); | |
220 | ||
221 | set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ | |
222 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ | |
223 | 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ | |
224 | ||
225 | memcpy((void *)0xfffff000, (void *)fixup, 4096); | |
226 | flush_cache(0xfffff000, 4096); | |
227 | ||
228 | disable_tlb(i); | |
229 | ||
230 | /* setup reset page back to 1:1, we'll use HW boot translation | |
231 | * to map this where we want | |
232 | */ | |
233 | set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */ | |
234 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ | |
235 | 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ | |
236 | ||
237 | pq3_mp_up(bootpg); | |
238 | } else { | |
239 | puts("WARNING: No reset page TLB. " | |
240 | "Skipping secondary core setup\n"); | |
241 | } | |
ec2b74ff | 242 | } |