[people/ms/u-boot.git] / cpu / mpc85xx / mp.c

/*
 * Copyright 2008-2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <ioports.h>
#include <lmb.h>
#include <asm/io.h>
#include "mp.h"

DECLARE_GLOBAL_DATA_PTR;

u32 get_my_id()
{
	return mfspr(SPRN_PIR);
}

int cpu_reset(int nr)
{
	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
	out_be32(&pic->pir, 1 << nr);
	/* the dummy read works around an errata on early 85xx MP PICs */
	(void)in_be32(&pic->pir);
	out_be32(&pic->pir, 0x0);

	return 0;
}

int cpu_status(int nr)
{
	u32 *table, id = get_my_id();

	if (nr == id) {
		table = (u32 *)get_spin_addr();
		printf("table base @ 0x%p\n", table);
	} else {
		table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
		printf("Running on cpu %d\n", id);
		printf("\n");
		printf("table @ 0x%p\n", table);
		printf("   addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
		printf("   r3   - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
		printf("   r6   - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
	}

	return 0;
}

static u8 boot_entry_map[4] = {
	0,
	BOOT_ENTRY_PIR,
	BOOT_ENTRY_R3_LOWER,
	BOOT_ENTRY_R6_LOWER,
};

int cpu_release(int nr, int argc, char *argv[])
{
	u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
	u64 boot_addr;

	if (nr == get_my_id()) {
		printf("Invalid to release the boot core.\n\n");
		return 1;
	}

	if (argc != 4) {
		printf("Invalid number of arguments to release.\n\n");
		return 1;
	}

#ifdef CONFIG_SYS_64BIT_STRTOUL
	boot_addr = simple_strtoull(argv[0], NULL, 16);
#else
	boot_addr = simple_strtoul(argv[0], NULL, 16);
#endif

	/* handle pir, r3, r6 */
	for (i = 1; i < 4; i++) {
		if (argv[i][0] != '-') {
			u8 entry = boot_entry_map[i];
			val = simple_strtoul(argv[i], NULL, 16);
			table[entry] = val;
		}
	}

	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);

	/* ensure all table updates complete before final address write */
	eieio();

	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);

	return 0;
}

u32 determine_mp_bootpg(void)
{
	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
	if ((u64)gd->ram_size > 0xfffff000)
		return (0xfffff000);

	return (gd->ram_size - 4096);
}

ulong get_spin_addr(void)
{
	extern ulong __secondary_start_page;
	extern ulong __spin_table;

	ulong addr =
		(ulong)&__spin_table - (ulong)&__secondary_start_page;
	addr += 0xfffff000;

	return addr;
}

static void pq3_mp_up(unsigned long bootpg)
{
	u32 up, cpu_up_mask, whoami;
	u32 *table = (u32 *)get_spin_addr();
	volatile u32 bpcr;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
	u32 devdisr;
	int timeout = 10;

	whoami = in_be32(&pic->whoami);
	out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));

	/* disable time base at the platform */
	devdisr = in_be32(&gur->devdisr);
	if (whoami)
		devdisr |= MPC85xx_DEVDISR_TB0;
	else
		devdisr |= MPC85xx_DEVDISR_TB1;
	out_be32(&gur->devdisr, devdisr);

	/* release the hounds */
	up = ((1 << cpu_numcores()) - 1);
	bpcr = in_be32(&ecm->eebpcr);
	bpcr |= (up << 24);
	out_be32(&ecm->eebpcr, bpcr);
	asm("sync; isync; msync");

	cpu_up_mask = 1 << whoami;
	/* wait for everyone */
	while (timeout) {
		int i;
		for (i = 0; i < cpu_numcores(); i++) {
			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
				cpu_up_mask |= (1 << i);
		};

		if ((cpu_up_mask & up) == up)
			break;

		udelay(100);
		timeout--;
	}

	if (timeout == 0)
		printf("CPU up timeout. CPU up mask is %x should be %x\n",
			cpu_up_mask, up);

	/* enable time base at the platform */
	if (whoami)
		devdisr |= MPC85xx_DEVDISR_TB1;
	else
		devdisr |= MPC85xx_DEVDISR_TB0;
	out_be32(&gur->devdisr, devdisr);
	mtspr(SPRN_TBWU, 0);
	mtspr(SPRN_TBWL, 0);

	devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
	out_be32(&gur->devdisr, devdisr);
}

void cpu_mp_lmb_reserve(struct lmb *lmb)
{
	u32 bootpg = determine_mp_bootpg();

	lmb_reserve(lmb, bootpg, 4096);
}

void setup_mp(void)
{
	extern ulong __secondary_start_page;
	ulong fixup = (ulong)&__secondary_start_page;
	u32 bootpg = determine_mp_bootpg();

	memcpy((void *)bootpg, (void *)fixup, 4096);
	flush_cache(bootpg, 4096);

	pq3_mp_up(bootpg);
}
Commit	Line	Data
ec2b74ff	1	/*
0e870980	2	* Copyright 2008-2009 Freescale Semiconductor, Inc.
ec2b74ff KG	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <asm/processor.h>
	25	#include <ioports.h>
dd6c910a	26	#include <lmb.h>
ec2b74ff KG	27	#include <asm/io.h>
	28	#include "mp.h"
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
ec2b74ff KG	32	u32 get_my_id()
	33	{
	34	return mfspr(SPRN_PIR);
	35	}
	36
	37	int cpu_reset(int nr)
	38	{
6d0f6bcf	39	volatile ccsr_pic_t pic = (void )(CONFIG_SYS_MPC85xx_PIC_ADDR);
ec2b74ff	40	out_be32(&pic->pir, 1 << nr);
c840d26c	41	/* the dummy read works around an errata on early 85xx MP PICs */
ec2b74ff KG	42	(void)in_be32(&pic->pir);
	43	out_be32(&pic->pir, 0x0);
	44
	45	return 0;
	46	}
	47
	48	int cpu_status(int nr)
	49	{
	50	u32 *table, id = get_my_id();
	51
	52	if (nr == id) {
	53	table = (u32 *)get_spin_addr();
348753d4	54	printf("table base @ 0x%p\n", table);
ec2b74ff KG	55	} else {
	56	table = (u32 )get_spin_addr() + nr NUM_BOOT_ENTRY;
	57	printf("Running on cpu %d\n", id);
	58	printf("\n");
348753d4	59	printf("table @ 0x%p\n", table);
79679d80	60	printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
ec2b74ff	61	printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
79679d80 KG	62	printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
79679d80 KG	63	printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
ec2b74ff KG	64	}
	65
	66	return 0;
	67	}
	68
79679d80 KG	69	static u8 boot_entry_map[4] = {
	70	0,
	71	BOOT_ENTRY_PIR,
	72	BOOT_ENTRY_R3_LOWER,
	73	BOOT_ENTRY_R6_LOWER,
	74	};
	75
	76	int cpu_release(int nr, int argc, char *argv[])
ec2b74ff KG	77	{
ec2b74ff KG	78	u32 i, val, table = (u32 )get_spin_addr() + nr * NUM_BOOT_ENTRY;
79679d80	79	u64 boot_addr;
ec2b74ff KG	80
	81	if (nr == get_my_id()) {
	82	printf("Invalid to release the boot core.\n\n");
	83	return 1;
	84	}
	85
79679d80	86	if (argc != 4) {
ec2b74ff KG	87	printf("Invalid number of arguments to release.\n\n");
	88	return 1;
	89	}
	90
6d0f6bcf	91	#ifdef CONFIG_SYS_64BIT_STRTOUL
79679d80 KG	92	boot_addr = simple_strtoull(argv[0], NULL, 16);
	93	#else
	94	boot_addr = simple_strtoul(argv[0], NULL, 16);
	95	#endif
	96
	97	/* handle pir, r3, r6 */
	98	for (i = 1; i < 4; i++) {
ec2b74ff	99	if (argv[i][0] != '-') {
79679d80	100	u8 entry = boot_entry_map[i];
ec2b74ff	101	val = simple_strtoul(argv[i], NULL, 16);
79679d80	102	table[entry] = val;
ec2b74ff KG	103	}
	104	}
	105
79679d80	106	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
cf6cc014 KG	107
	108	/* ensure all table updates complete before final address write */
	109	eieio();
	110
79679d80	111	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
ec2b74ff KG	112
	113	return 0;
	114	}
	115
c840d26c KG	116	u32 determine_mp_bootpg(void)
	117	{
	118	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
	119	if ((u64)gd->ram_size > 0xfffff000)
	120	return (0xfffff000);
	121
	122	return (gd->ram_size - 4096);
	123	}
	124
ec2b74ff KG	125	ulong get_spin_addr(void)
	126	{
	127	extern ulong __secondary_start_page;
	128	extern ulong __spin_table;
	129
	130	ulong addr =
	131	(ulong)&__spin_table - (ulong)&__secondary_start_page;
	132	addr += 0xfffff000;
	133
	134	return addr;
	135	}
	136
	137	static void pq3_mp_up(unsigned long bootpg)
	138	{
	139	u32 up, cpu_up_mask, whoami;
	140	u32 table = (u32 )get_spin_addr();
	141	volatile u32 bpcr;
6d0f6bcf JCPV	142	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	143	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	144	volatile ccsr_pic_t pic = (void )(CONFIG_SYS_MPC85xx_PIC_ADDR);
ec2b74ff KG	145	u32 devdisr;
	146	int timeout = 10;
	147
	148	whoami = in_be32(&pic->whoami);
	149	out_be32(&ecm->bptr, 0x80000000 \| (bootpg >> 12));
	150
	151	/* disable time base at the platform */
	152	devdisr = in_be32(&gur->devdisr);
	153	if (whoami)
	154	devdisr \|= MPC85xx_DEVDISR_TB0;
	155	else
	156	devdisr \|= MPC85xx_DEVDISR_TB1;
	157	out_be32(&gur->devdisr, devdisr);
	158
	159	/* release the hounds */
0e870980	160	up = ((1 << cpu_numcores()) - 1);
ec2b74ff KG	161	bpcr = in_be32(&ecm->eebpcr);
	162	bpcr \|= (up << 24);
	163	out_be32(&ecm->eebpcr, bpcr);
	164	asm("sync; isync; msync");
	165
	166	cpu_up_mask = 1 << whoami;
	167	/* wait for everyone */
	168	while (timeout) {
	169	int i;
0e870980	170	for (i = 0; i < cpu_numcores(); i++) {
97b3ecb5	171	if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
ec2b74ff KG	172	cpu_up_mask \|= (1 << i);
	173	};
	174
	175	if ((cpu_up_mask & up) == up)
	176	break;
	177
	178	udelay(100);
	179	timeout--;
	180	}
	181
97b3ecb5 KG	182	if (timeout == 0)
	183	printf("CPU up timeout. CPU up mask is %x should be %x\n",
	184	cpu_up_mask, up);
	185
ec2b74ff KG	186	/* enable time base at the platform */
	187	if (whoami)
	188	devdisr \|= MPC85xx_DEVDISR_TB1;
	189	else
	190	devdisr \|= MPC85xx_DEVDISR_TB0;
	191	out_be32(&gur->devdisr, devdisr);
	192	mtspr(SPRN_TBWU, 0);
	193	mtspr(SPRN_TBWL, 0);
	194
	195	devdisr &= ~(MPC85xx_DEVDISR_TB0 \| MPC85xx_DEVDISR_TB1);
	196	out_be32(&gur->devdisr, devdisr);
	197	}
	198
dd6c910a KG	199	void cpu_mp_lmb_reserve(struct lmb *lmb)
dd6c910a KG	200	{
c840d26c	201	u32 bootpg = determine_mp_bootpg();
dd6c910a KG	202
	203	lmb_reserve(lmb, bootpg, 4096);
	204	}
	205
ec2b74ff KG	206	void setup_mp(void)
	207	{
	208	extern ulong __secondary_start_page;
	209	ulong fixup = (ulong)&__secondary_start_page;
c840d26c	210	u32 bootpg = determine_mp_bootpg();
ec2b74ff KG	211
	212	memcpy((void )bootpg, (void )fixup, 4096);
	213	flush_cache(bootpg, 4096);
	214
	215	pq3_mp_up(bootpg);
	216	}