[people/ms/u-boot.git] / cpu / mpc85xx / serial_scc.c

/*
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 * Modified based on 8260 for 8560.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
 */

/*
 * Minimal serial functions needed to use one of the SCC ports
 * as serial console interface.
 */

#include <common.h>
#include <asm/cpm_85xx.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CPM2)
#if defined(CONFIG_CONS_ON_SCC)

#if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */

#define SCC_INDEX		0
#define PROFF_SCC		PROFF_SCC1
#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK

#elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */

#define SCC_INDEX		1
#define PROFF_SCC		PROFF_SCC2
#define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK

#elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */

#define SCC_INDEX		2
#define PROFF_SCC		PROFF_SCC3
#define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK

#elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */

#define SCC_INDEX		3
#define PROFF_SCC		PROFF_SCC4
#define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
#define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
#define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK

#else

#error "console not correctly defined"

#endif

int serial_init (void)
{
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	volatile ccsr_cpm_scc_t *sp;
	volatile scc_uart_t *up;
	volatile cbd_t *tbdf, *rbdf;
	volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
	uint	dpaddr;

	/* initialize pointers to SCC */

	sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);

	/* Disable transmitter/receiver.
	*/
	sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	/* put the SCC channel into NMSI (non multiplexd serial interface)
	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
	 */
	cpm->im_cpm_mux.cmxscr = \
		(cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;

	/* Set up the baud rate generator.
	*/
	serial_setbrg ();

	/* Allocate space for two buffer descriptors in the DP ram.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
	tbdf = rbdf + 1;
	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	tbdf->cbd_sc = BD_SC_WRAP;

	/* Set up the uart parameters in the parameter ram.
	*/
	up->scc_genscc.scc_rbase = dpaddr;
	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	up->scc_genscc.scc_rfcr = CPMFCR_EB;
	up->scc_genscc.scc_tfcr = CPMFCR_EB;
	up->scc_genscc.scc_mrblr = 1;
	up->scc_maxidl = 0;
	up->scc_brkcr = 1;
	up->scc_parec = 0;
	up->scc_frmec = 0;
	up->scc_nosec = 0;
	up->scc_brkec = 0;
	up->scc_uaddr1 = 0;
	up->scc_uaddr2 = 0;
	up->scc_toseq = 0;
	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
	up->scc_rccm = 0xc0ff;

	/* Mask all interrupts and remove anything pending.
	*/
	sp->sccm = 0;
	sp->scce = 0xffff;

	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
	*/
	sp->gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
	sp->gsmrl = \
		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;

	/* Set CTS no flow control, 1 stop bit, 8 bit character length,
	 * normal async UART mode, no parity
	 */
	sp->psmr = SCU_PSMR_CL;

	/* execute the "Init Rx and Tx params" CP command.
	*/

	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	/* Enable transmitter/receiver.
	*/
	sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;

	return (0);
}

void
serial_setbrg (void)
{
#if defined(CONFIG_CONS_USE_EXTC)
	m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
#else
	m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
#endif
}

void
serial_putc(const char c)
{
	volatile scc_uart_t	*up;
	volatile cbd_t		*tbdf;
	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;

	if (c == '\n')
		serial_putc ('\r');

	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
	tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);

	/* Wait for last character to go.
	 */
	while (tbdf->cbd_sc & BD_SC_READY)
		;

	/* Load the character into the transmit buffer.
	 */
	*(volatile char *)tbdf->cbd_bufaddr = c;
	tbdf->cbd_datlen = 1;
	tbdf->cbd_sc |= BD_SC_READY;
}

void
serial_puts (const char *s)
{
	while (*s) {
		serial_putc (*s++);
	}
}

int
serial_getc(void)
{
	volatile cbd_t		*rbdf;
	volatile scc_uart_t	*up;
	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	unsigned char		c;

	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);

	/* Wait for character to show up.
	 */
	while (rbdf->cbd_sc & BD_SC_EMPTY)
		;

	/* Grab the char and clear the buffer again.
	 */
	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
	rbdf->cbd_sc |= BD_SC_EMPTY;

	return (c);
}

int
serial_tstc()
{
	volatile cbd_t		*rbdf;
	volatile scc_uart_t	*up;
	volatile ccsr_cpm_t	*cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;

	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);

	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}

#endif	/* CONFIG_CONS_ON_SCC */

#endif /* CONFIG_CPM2 */
Commit	Line	Data
42d1f039 WD	1	/*
	2	* (C) Copyright 2003 Motorola Inc.
	3	* Xianghua Xiao (X.Xiao@motorola.com)
	4	* Modified based on 8260 for 8560.
	5	*
	6	* (C) Copyright 2000
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*
	27	* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
	28	*/
	29
	30	/*
	31	* Minimal serial functions needed to use one of the SCC ports
	32	* as serial console interface.
	33	*/
	34
	35	#include <common.h>
	36	#include <asm/cpm_85xx.h>
	37
d87080b7 WD	38	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	39
9c4c5ae3	40	#if defined(CONFIG_CPM2)
42d1f039 WD	41	#if defined(CONFIG_CONS_ON_SCC)
	42
	43	#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
	44
	45	#define SCC_INDEX 0
	46	#define PROFF_SCC PROFF_SCC1
	47	#define CMXSCR_MASK (CMXSCR_GR1\|CMXSCR_SC1\|\
	48	CMXSCR_RS1CS_MSK\|CMXSCR_TS1CS_MSK)
	49	#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1\|CMXSCR_TS1CS_BRG1)
	50	#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
	51	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
	52
	53	#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
	54
	55	#define SCC_INDEX 1
	56	#define PROFF_SCC PROFF_SCC2
	57	#define CMXSCR_MASK (CMXSCR_GR2\|CMXSCR_SC2\|\
	58	CMXSCR_RS2CS_MSK\|CMXSCR_TS2CS_MSK)
	59	#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2\|CMXSCR_TS2CS_BRG2)
	60	#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
	61	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
	62
	63	#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
	64
	65	#define SCC_INDEX 2
	66	#define PROFF_SCC PROFF_SCC3
	67	#define CMXSCR_MASK (CMXSCR_GR3\|CMXSCR_SC3\|\
	68	CMXSCR_RS3CS_MSK\|CMXSCR_TS3CS_MSK)
	69	#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3\|CMXSCR_TS3CS_BRG3)
	70	#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
	71	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
	72
	73	#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
	74
	75	#define SCC_INDEX 3
	76	#define PROFF_SCC PROFF_SCC4
	77	#define CMXSCR_MASK (CMXSCR_GR4\|CMXSCR_SC4\|\
	78	CMXSCR_RS4CS_MSK\|CMXSCR_TS4CS_MSK)
	79	#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4\|CMXSCR_TS4CS_BRG4)
	80	#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
	81	#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
	82
	83	#else
	84
	85	#error "console not correctly defined"
	86
	87	#endif
	88
	89	int serial_init (void)
	90	{
6d0f6bcf	91	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	92	volatile ccsr_cpm_scc_t *sp;
	93	volatile scc_uart_t *up;
	94	volatile cbd_t tbdf, rbdf;
aafeefbd	95	volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
42d1f039 WD	96	uint dpaddr;
	97
	98	/* initialize pointers to SCC */
	99
aafeefbd KG	100	sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]);
aafeefbd KG	101	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
42d1f039 WD	102
	103	/* Disable transmitter/receiver.
	104	*/
	105	sp->gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	106
	107	/* put the SCC channel into NMSI (non multiplexd serial interface)
	108	* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
	109	*/
aafeefbd KG	110	cpm->im_cpm_mux.cmxscr = \
aafeefbd KG	111	(cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)\|CMXSCR_VALUE;
42d1f039 WD	112
	113	/* Set up the baud rate generator.
	114	*/
	115	serial_setbrg ();
	116
	117	/* Allocate space for two buffer descriptors in the DP ram.
	118	* damm: allocating space after the two buffers for rx/tx data
	119	*/
	120
	121	dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
	122
	123	/* Set the physical address of the host memory buffers in
	124	* the buffer descriptors.
	125	*/
aafeefbd	126	rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]);
42d1f039 WD	127	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	128	rbdf->cbd_sc = BD_SC_EMPTY \| BD_SC_WRAP;
	129	tbdf = rbdf + 1;
	130	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	131	tbdf->cbd_sc = BD_SC_WRAP;
	132
	133	/* Set up the uart parameters in the parameter ram.
	134	*/
	135	up->scc_genscc.scc_rbase = dpaddr;
	136	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	137	up->scc_genscc.scc_rfcr = CPMFCR_EB;
	138	up->scc_genscc.scc_tfcr = CPMFCR_EB;
	139	up->scc_genscc.scc_mrblr = 1;
	140	up->scc_maxidl = 0;
	141	up->scc_brkcr = 1;
	142	up->scc_parec = 0;
	143	up->scc_frmec = 0;
	144	up->scc_nosec = 0;
	145	up->scc_brkec = 0;
	146	up->scc_uaddr1 = 0;
	147	up->scc_uaddr2 = 0;
	148	up->scc_toseq = 0;
	149	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
	150	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
	151	up->scc_rccm = 0xc0ff;
	152
	153	/* Mask all interrupts and remove anything pending.
	154	*/
	155	sp->sccm = 0;
	156	sp->scce = 0xffff;
	157
	158	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
	159	*/
	160	sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
	161	sp->gsmrl = \
	162	SCC_GSMRL_TDCR_16 \| SCC_GSMRL_RDCR_16 \| SCC_GSMRL_MODE_UART;
	163
	164	/* Set CTS no flow control, 1 stop bit, 8 bit character length,
	165	* normal async UART mode, no parity
	166	*/
	167	sp->psmr = SCU_PSMR_CL;
	168
	169	/* execute the "Init Rx and Tx params" CP command.
	170	*/
	171
	172	while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
	173	;
	174
	175	cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
	176	0, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
	177
	178	while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
	179	;
	180
	181	/* Enable transmitter/receiver.
	182	*/
	183	sp->gsmrl \|= SCC_GSMRL_ENR \| SCC_GSMRL_ENT;
	184
	185	return (0);
	186	}
	187
	188	void
	189	serial_setbrg (void)
	190	{
42d1f039 WD	191	#if defined(CONFIG_CONS_USE_EXTC)
	192	m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
	193	CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
	194	#else
	195	m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
	196	#endif
	197	}
	198
	199	void
	200	serial_putc(const char c)
	201	{
	202	volatile scc_uart_t *up;
	203	volatile cbd_t *tbdf;
6d0f6bcf	204	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	205
	206	if (c == '\n')
	207	serial_putc ('\r');
	208
aafeefbd KG	209	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
aafeefbd KG	210	tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]);
42d1f039 WD	211
	212	/* Wait for last character to go.
	213	*/
	214	while (tbdf->cbd_sc & BD_SC_READY)
	215	;
	216
	217	/* Load the character into the transmit buffer.
	218	*/
	219	(volatile char )tbdf->cbd_bufaddr = c;
	220	tbdf->cbd_datlen = 1;
	221	tbdf->cbd_sc \|= BD_SC_READY;
	222	}
	223
	224	void
	225	serial_puts (const char *s)
	226	{
	227	while (*s) {
	228	serial_putc (*s++);
	229	}
	230	}
	231
	232	int
	233	serial_getc(void)
	234	{
	235	volatile cbd_t *rbdf;
	236	volatile scc_uart_t *up;
6d0f6bcf	237	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	238	unsigned char c;
42d1f039 WD	239
aafeefbd KG	240	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
aafeefbd KG	241	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
42d1f039 WD	242
	243	/* Wait for character to show up.
	244	*/
	245	while (rbdf->cbd_sc & BD_SC_EMPTY)
	246	;
	247
	248	/* Grab the char and clear the buffer again.
	249	*/
	250	c = (volatile unsigned char )rbdf->cbd_bufaddr;
	251	rbdf->cbd_sc \|= BD_SC_EMPTY;
	252
	253	return (c);
	254	}
	255
	256	int
	257	serial_tstc()
	258	{
	259	volatile cbd_t *rbdf;
	260	volatile scc_uart_t *up;
6d0f6bcf	261	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039	262
aafeefbd KG	263	up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]);
aafeefbd KG	264	rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]);
42d1f039 WD	265
	266	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
	267	}
	268
	269	#endif /* CONFIG_CONS_ON_SCC */
	270
9c4c5ae3	271	#endif /* CONFIG_CPM2 */