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Fix crash on sequoia in ppc_4xx_eth_init
[people/ms/u-boot.git] / cpu / mpc85xx / speed.c
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42d1f039 1/*
97d80fc3 2 * Copyright 2004 Freescale Semiconductor.
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3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <ppc_asm.tmpl>
30#include <asm/processor.h>
31
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32DECLARE_GLOBAL_DATA_PTR;
33
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34/* --------------------------------------------------------------- */
35
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36void get_sys_info (sys_info_t * sysInfo)
37{
f59b55a5 38 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
66ed6cca 39 uint plat_ratio,e500_ratio,half_freqSystemBus;
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40
41 plat_ratio = (gur->porpllsr) & 0x0000003e;
42 plat_ratio >>= 1;
66ed6cca 43 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
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44 e500_ratio = (gur->porpllsr) & 0x003f0000;
45 e500_ratio >>= 16;
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46
47 /* Divide before multiply to avoid integer
48 * overflow for processor speeds above 2GHz */
49 half_freqSystemBus = sysInfo->freqSystemBus/2;
50 sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
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51
52 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
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53 sysInfo->freqDDRBus = sysInfo->freqSystemBus;
54
55#ifdef CONFIG_DDR_CLK_FREQ
56 {
57 u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
58 if (ddr_ratio != 0x7)
59 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
60 }
61#endif
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62}
63
66ed6cca 64
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65int get_clocks (void)
66{
42d1f039 67 sys_info_t sys_info;
9c4c5ae3 68#if defined(CONFIG_CPM2)
aafeefbd 69 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
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70 uint sccr, dfbrg;
71
72 /* set VCO = 4 * BRG */
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73 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
74 sccr = cpm->im_cpm_intctl.sccr;
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75 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
76#endif
77 get_sys_info (&sys_info);
78 gd->cpu_clk = sys_info.freqProcessor;
79 gd->bus_clk = sys_info.freqSystemBus;
a3e77fa5 80 gd->mem_clk = sys_info.freqDDRBus;
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81 gd->i2c1_clk = sys_info.freqSystemBus;
82 gd->i2c2_clk = sys_info.freqSystemBus;
83
9c4c5ae3 84#if defined(CONFIG_CPM2)
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85 gd->vco_out = 2*sys_info.freqSystemBus;
86 gd->cpm_clk = gd->vco_out / 2;
87 gd->scc_clk = gd->vco_out / 4;
88 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
89#endif
90
91 if(gd->cpu_clk != 0) return (0);
92 else return (1);
93}
94
95
96/********************************************
97 * get_bus_freq
98 * return system bus freq in Hz
99 *********************************************/
100ulong get_bus_freq (ulong dummy)
101{
a3e77fa5 102 return gd->bus_clk;
42d1f039 103}
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104
105/********************************************
106 * get_ddr_freq
107 * return ddr bus freq in Hz
108 *********************************************/
109ulong get_ddr_freq (ulong dummy)
110{
a3e77fa5 111 return gd->mem_clk;
d4357932 112}