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1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * (C) Copyright 2000 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/mmu.h> | |
ecf5b98c KG |
29 | #ifdef CONFIG_ADDR_MAP |
30 | #include <addr_map.h> | |
31 | #endif | |
32 | ||
33 | DECLARE_GLOBAL_DATA_PTR; | |
44a23cfd KG |
34 | |
35 | void set_tlb(u8 tlb, u32 epn, u64 rpn, | |
36 | u8 perms, u8 wimge, | |
37 | u8 ts, u8 esel, u8 tsize, u8 iprot) | |
38 | { | |
39 | u32 _mas0, _mas1, _mas2, _mas3, _mas7; | |
40 | ||
41 | _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); | |
42 | _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); | |
43 | _mas2 = FSL_BOOKE_MAS2(epn, wimge); | |
44 | _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); | |
45 | _mas7 = rpn >> 32; | |
46 | ||
47 | mtspr(MAS0, _mas0); | |
48 | mtspr(MAS1, _mas1); | |
49 | mtspr(MAS2, _mas2); | |
50 | mtspr(MAS3, _mas3); | |
51 | #ifdef CONFIG_ENABLE_36BIT_PHYS | |
52 | mtspr(MAS7, _mas7); | |
53 | #endif | |
54 | asm volatile("isync;msync;tlbwe;isync"); | |
ecf5b98c KG |
55 | |
56 | #ifdef CONFIG_ADDR_MAP | |
57 | if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) | |
58 | addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); | |
59 | #endif | |
44a23cfd KG |
60 | } |
61 | ||
62 | void disable_tlb(u8 esel) | |
63 | { | |
64 | u32 _mas0, _mas1, _mas2, _mas3, _mas7; | |
65 | ||
66 | _mas0 = FSL_BOOKE_MAS0(1, esel, 0); | |
67 | _mas1 = 0; | |
68 | _mas2 = 0; | |
69 | _mas3 = 0; | |
70 | _mas7 = 0; | |
71 | ||
72 | mtspr(MAS0, _mas0); | |
73 | mtspr(MAS1, _mas1); | |
74 | mtspr(MAS2, _mas2); | |
75 | mtspr(MAS3, _mas3); | |
76 | #ifdef CONFIG_ENABLE_36BIT_PHYS | |
77 | mtspr(MAS7, _mas7); | |
78 | #endif | |
79 | asm volatile("isync;msync;tlbwe;isync"); | |
ecf5b98c KG |
80 | |
81 | #ifdef CONFIG_ADDR_MAP | |
82 | if (gd->flags & GD_FLG_RELOC) | |
83 | addrmap_set_entry(0, 0, 0, esel); | |
84 | #endif | |
44a23cfd KG |
85 | } |
86 | ||
87 | void invalidate_tlb(u8 tlb) | |
88 | { | |
89 | if (tlb == 0) | |
90 | mtspr(MMUCSR0, 0x4); | |
91 | if (tlb == 1) | |
92 | mtspr(MMUCSR0, 0x2); | |
93 | } | |
94 | ||
95 | void init_tlbs(void) | |
96 | { | |
44a23cfd KG |
97 | int i; |
98 | ||
99 | for (i = 0; i < num_tlb_entries; i++) { | |
100 | set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, | |
101 | tlb_table[i].perms, tlb_table[i].wimge, | |
102 | tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, | |
103 | tlb_table[i].iprot); | |
104 | } | |
44a23cfd KG |
105 | |
106 | return ; | |
107 | } | |
6fb1b734 | 108 | |
ecf5b98c KG |
109 | #ifdef CONFIG_ADDR_MAP |
110 | void init_addr_map(void) | |
111 | { | |
112 | int i; | |
113 | ||
114 | for (i = 0; i < num_tlb_entries; i++) { | |
115 | if (tlb_table[i].tlb == 0) | |
116 | continue; | |
117 | ||
118 | addrmap_set_entry(tlb_table[i].epn, | |
119 | tlb_table[i].rpn, | |
120 | (1UL << ((tlb_table[i].tsize * 2) + 10)), | |
121 | tlb_table[i].esel); | |
122 | } | |
123 | ||
124 | return ; | |
125 | } | |
126 | #endif | |
127 | ||
95026431 HW |
128 | #ifndef CONFIG_SYS_DDR_TLB_START |
129 | #define CONFIG_SYS_DDR_TLB_START 8 | |
130 | #endif | |
131 | ||
6fb1b734 KG |
132 | unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) |
133 | { | |
134 | unsigned int tlb_size; | |
f8523cb0 KG |
135 | unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; |
136 | unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; | |
90d13b8a | 137 | unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; |
f8523cb0 | 138 | u64 size, memsize = (u64)memsize_in_meg << 20; |
6fb1b734 | 139 | |
f8523cb0 KG |
140 | size = min(memsize, CONFIG_MAX_MEM_MAPPED); |
141 | ||
142 | /* Convert (4^max) kB to (2^max) bytes */ | |
143 | max_cam = max_cam * 2 + 10; | |
144 | ||
145 | for (; size && ram_tlb_index < 16; ram_tlb_index++) { | |
146 | u32 camsize = __ilog2_u64(size) & ~1U; | |
147 | u32 align = __ilog2(ram_tlb_address) & ~1U; | |
148 | ||
149 | if (align == -2) align = max_cam; | |
150 | if (camsize > align) | |
151 | camsize = align; | |
152 | ||
153 | if (camsize > max_cam) | |
154 | camsize = max_cam; | |
155 | ||
156 | tlb_size = (camsize - 10) / 2; | |
6fb1b734 | 157 | |
6fb1b734 KG |
158 | set_tlb(1, ram_tlb_address, ram_tlb_address, |
159 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
160 | 0, ram_tlb_index, tlb_size, 1); | |
161 | ||
f8523cb0 KG |
162 | size -= 1ULL << camsize; |
163 | memsize -= 1ULL << camsize; | |
164 | ram_tlb_address += 1UL << camsize; | |
6fb1b734 KG |
165 | } |
166 | ||
f8523cb0 KG |
167 | if (memsize) |
168 | printf("%lldM left unmapped\n", memsize >> 20); | |
169 | ||
6fb1b734 KG |
170 | /* |
171 | * Confirm that the requested amount of memory was mapped. | |
172 | */ | |
173 | return memsize_in_meg; | |
174 | } |