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debb7354 JL |
1 | /* |
2 | * Copyright 2004 Freescale Semiconductor. | |
c934f655 | 3 | * Jeff Brown |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * cpu_init.c - low level cpu init | |
27 | */ | |
28 | ||
2d0daa03 | 29 | #include <config.h> |
debb7354 JL |
30 | #include <common.h> |
31 | #include <mpc86xx.h> | |
2d0daa03 | 32 | #include <asm/mmu.h> |
83d1b387 | 33 | #include <asm/fsl_law.h> |
debb7354 | 34 | |
1218abf1 WD |
35 | DECLARE_GLOBAL_DATA_PTR; |
36 | ||
debb7354 JL |
37 | /* |
38 | * Breathe some life into the CPU... | |
39 | * | |
40 | * Set up the memory map | |
41 | * initialize a bunch of registers | |
42 | */ | |
43 | ||
5c9efb36 | 44 | void cpu_init_f(void) |
debb7354 | 45 | { |
6d0f6bcf | 46 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
debb7354 | 47 | volatile ccsr_lbc_t *memctl = &immap->im_lbc; |
5c9efb36 | 48 | |
ffff3ae5 | 49 | /* Pointer is writable since we allocated a register for it */ |
6d0f6bcf | 50 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
debb7354 JL |
51 | |
52 | /* Clear initial global data */ | |
53 | memset ((void *) gd, 0, sizeof (gd_t)); | |
54 | ||
4933b91f BB |
55 | #ifdef CONFIG_FSL_LAW |
56 | init_laws(); | |
57 | #endif | |
58 | ||
debb7354 JL |
59 | /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary |
60 | * addresses - these have to be modified later when FLASH size | |
61 | * has been determined | |
62 | */ | |
63 | ||
6d0f6bcf JCPV |
64 | #if defined(CONFIG_SYS_OR0_REMAP) |
65 | memctl->or0 = CONFIG_SYS_OR0_REMAP; | |
debb7354 | 66 | #endif |
6d0f6bcf JCPV |
67 | #if defined(CONFIG_SYS_OR1_REMAP) |
68 | memctl->or1 = CONFIG_SYS_OR1_REMAP; | |
debb7354 JL |
69 | #endif |
70 | ||
71 | /* now restrict to preliminary range */ | |
6d0f6bcf JCPV |
72 | #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) |
73 | memctl->br0 = CONFIG_SYS_BR0_PRELIM; | |
74 | memctl->or0 = CONFIG_SYS_OR0_PRELIM; | |
debb7354 JL |
75 | #endif |
76 | ||
6d0f6bcf JCPV |
77 | #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) |
78 | memctl->or1 = CONFIG_SYS_OR1_PRELIM; | |
79 | memctl->br1 = CONFIG_SYS_BR1_PRELIM; | |
debb7354 JL |
80 | #endif |
81 | ||
6d0f6bcf JCPV |
82 | #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) |
83 | memctl->or2 = CONFIG_SYS_OR2_PRELIM; | |
84 | memctl->br2 = CONFIG_SYS_BR2_PRELIM; | |
debb7354 | 85 | #endif |
5c9efb36 | 86 | |
6d0f6bcf JCPV |
87 | #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) |
88 | memctl->or3 = CONFIG_SYS_OR3_PRELIM; | |
89 | memctl->br3 = CONFIG_SYS_BR3_PRELIM; | |
debb7354 | 90 | #endif |
5c9efb36 | 91 | |
6d0f6bcf JCPV |
92 | #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) |
93 | memctl->or4 = CONFIG_SYS_OR4_PRELIM; | |
94 | memctl->br4 = CONFIG_SYS_BR4_PRELIM; | |
debb7354 | 95 | #endif |
5c9efb36 | 96 | |
6d0f6bcf JCPV |
97 | #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) |
98 | memctl->or5 = CONFIG_SYS_OR5_PRELIM; | |
99 | memctl->br5 = CONFIG_SYS_BR5_PRELIM; | |
debb7354 JL |
100 | #endif |
101 | ||
6d0f6bcf JCPV |
102 | #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) |
103 | memctl->or6 = CONFIG_SYS_OR6_PRELIM; | |
104 | memctl->br6 = CONFIG_SYS_BR6_PRELIM; | |
debb7354 JL |
105 | #endif |
106 | ||
6d0f6bcf JCPV |
107 | #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) |
108 | memctl->or7 = CONFIG_SYS_OR7_PRELIM; | |
109 | memctl->br7 = CONFIG_SYS_BR7_PRELIM; | |
debb7354 JL |
110 | #endif |
111 | ||
112 | /* enable the timebase bit in HID0 */ | |
113 | set_hid0(get_hid0() | 0x4000000); | |
114 | ||
cfc7a7f5 JL |
115 | /* enable EMCP, SYNCBE | ABE bits in HID1 */ |
116 | set_hid1(get_hid1() | 0x80000C00); | |
debb7354 JL |
117 | } |
118 | ||
119 | /* | |
120 | * initialize higher level parts of CPU like timers | |
121 | */ | |
5c9efb36 | 122 | int cpu_init_r(void) |
debb7354 | 123 | { |
5c9efb36 | 124 | return 0; |
debb7354 | 125 | } |
2d0daa03 BB |
126 | |
127 | /* Set up BAT registers */ | |
128 | void setup_bats(void) | |
129 | { | |
6d0f6bcf JCPV |
130 | write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); |
131 | write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); | |
132 | write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); | |
133 | write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); | |
134 | write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); | |
135 | write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); | |
136 | write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); | |
137 | write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); | |
138 | write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); | |
139 | write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); | |
140 | write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); | |
141 | write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); | |
142 | write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); | |
143 | write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); | |
144 | write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); | |
145 | write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); | |
2d0daa03 BB |
146 | |
147 | return; | |
148 | } |