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debb7354 | 1 | /* |
fa7db9c3 JZR |
2 | * Copyright (C) Freescale Semiconductor,Inc. |
3 | * 2005, 2006. All rights reserved. | |
4 | * | |
debb7354 | 5 | * Ed Swarthout (ed.swarthout@freescale.com) |
fa7db9c3 | 6 | * Jason Jin (Jason.jin@freescale.com) |
debb7354 JL |
7 | * |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
fa7db9c3 | 28 | * PCIE Configuration space access support for PCIE Bridge |
debb7354 JL |
29 | */ |
30 | #include <common.h> | |
31 | #include <pci.h> | |
32 | ||
debb7354 | 33 | #if defined(CONFIG_PCI) |
debb7354 JL |
34 | void |
35 | pci_mpc86xx_init(struct pci_controller *hose) | |
36 | { | |
37 | volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; | |
fa7db9c3 JZR |
38 | volatile ccsr_pex_t *pcie1 = &immap->im_pex1; |
39 | u16 temp16; | |
40 | u32 temp32; | |
41 | ||
debb7354 JL |
42 | volatile ccsr_gur_t *gur = &immap->im_gur; |
43 | uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; | |
fa7db9c3 JZR |
44 | uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); |
45 | uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); | |
46 | uint devdisr = gur->devdisr; | |
47 | uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; | |
48 | ||
49 | if ((io_sel ==2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || | |
50 | io_sel == 7 || io_sel == 0xf) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){ | |
51 | printf ("PCI-EXPRESS 1: Configured as %s \n", | |
52 | pcie1_agent ? "Agent" : "Host"); | |
53 | if(pcie1_agent) return; /*Don't scan bus when configured as agent*/ | |
54 | printf (" Scanning PCIE bus"); | |
55 | debug("0x%08x=0x%08x ", &pcie1->pme_msg_det,pcie1->pme_msg_det); | |
56 | if (pcie1->pme_msg_det) { | |
57 | pcie1->pme_msg_det = 0xffffffff; | |
58 | debug (" with errors. Clearing. Now 0x%08x", | |
59 | pcie1->pme_msg_det); | |
60 | } | |
61 | debug ("\n"); | |
62 | } | |
63 | else{ | |
64 | printf("PCI-EXPRESS 1 disabled!\n"); | |
65 | return; | |
66 | } | |
debb7354 | 67 | |
fa7db9c3 JZR |
68 | /*set first_bus=0 only skipped B0:D0:F0 which is |
69 | * a reserved device in M1575, but make it easy for | |
70 | * most of the scan process. | |
71 | */ | |
72 | hose->first_busno = 0x00; | |
73 | hose->last_busno = 0xfe; | |
debb7354 | 74 | |
fa7db9c3 | 75 | pcie_setup_indirect(hose, |
debb7354 JL |
76 | (CFG_IMMR+0x8000), |
77 | (CFG_IMMR+0x8004)); | |
78 | ||
fa7db9c3 JZR |
79 | pci_hose_read_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, &temp16); |
80 | temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | | |
81 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; | |
82 | pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, temp16); | |
debb7354 | 83 | |
fa7db9c3 JZR |
84 | pci_hose_write_config_word(hose,PCI_BDF(0,0,0), PCI_STATUS, 0xffff); |
85 | pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 0x80); | |
debb7354 | 86 | |
fa7db9c3 JZR |
87 | pci_hose_read_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, &temp32); |
88 | temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); | |
89 | pci_hose_write_config_dword(hose, PCI_BDF(0,0,0), PCI_PRIMARY_BUS, temp32); | |
debb7354 | 90 | |
fa7db9c3 JZR |
91 | pcie1->powar1 = 0; |
92 | pcie1->powar2 = 0; | |
93 | pcie1->piwar1 = 0; | |
94 | pcie1->piwar1 = 0; | |
debb7354 | 95 | |
fa7db9c3 JZR |
96 | pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; |
97 | pcie1->powar1 = 0x8004401c; /* 512M MEM space */ | |
98 | pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; | |
99 | pcie1->potear1 = 0x00000000; | |
debb7354 | 100 | |
fa7db9c3 JZR |
101 | pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; |
102 | pcie1->powar2 = 0x80088017; /* 16M IO space */ | |
103 | pcie1->potar2 = 0x00000000; | |
104 | pcie1->potear2 = 0x00000000; | |
debb7354 | 105 | |
fa7db9c3 JZR |
106 | pcie1->pitar1 = 0x00000000; |
107 | pcie1->piwbar1 = 0x00000000; | |
108 | /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ | |
109 | pcie1->piwar1 = 0xa0f5501e; | |
debb7354 | 110 | |
fa7db9c3 JZR |
111 | pci_set_region(hose->regions + 0, |
112 | CFG_PCI_MEMORY_BUS, | |
113 | CFG_PCI_MEMORY_PHYS, | |
114 | CFG_PCI_MEMORY_SIZE, | |
115 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
debb7354 | 116 | |
fa7db9c3 JZR |
117 | pci_set_region(hose->regions + 1, |
118 | CFG_PCI1_MEM_BASE, | |
119 | CFG_PCI1_MEM_PHYS, | |
120 | CFG_PCI1_MEM_SIZE, | |
121 | PCI_REGION_MEM); | |
debb7354 | 122 | |
fa7db9c3 JZR |
123 | pci_set_region(hose->regions + 2, |
124 | CFG_PCI1_IO_BASE, | |
125 | CFG_PCI1_IO_PHYS, | |
126 | CFG_PCI1_IO_SIZE, | |
127 | PCI_REGION_IO); | |
debb7354 | 128 | |
fa7db9c3 | 129 | hose->region_count = 3; |
debb7354 | 130 | |
fa7db9c3 | 131 | pci_register_hose(hose); |
debb7354 | 132 | |
5c9efb36 | 133 | hose->last_busno = pci_hose_scan(hose); |
fa7db9c3 JZR |
134 | debug("pcie_mpc86xx_init: last_busno %x\n",hose->last_busno); |
135 | debug("pcie_mpc86xx init: current_busno %x\n ",hose->current_busno); | |
debb7354 | 136 | |
fa7db9c3 | 137 | printf("....PCIE1 scan & enumeration done\n"); |
debb7354 JL |
138 | } |
139 | #endif /* CONFIG_PCI */ |