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debb7354 JL |
1 | /* |
2 | * Copyright 2004 Freescale Semiconductor. | |
3 | * (C) Copyright 2003 Motorola Inc. | |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <asm/processor.h> | |
27 | #include <i2c.h> | |
28 | #include <spd.h> | |
29 | #include <asm/mmu.h> | |
30 | ||
31 | ||
32 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
33 | extern void dma_init(void); | |
34 | extern uint dma_check(void); | |
35 | extern int dma_xfer(void *dest, uint count, void *src); | |
36 | #endif | |
37 | ||
38 | #ifdef CONFIG_SPD_EEPROM | |
39 | ||
40 | #ifndef CFG_READ_SPD | |
41 | #define CFG_READ_SPD i2c_read | |
42 | #endif | |
43 | ||
9a655876 JL |
44 | /* |
45 | * Only one of the following three should be 1; others should be 0 | |
46 | * By default the cache line interleaving is selected if | |
91a414c7 | 47 | * the CONFIG_DDR_INTERLEAVE flag is defined |
9a655876 JL |
48 | */ |
49 | #define CFG_PAGE_INTERLEAVING 0 | |
50 | #define CFG_BANK_INTERLEAVING 0 | |
51 | #define CFG_SUPER_BANK_INTERLEAVING 0 | |
52 | ||
debb7354 JL |
53 | /* |
54 | * Convert picoseconds into clock cycles (rounding up if needed). | |
55 | */ | |
56 | ||
57 | int | |
58 | picos_to_clk(int picos) | |
59 | { | |
60 | int clks; | |
61 | ||
62 | clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); | |
63 | if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { | |
64 | clks++; | |
65 | } | |
66 | ||
67 | return clks; | |
68 | } | |
69 | ||
70 | ||
71 | /* | |
72 | * Calculate the Density of each Physical Rank. | |
73 | * Returned size is in bytes. | |
74 | * | |
75 | * Study these table from Byte 31 of JEDEC SPD Spec. | |
76 | * | |
77 | * DDR I DDR II | |
78 | * Bit Size Size | |
79 | * --- ----- ------ | |
80 | * 7 high 512MB 512MB | |
81 | * 6 256MB 256MB | |
82 | * 5 128MB 128MB | |
83 | * 4 64MB 16GB | |
84 | * 3 32MB 8GB | |
85 | * 2 16MB 4GB | |
86 | * 1 2GB 2GB | |
87 | * 0 low 1GB 1GB | |
88 | * | |
89 | * Reorder Table to be linear by stripping the bottom | |
90 | * 2 or 5 bits off and shifting them up to the top. | |
91 | */ | |
92 | ||
93 | unsigned int | |
94 | compute_banksize(unsigned int mem_type, unsigned char row_dens) | |
95 | { | |
96 | unsigned int bsize; | |
97 | ||
98 | if (mem_type == SPD_MEMTYPE_DDR) { | |
99 | /* Bottom 2 bits up to the top. */ | |
100 | bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; | |
101 | debug("DDR: DDR I rank density = 0x%08x\n", bsize); | |
102 | } else { | |
103 | /* Bottom 5 bits up to the top. */ | |
104 | bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27; | |
105 | debug("DDR: DDR II rank density = 0x%08x\n", bsize); | |
106 | } | |
107 | return bsize; | |
108 | } | |
109 | ||
110 | ||
111 | /* | |
112 | * Convert a two-nibble BCD value into a cycle time. | |
113 | * While the spec calls for nano-seconds, picos are returned. | |
114 | * | |
115 | * This implements the tables for bytes 9, 23 and 25 for both | |
116 | * DDR I and II. No allowance for distinguishing the invalid | |
117 | * fields absent for DDR I yet present in DDR II is made. | |
118 | * (That is, cycle times of .25, .33, .66 and .75 ns are | |
119 | * allowed for both DDR II and I.) | |
120 | */ | |
121 | ||
122 | unsigned int | |
123 | convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) | |
124 | { | |
125 | /* | |
126 | * Table look up the lower nibble, allow DDR I & II. | |
127 | */ | |
128 | unsigned int tenths_ps[16] = { | |
129 | 0, | |
130 | 100, | |
131 | 200, | |
132 | 300, | |
133 | 400, | |
134 | 500, | |
135 | 600, | |
136 | 700, | |
137 | 800, | |
138 | 900, | |
139 | 250, | |
91a414c7 JT |
140 | 330, |
141 | 660, | |
debb7354 JL |
142 | 750, |
143 | 0, /* undefined */ | |
144 | 0 /* undefined */ | |
145 | }; | |
146 | ||
147 | unsigned int whole_ns = (spd_val & 0xF0) >> 4; | |
148 | unsigned int tenth_ns = spd_val & 0x0F; | |
149 | unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; | |
150 | ||
151 | return ps; | |
152 | } | |
153 | ||
154 | ||
1fd5699a JL |
155 | /* |
156 | * Determine Refresh Rate. Ignore self refresh bit on DDR I. | |
157 | * Table from SPD Spec, Byte 12, converted to picoseconds and | |
158 | * filled in with "default" normal values. | |
159 | */ | |
160 | unsigned int determine_refresh_rate(unsigned int spd_refresh) | |
161 | { | |
162 | unsigned int refresh_time_ns[8] = { | |
163 | 15625000, /* 0 Normal 1.00x */ | |
164 | 3900000, /* 1 Reduced .25x */ | |
165 | 7800000, /* 2 Extended .50x */ | |
166 | 31300000, /* 3 Extended 2.00x */ | |
167 | 62500000, /* 4 Extended 4.00x */ | |
168 | 125000000, /* 5 Extended 8.00x */ | |
169 | 15625000, /* 6 Normal 1.00x filler */ | |
170 | 15625000, /* 7 Normal 1.00x filler */ | |
171 | }; | |
172 | ||
173 | return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]); | |
174 | } | |
175 | ||
176 | ||
debb7354 | 177 | long int |
9a655876 JL |
178 | spd_init(unsigned char i2c_address, unsigned int ddr_num, |
179 | unsigned int dimm_num, unsigned int start_addr) | |
debb7354 JL |
180 | { |
181 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
9a655876 | 182 | volatile ccsr_ddr_t *ddr; |
debb7354 JL |
183 | volatile ccsr_gur_t *gur = &immap->im_gur; |
184 | spd_eeprom_t spd; | |
185 | unsigned int n_ranks; | |
186 | unsigned int rank_density; | |
187 | unsigned int odt_rd_cfg, odt_wr_cfg; | |
188 | unsigned int odt_cfg, mode_odt_enable; | |
1fd5699a JL |
189 | unsigned int refresh_clk; |
190 | #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL | |
191 | unsigned char clk_adjust; | |
192 | #endif | |
debb7354 JL |
193 | unsigned int dqs_cfg; |
194 | unsigned char twr_clk, twtr_clk, twr_auto_clk; | |
195 | unsigned int tCKmin_ps, tCKmax_ps; | |
91a414c7 | 196 | unsigned int max_data_rate; |
debb7354 | 197 | unsigned int busfreq; |
debb7354 JL |
198 | unsigned int memsize; |
199 | unsigned char caslat, caslat_ctrl; | |
200 | unsigned int trfc, trfc_clk, trfc_low, trfc_high; | |
201 | unsigned int trcd_clk; | |
202 | unsigned int trtp_clk; | |
203 | unsigned char cke_min_clk; | |
204 | unsigned char add_lat; | |
205 | unsigned char wr_lat; | |
206 | unsigned char wr_data_delay; | |
207 | unsigned char four_act; | |
208 | unsigned char cpo; | |
209 | unsigned char burst_len; | |
210 | unsigned int mode_caslat; | |
debb7354 | 211 | unsigned char d_init; |
91a414c7 | 212 | unsigned int tCycle_ps, modfreq; |
debb7354 | 213 | |
9a655876 JL |
214 | if (ddr_num == 1) |
215 | ddr = &immap->im_ddr1; | |
216 | else | |
217 | ddr = &immap->im_ddr2; | |
5c9efb36 | 218 | |
debb7354 JL |
219 | /* |
220 | * Read SPD information. | |
221 | */ | |
9a655876 JL |
222 | debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); |
223 | memset((void *)&spd, 0, sizeof(spd)); | |
224 | CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); | |
debb7354 JL |
225 | |
226 | /* | |
227 | * Check for supported memory module types. | |
228 | */ | |
229 | if (spd.mem_type != SPD_MEMTYPE_DDR && | |
230 | spd.mem_type != SPD_MEMTYPE_DDR2) { | |
9a655876 JL |
231 | debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n" |
232 | " Fundamental memory type is 0x%0x\n", | |
233 | dimm_num, | |
234 | ddr_num, | |
235 | spd.mem_type); | |
debb7354 JL |
236 | return 0; |
237 | } | |
238 | ||
9a655876 JL |
239 | debug("\nFound memory of type 0x%02lx ", spd.mem_type); |
240 | if (spd.mem_type == SPD_MEMTYPE_DDR) | |
241 | debug("DDR I\n"); | |
242 | else | |
243 | debug("DDR II\n"); | |
244 | ||
debb7354 JL |
245 | /* |
246 | * These test gloss over DDR I and II differences in interpretation | |
247 | * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks | |
248 | * are not supported on DDR I; and not encoded on DDR II. | |
249 | * | |
250 | * Also note that the 8548 controller can support: | |
251 | * 12 <= nrow <= 16 | |
252 | * and | |
253 | * 8 <= ncol <= 11 (still, for DDR) | |
254 | * 6 <= ncol <= 9 (for FCRAM) | |
255 | */ | |
256 | if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { | |
257 | printf("DDR: Unsupported number of Row Addr lines: %d.\n", | |
258 | spd.nrow_addr); | |
259 | return 0; | |
260 | } | |
261 | if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { | |
262 | printf("DDR: Unsupported number of Column Addr lines: %d.\n", | |
263 | spd.ncol_addr); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | /* | |
268 | * Determine the number of physical banks controlled by | |
269 | * different Chip Select signals. This is not quite the | |
270 | * same as the number of DIMM modules on the board. Feh. | |
271 | */ | |
272 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
273 | n_ranks = spd.nrows; | |
274 | } else { | |
275 | n_ranks = (spd.nrows & 0x7) + 1; | |
276 | } | |
277 | ||
278 | debug("DDR: number of ranks = %d\n", n_ranks); | |
279 | ||
280 | if (n_ranks > 2) { | |
281 | printf("DDR: Only 2 chip selects are supported: %d\n", | |
282 | n_ranks); | |
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
2ccceacc | 287 | * Adjust DDR II IO voltage biasing. Rev1 only |
debb7354 | 288 | */ |
2ccceacc | 289 | if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { |
debb7354 JL |
290 | gur->ddrioovcr = (0 |
291 | | 0x80000000 /* Enable */ | |
292 | | 0x10000000 /* VSEL to 1.8V */ | |
293 | ); | |
294 | } | |
295 | ||
296 | /* | |
297 | * Determine the size of each Rank in bytes. | |
298 | */ | |
299 | rank_density = compute_banksize(spd.mem_type, spd.row_dens); | |
300 | ||
9a655876 | 301 | debug("Start address for this controller is 0x%08lx\n", start_addr); |
debb7354 JL |
302 | |
303 | /* | |
304 | * ODT configuration recommendation from DDR Controller Chapter. | |
305 | */ | |
306 | odt_rd_cfg = 0; /* Never assert ODT */ | |
307 | odt_wr_cfg = 0; /* Never assert ODT */ | |
308 | if (spd.mem_type == SPD_MEMTYPE_DDR2) { | |
309 | odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ | |
310 | } | |
311 | ||
9a655876 | 312 | #ifdef CONFIG_DDR_INTERLEAVE |
91a414c7 | 313 | |
9a655876 JL |
314 | if (dimm_num != 1) { |
315 | printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); | |
316 | return 0; | |
317 | } else { | |
318 | /* | |
319 | * Since interleaved memory only uses CS0, the | |
320 | * memory sticks have to be identical in size and quantity | |
321 | * of ranks. That essentially gives double the size on | |
322 | * one rank, i.e on CS0 for both controllers put together. | |
323 | * Confirm this??? | |
324 | */ | |
325 | rank_density *= 2; | |
debb7354 | 326 | |
debb7354 | 327 | /* |
9a655876 JL |
328 | * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg |
329 | */ | |
330 | start_addr = 0; | |
331 | ddr->cs0_bnds = (start_addr >> 8) | |
332 | | (((start_addr + rank_density - 1) >> 24)); | |
333 | /* | |
334 | * Default interleaving mode to cache-line interleaving. | |
debb7354 | 335 | */ |
9a655876 JL |
336 | ddr->cs0_config = ( 1 << 31 |
337 | #if (CFG_PAGE_INTERLEAVING == 1) | |
338 | | (PAGE_INTERLEAVING) | |
339 | #elif (CFG_BANK_INTERLEAVING == 1) | |
340 | | (BANK_INTERLEAVING) | |
341 | #elif (CFG_SUPER_BANK_INTERLEAVING == 1) | |
342 | | (SUPER_BANK_INTERLEAVING) | |
343 | #else | |
344 | | (CACHE_LINE_INTERLEAVING) | |
345 | #endif | |
debb7354 JL |
346 | | (odt_rd_cfg << 20) |
347 | | (odt_wr_cfg << 16) | |
348 | | (spd.nrow_addr - 12) << 8 | |
349 | | (spd.ncol_addr - 8) ); | |
9a655876 JL |
350 | |
351 | debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); | |
352 | debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); | |
353 | ||
354 | /* | |
355 | * Adjustment for dual rank memory to get correct memory | |
356 | * size (return value of this function). | |
357 | */ | |
358 | if (n_ranks == 2) { | |
359 | n_ranks = 1; | |
360 | rank_density /= 2; | |
361 | } else { | |
362 | rank_density /= 2; | |
363 | } | |
debb7354 | 364 | } |
9a655876 JL |
365 | #else /* CONFIG_DDR_INTERLEAVE */ |
366 | ||
367 | if (dimm_num == 1) { | |
368 | /* | |
369 | * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg | |
370 | */ | |
371 | ddr->cs0_bnds = (start_addr >> 8) | |
372 | | (((start_addr + rank_density - 1) >> 24)); | |
373 | ||
374 | ddr->cs0_config = ( 1 << 31 | |
375 | | (odt_rd_cfg << 20) | |
376 | | (odt_wr_cfg << 16) | |
377 | | (spd.nrow_addr - 12) << 8 | |
378 | | (spd.ncol_addr - 8) ); | |
379 | ||
380 | debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); | |
381 | debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); | |
382 | ||
383 | if (n_ranks == 2) { | |
384 | /* | |
385 | * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, | |
386 | * second 256 Meg | |
387 | */ | |
388 | ddr->cs1_bnds = (((start_addr + rank_density) >> 8) | |
389 | | (( start_addr + 2*rank_density - 1) | |
390 | >> 24)); | |
391 | ddr->cs1_config = ( 1<<31 | |
392 | | (odt_rd_cfg << 20) | |
393 | | (odt_wr_cfg << 16) | |
394 | | (spd.nrow_addr - 12) << 8 | |
395 | | (spd.ncol_addr - 8) ); | |
396 | debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); | |
397 | debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); | |
398 | } | |
399 | ||
400 | } else { | |
401 | /* | |
402 | * This is the 2nd DIMM slot for this controller | |
403 | */ | |
404 | /* | |
405 | * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg | |
406 | */ | |
407 | ddr->cs2_bnds = (start_addr >> 8) | |
408 | | (((start_addr + rank_density - 1) >> 24)); | |
409 | ||
410 | ddr->cs2_config = ( 1 << 31 | |
411 | | (odt_rd_cfg << 20) | |
412 | | (odt_wr_cfg << 16) | |
413 | | (spd.nrow_addr - 12) << 8 | |
414 | | (spd.ncol_addr - 8) ); | |
415 | ||
416 | debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds); | |
417 | debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config); | |
418 | ||
419 | if (n_ranks == 2) { | |
420 | /* | |
421 | * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, | |
422 | * second 256 Meg | |
423 | */ | |
424 | ddr->cs3_bnds = (((start_addr + rank_density) >> 8) | |
425 | | (( start_addr + 2*rank_density - 1) | |
426 | >> 24)); | |
427 | ddr->cs3_config = ( 1<<31 | |
428 | | (odt_rd_cfg << 20) | |
429 | | (odt_wr_cfg << 16) | |
430 | | (spd.nrow_addr - 12) << 8 | |
431 | | (spd.ncol_addr - 8) ); | |
432 | debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); | |
433 | debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config); | |
434 | } | |
435 | } | |
436 | #endif /* CONFIG_DDR_INTERLEAVE */ | |
debb7354 JL |
437 | |
438 | /* | |
439 | * Find the largest CAS by locating the highest 1 bit | |
440 | * in the spd.cas_lat field. Translate it to a DDR | |
441 | * controller field value: | |
442 | * | |
443 | * CAS Lat DDR I DDR II Ctrl | |
444 | * Clocks SPD Bit SPD Bit Value | |
445 | * ------- ------- ------- ----- | |
446 | * 1.0 0 0001 | |
447 | * 1.5 1 0010 | |
448 | * 2.0 2 2 0011 | |
449 | * 2.5 3 0100 | |
450 | * 3.0 4 3 0101 | |
451 | * 3.5 5 0110 | |
452 | * 4.0 4 0111 | |
453 | * 4.5 1000 | |
454 | * 5.0 5 1001 | |
455 | */ | |
456 | caslat = __ilog2(spd.cas_lat); | |
457 | if ((spd.mem_type == SPD_MEMTYPE_DDR) | |
458 | && (caslat > 5)) { | |
459 | printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); | |
460 | return 0; | |
461 | ||
462 | } else if (spd.mem_type == SPD_MEMTYPE_DDR2 | |
463 | && (caslat < 2 || caslat > 5)) { | |
464 | printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", | |
465 | spd.cas_lat); | |
466 | return 0; | |
467 | } | |
468 | debug("DDR: caslat SPD bit is %d\n", caslat); | |
469 | ||
470 | /* | |
471 | * Calculate the Maximum Data Rate based on the Minimum Cycle time. | |
472 | * The SPD clk_cycle field (tCKmin) is measured in tenths of | |
473 | * nanoseconds and represented as BCD. | |
474 | */ | |
475 | tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle); | |
476 | debug("DDR: tCKmin = %d ps\n", tCKmin_ps); | |
477 | ||
478 | /* | |
479 | * Double-data rate, scaled 1000 to picoseconds, and back down to MHz. | |
480 | */ | |
481 | max_data_rate = 2 * 1000 * 1000 / tCKmin_ps; | |
482 | debug("DDR: Module max data rate = %d Mhz\n", max_data_rate); | |
483 | ||
484 | ||
485 | /* | |
486 | * Adjust the CAS Latency to allow for bus speeds that | |
487 | * are slower than the DDR module. | |
488 | */ | |
489 | busfreq = get_bus_freq(0) / 1000000; /* MHz */ | |
f55df181 JT |
490 | tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3); |
491 | modfreq = 2 * 1000 * 1000 / tCycle_ps; | |
debb7354 | 492 | |
91a414c7 JT |
493 | if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) { |
494 | printf("DDR: platform frequency too low for correct DDR2 controller operation\n"); | |
debb7354 | 495 | return 0; |
91a414c7 JT |
496 | } else if (busfreq < 90) { |
497 | printf("DDR: platform frequency too low for correct DDR1 operation\n"); | |
debb7354 JL |
498 | return 0; |
499 | } | |
500 | ||
91a414c7 JT |
501 | if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) { |
502 | caslat -= 2; | |
503 | } else { | |
504 | tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2); | |
505 | modfreq = 2 * 1000 * 1000 / tCycle_ps; | |
506 | if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1)))) | |
507 | caslat -= 1; | |
508 | else if (busfreq > max_data_rate) { | |
509 | printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", | |
510 | busfreq, max_data_rate); | |
511 | return 0; | |
512 | } | |
513 | } | |
514 | ||
515 | /* | |
516 | * Empirically set ~MCAS-to-preamble override for DDR 2. | |
517 | * Your milage will vary. | |
518 | */ | |
519 | cpo = 0; | |
520 | if (spd.mem_type == SPD_MEMTYPE_DDR2) { | |
521 | if (busfreq <= 333) { | |
522 | cpo = 0x7; | |
523 | } else if (busfreq <= 400) { | |
524 | cpo = 0x9; | |
525 | } else { | |
526 | cpo = 0xa; | |
527 | } | |
528 | } | |
debb7354 JL |
529 | |
530 | /* | |
531 | * Convert caslat clocks to DDR controller value. | |
532 | * Force caslat_ctrl to be DDR Controller field-sized. | |
533 | */ | |
534 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
535 | caslat_ctrl = (caslat + 1) & 0x07; | |
536 | } else { | |
537 | caslat_ctrl = (2 * caslat - 1) & 0x0f; | |
538 | } | |
539 | ||
debb7354 JL |
540 | debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", |
541 | caslat, caslat_ctrl); | |
542 | ||
543 | /* | |
544 | * Timing Config 0. | |
545 | * Avoid writing for DDR I. The new PQ38 DDR controller | |
546 | * dreams up non-zero default values to be backwards compatible. | |
547 | */ | |
548 | if (spd.mem_type == SPD_MEMTYPE_DDR2) { | |
549 | unsigned char taxpd_clk = 8; /* By the book. */ | |
550 | unsigned char tmrd_clk = 2; /* By the book. */ | |
551 | unsigned char act_pd_exit = 2; /* Empirical? */ | |
552 | unsigned char pre_pd_exit = 6; /* Empirical? */ | |
553 | ||
9a655876 | 554 | ddr->timing_cfg_0 = (0 |
debb7354 JL |
555 | | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ |
556 | | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ | |
557 | | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ | |
558 | | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ | |
559 | ); | |
9a655876 | 560 | debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); |
debb7354 | 561 | |
debb7354 JL |
562 | } |
563 | ||
564 | ||
565 | /* | |
566 | * Some Timing Config 1 values now. | |
567 | * Sneak Extended Refresh Recovery in here too. | |
568 | */ | |
569 | ||
570 | /* | |
571 | * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, | |
572 | * use conservative value. | |
573 | * For DDR II, they are bytes 36 and 37, in quarter nanos. | |
574 | */ | |
575 | ||
576 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
577 | twr_clk = 3; /* Clocks */ | |
578 | twtr_clk = 1; /* Clocks */ | |
579 | } else { | |
580 | twr_clk = picos_to_clk(spd.twr * 250); | |
581 | twtr_clk = picos_to_clk(spd.twtr * 250); | |
582 | } | |
583 | ||
584 | /* | |
585 | * Calculate Trfc, in picos. | |
586 | * DDR I: Byte 42 straight up in ns. | |
587 | * DDR II: Byte 40 and 42 swizzled some, in ns. | |
588 | */ | |
589 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
590 | trfc = spd.trfc * 1000; /* up to ps */ | |
591 | } else { | |
592 | unsigned int byte40_table_ps[8] = { | |
593 | 0, | |
594 | 250, | |
595 | 330, | |
596 | 500, | |
597 | 660, | |
598 | 750, | |
599 | 0, | |
600 | 0 | |
601 | }; | |
602 | ||
603 | trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 | |
604 | + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; | |
605 | } | |
606 | trfc_clk = picos_to_clk(trfc); | |
607 | ||
608 | /* | |
609 | * Trcd, Byte 29, from quarter nanos to ps and clocks. | |
610 | */ | |
611 | trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; | |
612 | ||
613 | /* | |
614 | * Convert trfc_clk to DDR controller fields. DDR I should | |
615 | * fit in the REFREC field (16-19) of TIMING_CFG_1, but the | |
616 | * 8548 controller has an extended REFREC field of three bits. | |
617 | * The controller automatically adds 8 clocks to this value, | |
618 | * so preadjust it down 8 first before splitting it up. | |
619 | */ | |
620 | trfc_low = (trfc_clk - 8) & 0xf; | |
621 | trfc_high = ((trfc_clk - 8) >> 4) & 0x3; | |
622 | ||
623 | /* | |
624 | * Sneak in some Extended Refresh Recovery. | |
625 | */ | |
9a655876 JL |
626 | ddr->ext_refrec = (trfc_high << 16); |
627 | debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); | |
debb7354 | 628 | |
9a655876 | 629 | ddr->timing_cfg_1 = |
debb7354 JL |
630 | (0 |
631 | | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ | |
632 | | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ | |
633 | | (trcd_clk << 20) /* ACTTORW */ | |
634 | | (caslat_ctrl << 16) /* CASLAT */ | |
635 | | (trfc_low << 12) /* REFEC */ | |
636 | | ((twr_clk & 0x07) << 8) /* WRRREC */ | |
637 | | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */ | |
638 | | ((twtr_clk & 0x07) << 0) /* WRTORD */ | |
639 | ); | |
640 | ||
9a655876 | 641 | debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); |
debb7354 JL |
642 | |
643 | ||
644 | /* | |
645 | * Timing_Config_2 | |
646 | * Was: 0x00000800; | |
647 | */ | |
648 | ||
649 | /* | |
650 | * Additive Latency | |
651 | * For DDR I, 0. | |
652 | * For DDR II, with ODT enabled, use "a value" less than ACTTORW, | |
653 | * which comes from Trcd, and also note that: | |
654 | * add_lat + caslat must be >= 4 | |
655 | */ | |
656 | add_lat = 0; | |
657 | if (spd.mem_type == SPD_MEMTYPE_DDR2 | |
658 | && (odt_wr_cfg || odt_rd_cfg) | |
659 | && (caslat < 4)) { | |
660 | add_lat = 4 - caslat; | |
91a414c7 | 661 | if (add_lat >= trcd_clk) { |
debb7354 JL |
662 | add_lat = trcd_clk - 1; |
663 | } | |
664 | } | |
665 | ||
666 | /* | |
667 | * Write Data Delay | |
668 | * Historically 0x2 == 4/8 clock delay. | |
669 | * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. | |
670 | */ | |
671 | wr_data_delay = 3; | |
672 | ||
673 | /* | |
674 | * Write Latency | |
675 | * Read to Precharge | |
676 | * Minimum CKE Pulse Width. | |
677 | * Four Activate Window | |
678 | */ | |
679 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
680 | /* | |
681 | * This is a lie. It should really be 1, but if it is | |
682 | * set to 1, bits overlap into the old controller's | |
683 | * otherwise unused ACSM field. If we leave it 0, then | |
684 | * the HW will magically treat it as 1 for DDR 1. Oh Yea. | |
685 | */ | |
686 | wr_lat = 0; | |
687 | ||
688 | trtp_clk = 2; /* By the book. */ | |
689 | cke_min_clk = 1; /* By the book. */ | |
690 | four_act = 1; /* By the book. */ | |
691 | ||
692 | } else { | |
693 | wr_lat = caslat - 1; | |
694 | ||
695 | /* Convert SPD value from quarter nanos to picos. */ | |
696 | trtp_clk = picos_to_clk(spd.trtp * 250); | |
697 | ||
698 | cke_min_clk = 3; /* By the book. */ | |
699 | four_act = picos_to_clk(37500); /* By the book. 1k pages? */ | |
700 | } | |
701 | ||
9a655876 | 702 | ddr->timing_cfg_2 = (0 |
debb7354 | 703 | | ((add_lat & 0x7) << 28) /* ADD_LAT */ |
5c9efb36 | 704 | | ((cpo & 0x1f) << 23) /* CPO */ |
debb7354 JL |
705 | | ((wr_lat & 0x7) << 19) /* WR_LAT */ |
706 | | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ | |
707 | | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ | |
708 | | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ | |
709 | | ((four_act & 0x1f) << 0) /* FOUR_ACT */ | |
710 | ); | |
711 | ||
9a655876 | 712 | debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); |
debb7354 JL |
713 | |
714 | ||
715 | /* | |
716 | * Determine the Mode Register Set. | |
717 | * | |
718 | * This is nominally part specific, but it appears to be | |
719 | * consistent for all DDR I devices, and for all DDR II devices. | |
720 | * | |
721 | * caslat must be programmed | |
722 | * burst length is always 4 | |
723 | * burst type is sequential | |
724 | * | |
725 | * For DDR I: | |
726 | * operating mode is "normal" | |
727 | * | |
728 | * For DDR II: | |
729 | * other stuff | |
730 | */ | |
731 | ||
732 | mode_caslat = 0; | |
733 | ||
734 | /* | |
735 | * Table lookup from DDR I or II Device Operation Specs. | |
736 | */ | |
737 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
738 | if (1 <= caslat && caslat <= 4) { | |
739 | unsigned char mode_caslat_table[4] = { | |
740 | 0x5, /* 1.5 clocks */ | |
741 | 0x2, /* 2.0 clocks */ | |
742 | 0x6, /* 2.5 clocks */ | |
743 | 0x3 /* 3.0 clocks */ | |
744 | }; | |
745 | mode_caslat = mode_caslat_table[caslat - 1]; | |
746 | } else { | |
747 | puts("DDR I: Only CAS Latencies of 1.5, 2.0, " | |
748 | "2.5 and 3.0 clocks are supported.\n"); | |
749 | return 0; | |
750 | } | |
751 | ||
752 | } else { | |
753 | if (2 <= caslat && caslat <= 5) { | |
754 | mode_caslat = caslat; | |
755 | } else { | |
756 | puts("DDR II: Only CAS Latencies of 2.0, 3.0, " | |
757 | "4.0 and 5.0 clocks are supported.\n"); | |
758 | return 0; | |
759 | } | |
760 | } | |
761 | ||
762 | /* | |
9a655876 | 763 | * Encoded Burst Length of 4. |
debb7354 JL |
764 | */ |
765 | burst_len = 2; /* Fiat. */ | |
766 | ||
767 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
768 | twr_auto_clk = 0; /* Historical */ | |
769 | } else { | |
770 | /* | |
771 | * Determine tCK max in picos. Grab tWR and convert to picos. | |
772 | * Auto-precharge write recovery is: | |
773 | * WR = roundup(tWR_ns/tCKmax_ns). | |
774 | * | |
775 | * Ponder: Is twr_auto_clk different than twr_clk? | |
776 | */ | |
777 | tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax); | |
778 | twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; | |
779 | } | |
780 | ||
debb7354 JL |
781 | /* |
782 | * Mode Reg in bits 16 ~ 31, | |
783 | * Extended Mode Reg 1 in bits 0 ~ 15. | |
784 | */ | |
785 | mode_odt_enable = 0x0; /* Default disabled */ | |
786 | if (odt_wr_cfg || odt_rd_cfg) { | |
787 | /* | |
788 | * Bits 6 and 2 in Extended MRS(1) | |
789 | * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. | |
790 | * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. | |
791 | */ | |
792 | mode_odt_enable = 0x40; /* 150 Ohm */ | |
793 | } | |
794 | ||
9a655876 | 795 | ddr->sdram_mode_1 = |
debb7354 JL |
796 | (0 |
797 | | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | |
798 | | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ | |
799 | | (twr_auto_clk << 9) /* Write Recovery Autopre */ | |
800 | | (mode_caslat << 4) /* caslat */ | |
801 | | (burst_len << 0) /* Burst length */ | |
802 | ); | |
803 | ||
9a655876 | 804 | debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); |
debb7354 | 805 | |
debb7354 JL |
806 | /* |
807 | * Clear EMRS2 and EMRS3. | |
808 | */ | |
9a655876 JL |
809 | ddr->sdram_mode_2 = 0; |
810 | debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); | |
debb7354 | 811 | |
debb7354 | 812 | /* |
1fd5699a | 813 | * Determine Refresh Rate. |
debb7354 | 814 | */ |
1fd5699a | 815 | refresh_clk = determine_refresh_rate(spd.refresh & 0x7); |
debb7354 | 816 | |
1fd5699a JL |
817 | /* |
818 | * Set BSTOPRE to 0x100 for page mode | |
819 | * If auto-charge is used, set BSTOPRE = 0 | |
820 | */ | |
821 | ddr->sdram_interval = | |
822 | (0 | |
823 | | (refresh_clk & 0x3fff) << 16 | |
824 | | 0x100 | |
825 | ); | |
826 | debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); | |
debb7354 | 827 | |
debb7354 JL |
828 | |
829 | /* | |
830 | * Is this an ECC DDR chip? | |
831 | * But don't mess with it if the DDR controller will init mem. | |
832 | */ | |
833 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
834 | if (spd.config == 0x02) { | |
9a655876 JL |
835 | ddr->err_disable = 0x0000000d; |
836 | ddr->err_sbe = 0x00ff0000; | |
debb7354 | 837 | } |
9a655876 JL |
838 | debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); |
839 | debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); | |
debb7354 JL |
840 | #endif |
841 | ||
cd6d73d5 | 842 | asm volatile("sync;isync"); |
debb7354 JL |
843 | udelay(500); |
844 | ||
845 | /* | |
846 | * SDRAM Cfg 2 | |
847 | */ | |
848 | ||
849 | /* | |
850 | * When ODT is enabled, Chap 9 suggests asserting ODT to | |
851 | * internal IOs only during reads. | |
852 | */ | |
853 | odt_cfg = 0; | |
854 | if (odt_rd_cfg | odt_wr_cfg) { | |
855 | odt_cfg = 0x2; /* ODT to IOs during reads */ | |
856 | } | |
857 | ||
858 | /* | |
859 | * Try to use differential DQS with DDR II. | |
860 | */ | |
861 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
862 | dqs_cfg = 0; /* No Differential DQS for DDR I */ | |
863 | } else { | |
864 | dqs_cfg = 0x1; /* Differential DQS for DDR II */ | |
865 | } | |
866 | ||
867 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
868 | /* | |
869 | * Use the DDR controller to auto initialize memory. | |
870 | */ | |
871 | d_init = 1; | |
9a655876 JL |
872 | ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; |
873 | debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); | |
debb7354 JL |
874 | #else |
875 | /* | |
876 | * Memory will be initialized via DMA, or not at all. | |
877 | */ | |
5c9efb36 | 878 | d_init = 0; |
debb7354 JL |
879 | #endif |
880 | ||
9a655876 | 881 | ddr->sdram_cfg_2 = (0 |
debb7354 JL |
882 | | (dqs_cfg << 26) /* Differential DQS */ |
883 | | (odt_cfg << 21) /* ODT */ | |
884 | | (d_init << 4) /* D_INIT auto init DDR */ | |
885 | ); | |
886 | ||
9a655876 | 887 | debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); |
debb7354 JL |
888 | |
889 | ||
890 | #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL | |
1fd5699a JL |
891 | /* |
892 | * Setup the clock control. | |
893 | * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 | |
894 | * SDRAM_CLK_CNTL[5-7] = Clock Adjust | |
895 | * 0110 3/4 cycle late | |
896 | * 0111 7/8 cycle late | |
897 | */ | |
898 | if (spd.mem_type == SPD_MEMTYPE_DDR) | |
899 | clk_adjust = 0x6; | |
900 | else | |
901 | clk_adjust = 0x7; | |
debb7354 | 902 | |
1fd5699a | 903 | ddr->sdram_clk_cntl = (0 |
debb7354 JL |
904 | | 0x80000000 |
905 | | (clk_adjust << 23) | |
906 | ); | |
1fd5699a | 907 | debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); |
debb7354 JL |
908 | #endif |
909 | ||
910 | /* | |
9a655876 | 911 | * Figure out memory size in Megabytes. |
debb7354 | 912 | */ |
9a655876 JL |
913 | debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density); |
914 | memsize = n_ranks * rank_density / 0x100000; | |
915 | return memsize; | |
916 | } | |
917 | ||
918 | ||
919 | unsigned int enable_ddr(unsigned int ddr_num) | |
920 | { | |
921 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
922 | spd_eeprom_t spd1,spd2; | |
923 | volatile ccsr_ddr_t *ddr; | |
924 | unsigned sdram_cfg_1; | |
925 | unsigned char sdram_type, mem_type, config, mod_attr; | |
926 | unsigned char d_init; | |
927 | unsigned int no_dimm1=0, no_dimm2=0; | |
928 | ||
929 | /* Set up pointer to enable the current ddr controller */ | |
930 | if (ddr_num == 1) | |
931 | ddr = &immap->im_ddr1; | |
932 | else | |
933 | ddr = &immap->im_ddr2; | |
debb7354 JL |
934 | |
935 | /* | |
9a655876 JL |
936 | * Read both dimm slots and decide whether |
937 | * or not to enable this controller. | |
debb7354 | 938 | */ |
9a655876 JL |
939 | memset((void *)&spd1,0,sizeof(spd1)); |
940 | memset((void *)&spd2,0,sizeof(spd2)); | |
941 | ||
942 | if (ddr_num == 1) { | |
943 | CFG_READ_SPD(SPD_EEPROM_ADDRESS1, | |
944 | 0, 1, (uchar *) &spd1, sizeof(spd1)); | |
945 | CFG_READ_SPD(SPD_EEPROM_ADDRESS2, | |
946 | 0, 1, (uchar *) &spd2, sizeof(spd2)); | |
947 | } else { | |
948 | CFG_READ_SPD(SPD_EEPROM_ADDRESS3, | |
949 | 0, 1, (uchar *) &spd1, sizeof(spd1)); | |
950 | CFG_READ_SPD(SPD_EEPROM_ADDRESS4, | |
951 | 0, 1, (uchar *) &spd2, sizeof(spd2)); | |
debb7354 JL |
952 | } |
953 | ||
debb7354 | 954 | /* |
9a655876 | 955 | * Check for supported memory module types. |
debb7354 | 956 | */ |
9a655876 JL |
957 | if (spd1.mem_type != SPD_MEMTYPE_DDR |
958 | && spd1.mem_type != SPD_MEMTYPE_DDR2) { | |
959 | no_dimm1 = 1; | |
960 | } else { | |
961 | debug("\nFound memory of type 0x%02lx ",spd1.mem_type ); | |
962 | if (spd1.mem_type == SPD_MEMTYPE_DDR) | |
963 | debug("DDR I\n"); | |
964 | else | |
965 | debug("DDR II\n"); | |
966 | } | |
967 | ||
968 | if (spd2.mem_type != SPD_MEMTYPE_DDR && | |
969 | spd2.mem_type != SPD_MEMTYPE_DDR2) { | |
970 | no_dimm2 = 1; | |
971 | } else { | |
972 | debug("\nFound memory of type 0x%02lx ",spd2.mem_type ); | |
973 | if (spd2.mem_type == SPD_MEMTYPE_DDR) | |
974 | debug("DDR I\n"); | |
975 | else | |
976 | debug("DDR II\n"); | |
977 | } | |
978 | ||
979 | #ifdef CONFIG_DDR_INTERLEAVE | |
980 | if (no_dimm1) { | |
981 | printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n"); | |
982 | return 0; | |
debb7354 JL |
983 | } |
984 | #endif | |
985 | ||
986 | /* | |
9a655876 | 987 | * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn |
debb7354 | 988 | */ |
9a655876 JL |
989 | if (no_dimm1 && no_dimm2) { |
990 | printf("No memory modules found for DDR controller %d!!\n", ddr_num); | |
991 | return 0; | |
992 | } else { | |
993 | mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type; | |
debb7354 | 994 | |
9a655876 JL |
995 | /* |
996 | * Figure out the settings for the sdram_cfg register. | |
997 | * Build up the entire register in 'sdram_cfg' before | |
998 | * writing since the write into the register will | |
999 | * actually enable the memory controller; all settings | |
1000 | * must be done before enabling. | |
1001 | * | |
1002 | * sdram_cfg[0] = 1 (ddr sdram logic enable) | |
1003 | * sdram_cfg[1] = 1 (self-refresh-enable) | |
1004 | * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) | |
1005 | * 010 DDR 1 SDRAM | |
1006 | * 011 DDR 2 SDRAM | |
1007 | */ | |
1008 | sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; | |
1009 | sdram_cfg_1 = (0 | |
1010 | | (1 << 31) /* Enable */ | |
1011 | | (1 << 30) /* Self refresh */ | |
1012 | | (sdram_type << 24) /* SDRAM type */ | |
1013 | ); | |
1014 | ||
1015 | /* | |
1016 | * sdram_cfg[3] = RD_EN - registered DIMM enable | |
1017 | * A value of 0x26 indicates micron registered | |
1018 | * DIMMS (micron.com) | |
1019 | */ | |
1020 | mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr; | |
1021 | if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) { | |
1022 | sdram_cfg_1 |= 0x10000000; /* RD_EN */ | |
1023 | } | |
1024 | ||
1025 | #if defined(CONFIG_DDR_ECC) | |
1026 | ||
1027 | config = no_dimm2 ? spd1.config : spd2.config; | |
1028 | ||
1029 | /* | |
1030 | * If the user wanted ECC (enabled via sdram_cfg[2]) | |
1031 | */ | |
1032 | if (config == 0x02) { | |
70205e5a | 1033 | ddr->err_disable = 0x00000000; |
cd6d73d5 | 1034 | asm volatile("sync;isync;"); |
70205e5a HW |
1035 | ddr->err_sbe = 0x00ff0000; |
1036 | ddr->err_int_en = 0x0000000d; | |
9a655876 JL |
1037 | sdram_cfg_1 |= 0x20000000; /* ECC_EN */ |
1038 | } | |
1039 | #endif | |
1040 | ||
1041 | /* | |
70205e5a | 1042 | * Set 1T or 2T timing based on 1 or 2 modules |
9a655876 JL |
1043 | */ |
1044 | { | |
70205e5a | 1045 | if (!(no_dimm1 || no_dimm2)) { |
9a655876 | 1046 | /* |
70205e5a | 1047 | * 2T timing,because both DIMMS are present. |
9a655876 JL |
1048 | * Enable 2T timing by setting sdram_cfg[16]. |
1049 | */ | |
1050 | sdram_cfg_1 |= 0x8000; /* 2T_EN */ | |
9a655876 | 1051 | } |
debb7354 | 1052 | } |
debb7354 | 1053 | |
9a655876 JL |
1054 | /* |
1055 | * 200 painful micro-seconds must elapse between | |
1056 | * the DDR clock setup and the DDR config enable. | |
1057 | */ | |
1058 | udelay(200); | |
debb7354 | 1059 | |
9a655876 JL |
1060 | /* |
1061 | * Go! | |
1062 | */ | |
1063 | ddr->sdram_cfg_1 = sdram_cfg_1; | |
debb7354 | 1064 | |
9a655876 JL |
1065 | asm volatile("sync;isync"); |
1066 | udelay(500); | |
debb7354 | 1067 | |
9a655876 | 1068 | debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1); |
debb7354 JL |
1069 | |
1070 | ||
1071 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
9a655876 JL |
1072 | d_init = 1; |
1073 | debug("DDR: memory initializing\n"); | |
1074 | ||
1075 | /* | |
1076 | * Poll until memory is initialized. | |
1077 | * 512 Meg at 400 might hit this 200 times or so. | |
1078 | */ | |
1079 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { | |
1080 | udelay(1000); | |
1081 | } | |
1082 | debug("DDR: memory initialized\n\n"); | |
1083 | #endif | |
1084 | ||
1085 | debug("Enabled DDR Controller %d\n", ddr_num); | |
1086 | return 1; | |
1087 | } | |
1088 | } | |
1089 | ||
1090 | ||
1091 | long int | |
1092 | spd_sdram(void) | |
1093 | { | |
1094 | int memsize_ddr1_dimm1 = 0; | |
1095 | int memsize_ddr1_dimm2 = 0; | |
1096 | int memsize_ddr2_dimm1 = 0; | |
1097 | int memsize_ddr2_dimm2 = 0; | |
1098 | int memsize_total = 0; | |
1099 | int memsize_ddr1 = 0; | |
1100 | int memsize_ddr2 = 0; | |
1101 | unsigned int ddr1_enabled = 0; | |
1102 | unsigned int ddr2_enabled = 0; | |
1103 | unsigned int law_size_ddr1; | |
1104 | unsigned int law_size_ddr2; | |
1105 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
9a655876 JL |
1106 | volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; |
1107 | ||
1108 | #ifdef CONFIG_DDR_INTERLEAVE | |
1109 | unsigned int law_size_interleaved; | |
ea08ff6e JL |
1110 | volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; |
1111 | volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; | |
9a655876 JL |
1112 | |
1113 | memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, | |
1114 | 1, 1, | |
1115 | (unsigned int)memsize_total * 1024*1024); | |
1116 | memsize_total += memsize_ddr1_dimm1; | |
1117 | ||
1118 | memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, | |
1119 | 2, 1, | |
1120 | (unsigned int)memsize_total * 1024*1024); | |
1121 | memsize_total += memsize_ddr2_dimm1; | |
1122 | ||
1123 | if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) { | |
1124 | if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1) | |
1125 | memsize_total -= memsize_ddr1_dimm1; | |
1126 | else | |
1127 | memsize_total -= memsize_ddr2_dimm1; | |
1128 | debug("Total memory available for interleaving 0x%08lx\n", | |
1129 | memsize_total * 1024 * 1024); | |
1130 | debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n"); | |
1131 | ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; | |
1132 | ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; | |
1133 | debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); | |
1134 | debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds); | |
debb7354 | 1135 | } |
9a655876 JL |
1136 | |
1137 | ddr1_enabled = enable_ddr(1); | |
1138 | ddr2_enabled = enable_ddr(2); | |
1139 | ||
1140 | /* | |
1141 | * Both controllers need to be enabled for interleaving. | |
1142 | */ | |
1143 | if (ddr1_enabled && ddr2_enabled) { | |
1144 | law_size_interleaved = 19 + __ilog2(memsize_total); | |
1145 | ||
1146 | /* | |
1147 | * Set up LAWBAR for DDR 1 space. | |
1148 | */ | |
1149 | mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); | |
1150 | mcm->lawar1 = (LAWAR_EN | |
1151 | | LAWAR_TRGT_IF_DDR_INTERLEAVED | |
1152 | | (LAWAR_SIZE & law_size_interleaved)); | |
1153 | debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); | |
1154 | debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); | |
1155 | debug("Interleaved memory size is 0x%08lx\n", memsize_total); | |
1156 | ||
1157 | #ifdef CONFIG_DDR_INTERLEAVE | |
1158 | #if (CFG_PAGE_INTERLEAVING == 1) | |
1159 | printf("Page "); | |
1160 | #elif (CFG_BANK_INTERLEAVING == 1) | |
1161 | printf("Bank "); | |
1162 | #elif (CFG_SUPER_BANK_INTERLEAVING == 1) | |
1163 | printf("Super-bank "); | |
1164 | #else | |
1165 | printf("Cache-line "); | |
debb7354 | 1166 | #endif |
9a655876 JL |
1167 | #endif |
1168 | printf("Interleaved"); | |
1169 | return memsize_total * 1024 * 1024; | |
1170 | } else { | |
1171 | printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n"); | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | #else | |
1176 | /* | |
1177 | * Call spd_sdram() routine to init ddr1 - pass I2c address, | |
1178 | * controller number, dimm number, and starting address. | |
1179 | */ | |
1180 | memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, | |
1181 | 1, 1, | |
1182 | (unsigned int)memsize_total * 1024*1024); | |
1183 | memsize_total += memsize_ddr1_dimm1; | |
debb7354 | 1184 | |
9a655876 JL |
1185 | memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, |
1186 | 1, 2, | |
1187 | (unsigned int)memsize_total * 1024*1024); | |
1188 | memsize_total += memsize_ddr1_dimm2; | |
debb7354 JL |
1189 | |
1190 | /* | |
9a655876 | 1191 | * Enable the DDR controller - pass ddr controller number. |
debb7354 | 1192 | */ |
9a655876 | 1193 | ddr1_enabled = enable_ddr(1); |
debb7354 | 1194 | |
9a655876 JL |
1195 | /* Keep track of memory to be addressed by DDR1 */ |
1196 | memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2; | |
debb7354 | 1197 | |
9a655876 | 1198 | /* |
debb7354 JL |
1199 | * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. |
1200 | */ | |
9a655876 JL |
1201 | if (ddr1_enabled) { |
1202 | law_size_ddr1 = 19 + __ilog2(memsize_ddr1); | |
1203 | ||
1204 | /* | |
1205 | * Set up LAWBAR for DDR 1 space. | |
1206 | */ | |
1207 | mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); | |
1208 | mcm->lawar1 = (LAWAR_EN | |
1209 | | LAWAR_TRGT_IF_DDR1 | |
1210 | | (LAWAR_SIZE & law_size_ddr1)); | |
1211 | debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); | |
1212 | debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); | |
1213 | } | |
1214 | ||
1215 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) | |
1216 | memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, | |
1217 | 2, 1, | |
1218 | (unsigned int)memsize_total * 1024*1024); | |
1219 | memsize_total += memsize_ddr2_dimm1; | |
1220 | ||
1221 | memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4, | |
1222 | 2, 2, | |
1223 | (unsigned int)memsize_total * 1024*1024); | |
1224 | memsize_total += memsize_ddr2_dimm2; | |
1225 | ||
1226 | ddr2_enabled = enable_ddr(2); | |
1227 | ||
1228 | /* Keep track of memory to be addressed by DDR2 */ | |
1229 | memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2; | |
1230 | ||
1231 | if (ddr2_enabled) { | |
1232 | law_size_ddr2 = 19 + __ilog2(memsize_ddr2); | |
1233 | ||
1234 | /* | |
1235 | * Set up LAWBAR for DDR 2 space. | |
1236 | */ | |
1237 | if (ddr1_enabled) | |
1238 | mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) | |
1239 | & 0xfffff); | |
1240 | else | |
1241 | mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); | |
1242 | ||
1243 | mcm->lawar8 = (LAWAR_EN | |
1244 | | LAWAR_TRGT_IF_DDR2 | |
1245 | | (LAWAR_SIZE & law_size_ddr2)); | |
1246 | debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); | |
1247 | debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); | |
1248 | } | |
1249 | #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ | |
1250 | ||
1251 | debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", | |
1252 | memsize_ddr1, memsize_ddr2); | |
debb7354 JL |
1253 | |
1254 | /* | |
9a655876 | 1255 | * If neither DDR controller is enabled return 0. |
debb7354 | 1256 | */ |
9a655876 JL |
1257 | if (!ddr1_enabled && !ddr2_enabled) |
1258 | return 0; | |
1fd5699a JL |
1259 | |
1260 | printf("Non-interleaved"); | |
1261 | return memsize_total * 1024 * 1024; | |
5c9efb36 | 1262 | |
9a655876 | 1263 | #endif /* CONFIG_DDR_INTERLEAVE */ |
debb7354 JL |
1264 | } |
1265 | ||
9a655876 | 1266 | |
debb7354 JL |
1267 | #endif /* CONFIG_SPD_EEPROM */ |
1268 | ||
1269 | ||
1270 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
1271 | ||
1272 | /* | |
1273 | * Initialize all of memory for ECC, then enable errors. | |
1274 | */ | |
1275 | ||
1276 | void | |
1277 | ddr_enable_ecc(unsigned int dram_size) | |
1278 | { | |
1279 | uint *p = 0; | |
1280 | uint i = 0; | |
1281 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
1282 | volatile ccsr_ddr_t *ddr1= &immap->im_ddr1; | |
1283 | ||
1284 | dma_init(); | |
1285 | ||
1286 | for (*p = 0; p < (uint *)(8 * 1024); p++) { | |
1287 | if (((unsigned int)p & 0x1f) == 0) { | |
1288 | ppcDcbz((unsigned long) p); | |
1289 | } | |
1290 | *p = (unsigned int)CONFIG_MEM_INIT_VALUE; | |
1291 | if (((unsigned int)p & 0x1c) == 0x1c) { | |
1292 | ppcDcbf((unsigned long) p); | |
1293 | } | |
1294 | } | |
1295 | ||
1fd5699a JL |
1296 | dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */ |
1297 | dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */ | |
1298 | dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */ | |
1299 | dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */ | |
1300 | dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */ | |
1301 | dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */ | |
1302 | dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */ | |
1303 | dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ | |
1304 | dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ | |
1305 | dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ | |
debb7354 JL |
1306 | |
1307 | for (i = 1; i < dram_size / 0x800000; i++) { | |
1308 | dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); | |
1309 | } | |
1310 | ||
1311 | /* | |
1312 | * Enable errors for ECC. | |
1313 | */ | |
1314 | debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); | |
1315 | ddr1->err_disable = 0x00000000; | |
cd6d73d5 | 1316 | asm volatile("sync;isync"); |
debb7354 JL |
1317 | debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); |
1318 | } | |
1319 | ||
1320 | #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ |