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debb7354 JL |
1 | /* |
2 | * Copyright 2004 Freescale Semiconductor. | |
3 | * (C) Copyright 2003 Motorola Inc. | |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <asm/processor.h> | |
27 | #include <i2c.h> | |
28 | #include <spd.h> | |
29 | #include <asm/mmu.h> | |
4933b91f | 30 | #include <asm/fsl_law.h> |
debb7354 JL |
31 | |
32 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
33 | extern void dma_init(void); | |
34 | extern uint dma_check(void); | |
35 | extern int dma_xfer(void *dest, uint count, void *src); | |
36 | #endif | |
37 | ||
38 | #ifdef CONFIG_SPD_EEPROM | |
39 | ||
40 | #ifndef CFG_READ_SPD | |
41 | #define CFG_READ_SPD i2c_read | |
42 | #endif | |
43 | ||
9a655876 JL |
44 | /* |
45 | * Only one of the following three should be 1; others should be 0 | |
46 | * By default the cache line interleaving is selected if | |
91a414c7 | 47 | * the CONFIG_DDR_INTERLEAVE flag is defined |
9a655876 JL |
48 | */ |
49 | #define CFG_PAGE_INTERLEAVING 0 | |
50 | #define CFG_BANK_INTERLEAVING 0 | |
51 | #define CFG_SUPER_BANK_INTERLEAVING 0 | |
52 | ||
debb7354 | 53 | /* |
c1ab8266 | 54 | * Convert picoseconds into DRAM clock cycles (rounding up if needed). |
debb7354 JL |
55 | */ |
56 | ||
c1ab8266 JY |
57 | static unsigned int |
58 | picos_to_clk(unsigned int picos) | |
debb7354 | 59 | { |
c1ab8266 JY |
60 | /* use unsigned long long to avoid rounding errors */ |
61 | const unsigned long long ULL_2e12 = 2000000000000ULL; | |
62 | unsigned long long clks; | |
63 | unsigned long long clks_temp; | |
debb7354 | 64 | |
c1ab8266 JY |
65 | if (! picos) |
66 | return 0; | |
67 | ||
68 | clks = get_bus_freq(0) * (unsigned long long) picos; | |
69 | clks_temp = clks; | |
70 | clks = clks / ULL_2e12; | |
71 | if (clks_temp % ULL_2e12) { | |
debb7354 JL |
72 | clks++; |
73 | } | |
74 | ||
c1ab8266 JY |
75 | if (clks > 0xFFFFFFFFULL) { |
76 | clks = 0xFFFFFFFFULL; | |
77 | } | |
78 | ||
79 | return (unsigned int) clks; | |
debb7354 JL |
80 | } |
81 | ||
82 | ||
83 | /* | |
84 | * Calculate the Density of each Physical Rank. | |
85 | * Returned size is in bytes. | |
86 | * | |
87 | * Study these table from Byte 31 of JEDEC SPD Spec. | |
88 | * | |
89 | * DDR I DDR II | |
90 | * Bit Size Size | |
91 | * --- ----- ------ | |
92 | * 7 high 512MB 512MB | |
93 | * 6 256MB 256MB | |
94 | * 5 128MB 128MB | |
95 | * 4 64MB 16GB | |
96 | * 3 32MB 8GB | |
97 | * 2 16MB 4GB | |
98 | * 1 2GB 2GB | |
99 | * 0 low 1GB 1GB | |
100 | * | |
101 | * Reorder Table to be linear by stripping the bottom | |
102 | * 2 or 5 bits off and shifting them up to the top. | |
103 | */ | |
104 | ||
105 | unsigned int | |
106 | compute_banksize(unsigned int mem_type, unsigned char row_dens) | |
107 | { | |
108 | unsigned int bsize; | |
109 | ||
110 | if (mem_type == SPD_MEMTYPE_DDR) { | |
111 | /* Bottom 2 bits up to the top. */ | |
112 | bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; | |
113 | debug("DDR: DDR I rank density = 0x%08x\n", bsize); | |
114 | } else { | |
115 | /* Bottom 5 bits up to the top. */ | |
116 | bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27; | |
117 | debug("DDR: DDR II rank density = 0x%08x\n", bsize); | |
118 | } | |
119 | return bsize; | |
120 | } | |
121 | ||
122 | ||
123 | /* | |
124 | * Convert a two-nibble BCD value into a cycle time. | |
125 | * While the spec calls for nano-seconds, picos are returned. | |
126 | * | |
127 | * This implements the tables for bytes 9, 23 and 25 for both | |
128 | * DDR I and II. No allowance for distinguishing the invalid | |
129 | * fields absent for DDR I yet present in DDR II is made. | |
130 | * (That is, cycle times of .25, .33, .66 and .75 ns are | |
131 | * allowed for both DDR II and I.) | |
132 | */ | |
133 | ||
134 | unsigned int | |
135 | convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) | |
136 | { | |
137 | /* | |
138 | * Table look up the lower nibble, allow DDR I & II. | |
139 | */ | |
140 | unsigned int tenths_ps[16] = { | |
141 | 0, | |
142 | 100, | |
143 | 200, | |
144 | 300, | |
145 | 400, | |
146 | 500, | |
147 | 600, | |
148 | 700, | |
149 | 800, | |
150 | 900, | |
151 | 250, | |
91a414c7 JT |
152 | 330, |
153 | 660, | |
debb7354 JL |
154 | 750, |
155 | 0, /* undefined */ | |
156 | 0 /* undefined */ | |
157 | }; | |
158 | ||
159 | unsigned int whole_ns = (spd_val & 0xF0) >> 4; | |
160 | unsigned int tenth_ns = spd_val & 0x0F; | |
161 | unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; | |
162 | ||
163 | return ps; | |
164 | } | |
165 | ||
166 | ||
1fd5699a JL |
167 | /* |
168 | * Determine Refresh Rate. Ignore self refresh bit on DDR I. | |
169 | * Table from SPD Spec, Byte 12, converted to picoseconds and | |
170 | * filled in with "default" normal values. | |
171 | */ | |
172 | unsigned int determine_refresh_rate(unsigned int spd_refresh) | |
173 | { | |
174 | unsigned int refresh_time_ns[8] = { | |
175 | 15625000, /* 0 Normal 1.00x */ | |
176 | 3900000, /* 1 Reduced .25x */ | |
177 | 7800000, /* 2 Extended .50x */ | |
178 | 31300000, /* 3 Extended 2.00x */ | |
179 | 62500000, /* 4 Extended 4.00x */ | |
180 | 125000000, /* 5 Extended 8.00x */ | |
181 | 15625000, /* 6 Normal 1.00x filler */ | |
182 | 15625000, /* 7 Normal 1.00x filler */ | |
183 | }; | |
184 | ||
185 | return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]); | |
186 | } | |
187 | ||
188 | ||
debb7354 | 189 | long int |
9a655876 JL |
190 | spd_init(unsigned char i2c_address, unsigned int ddr_num, |
191 | unsigned int dimm_num, unsigned int start_addr) | |
debb7354 JL |
192 | { |
193 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
9a655876 | 194 | volatile ccsr_ddr_t *ddr; |
debb7354 JL |
195 | volatile ccsr_gur_t *gur = &immap->im_gur; |
196 | spd_eeprom_t spd; | |
197 | unsigned int n_ranks; | |
198 | unsigned int rank_density; | |
b830b7f1 | 199 | unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; |
debb7354 | 200 | unsigned int odt_cfg, mode_odt_enable; |
1fd5699a JL |
201 | unsigned int refresh_clk; |
202 | #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL | |
203 | unsigned char clk_adjust; | |
204 | #endif | |
debb7354 JL |
205 | unsigned int dqs_cfg; |
206 | unsigned char twr_clk, twtr_clk, twr_auto_clk; | |
207 | unsigned int tCKmin_ps, tCKmax_ps; | |
91a414c7 | 208 | unsigned int max_data_rate; |
debb7354 | 209 | unsigned int busfreq; |
debb7354 JL |
210 | unsigned int memsize; |
211 | unsigned char caslat, caslat_ctrl; | |
212 | unsigned int trfc, trfc_clk, trfc_low, trfc_high; | |
213 | unsigned int trcd_clk; | |
214 | unsigned int trtp_clk; | |
215 | unsigned char cke_min_clk; | |
216 | unsigned char add_lat; | |
217 | unsigned char wr_lat; | |
218 | unsigned char wr_data_delay; | |
219 | unsigned char four_act; | |
220 | unsigned char cpo; | |
221 | unsigned char burst_len; | |
222 | unsigned int mode_caslat; | |
debb7354 | 223 | unsigned char d_init; |
91a414c7 | 224 | unsigned int tCycle_ps, modfreq; |
debb7354 | 225 | |
9a655876 JL |
226 | if (ddr_num == 1) |
227 | ddr = &immap->im_ddr1; | |
228 | else | |
229 | ddr = &immap->im_ddr2; | |
5c9efb36 | 230 | |
debb7354 JL |
231 | /* |
232 | * Read SPD information. | |
233 | */ | |
9a655876 JL |
234 | debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address); |
235 | memset((void *)&spd, 0, sizeof(spd)); | |
236 | CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd)); | |
debb7354 JL |
237 | |
238 | /* | |
239 | * Check for supported memory module types. | |
240 | */ | |
241 | if (spd.mem_type != SPD_MEMTYPE_DDR && | |
242 | spd.mem_type != SPD_MEMTYPE_DDR2) { | |
9a655876 JL |
243 | debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n" |
244 | " Fundamental memory type is 0x%0x\n", | |
245 | dimm_num, | |
246 | ddr_num, | |
247 | spd.mem_type); | |
debb7354 JL |
248 | return 0; |
249 | } | |
250 | ||
9a655876 JL |
251 | debug("\nFound memory of type 0x%02lx ", spd.mem_type); |
252 | if (spd.mem_type == SPD_MEMTYPE_DDR) | |
253 | debug("DDR I\n"); | |
254 | else | |
255 | debug("DDR II\n"); | |
256 | ||
debb7354 JL |
257 | /* |
258 | * These test gloss over DDR I and II differences in interpretation | |
259 | * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks | |
260 | * are not supported on DDR I; and not encoded on DDR II. | |
261 | * | |
262 | * Also note that the 8548 controller can support: | |
263 | * 12 <= nrow <= 16 | |
264 | * and | |
265 | * 8 <= ncol <= 11 (still, for DDR) | |
266 | * 6 <= ncol <= 9 (for FCRAM) | |
267 | */ | |
268 | if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { | |
269 | printf("DDR: Unsupported number of Row Addr lines: %d.\n", | |
270 | spd.nrow_addr); | |
271 | return 0; | |
272 | } | |
273 | if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { | |
274 | printf("DDR: Unsupported number of Column Addr lines: %d.\n", | |
275 | spd.ncol_addr); | |
276 | return 0; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Determine the number of physical banks controlled by | |
281 | * different Chip Select signals. This is not quite the | |
282 | * same as the number of DIMM modules on the board. Feh. | |
283 | */ | |
284 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
285 | n_ranks = spd.nrows; | |
286 | } else { | |
287 | n_ranks = (spd.nrows & 0x7) + 1; | |
288 | } | |
289 | ||
290 | debug("DDR: number of ranks = %d\n", n_ranks); | |
291 | ||
292 | if (n_ranks > 2) { | |
293 | printf("DDR: Only 2 chip selects are supported: %d\n", | |
294 | n_ranks); | |
295 | return 0; | |
296 | } | |
297 | ||
298 | /* | |
2ccceacc | 299 | * Adjust DDR II IO voltage biasing. Rev1 only |
debb7354 | 300 | */ |
2ccceacc | 301 | if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { |
debb7354 JL |
302 | gur->ddrioovcr = (0 |
303 | | 0x80000000 /* Enable */ | |
304 | | 0x10000000 /* VSEL to 1.8V */ | |
305 | ); | |
306 | } | |
307 | ||
308 | /* | |
309 | * Determine the size of each Rank in bytes. | |
310 | */ | |
311 | rank_density = compute_banksize(spd.mem_type, spd.row_dens); | |
312 | ||
9a655876 | 313 | debug("Start address for this controller is 0x%08lx\n", start_addr); |
debb7354 JL |
314 | |
315 | /* | |
316 | * ODT configuration recommendation from DDR Controller Chapter. | |
317 | */ | |
318 | odt_rd_cfg = 0; /* Never assert ODT */ | |
319 | odt_wr_cfg = 0; /* Never assert ODT */ | |
320 | if (spd.mem_type == SPD_MEMTYPE_DDR2) { | |
321 | odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ | |
322 | } | |
323 | ||
b830b7f1 BB |
324 | ba_bits = 0; |
325 | if (spd.nbanks == 0x8) | |
326 | ba_bits = 1; | |
327 | ||
9a655876 | 328 | #ifdef CONFIG_DDR_INTERLEAVE |
91a414c7 | 329 | |
9a655876 JL |
330 | if (dimm_num != 1) { |
331 | printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num); | |
332 | return 0; | |
333 | } else { | |
334 | /* | |
335 | * Since interleaved memory only uses CS0, the | |
336 | * memory sticks have to be identical in size and quantity | |
337 | * of ranks. That essentially gives double the size on | |
338 | * one rank, i.e on CS0 for both controllers put together. | |
339 | * Confirm this??? | |
340 | */ | |
341 | rank_density *= 2; | |
debb7354 | 342 | |
debb7354 | 343 | /* |
9a655876 JL |
344 | * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg |
345 | */ | |
346 | start_addr = 0; | |
347 | ddr->cs0_bnds = (start_addr >> 8) | |
348 | | (((start_addr + rank_density - 1) >> 24)); | |
349 | /* | |
350 | * Default interleaving mode to cache-line interleaving. | |
debb7354 | 351 | */ |
9a655876 JL |
352 | ddr->cs0_config = ( 1 << 31 |
353 | #if (CFG_PAGE_INTERLEAVING == 1) | |
354 | | (PAGE_INTERLEAVING) | |
355 | #elif (CFG_BANK_INTERLEAVING == 1) | |
356 | | (BANK_INTERLEAVING) | |
357 | #elif (CFG_SUPER_BANK_INTERLEAVING == 1) | |
358 | | (SUPER_BANK_INTERLEAVING) | |
359 | #else | |
360 | | (CACHE_LINE_INTERLEAVING) | |
361 | #endif | |
debb7354 JL |
362 | | (odt_rd_cfg << 20) |
363 | | (odt_wr_cfg << 16) | |
b830b7f1 | 364 | | (ba_bits << 14) |
debb7354 JL |
365 | | (spd.nrow_addr - 12) << 8 |
366 | | (spd.ncol_addr - 8) ); | |
9a655876 JL |
367 | |
368 | debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); | |
369 | debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); | |
370 | ||
371 | /* | |
372 | * Adjustment for dual rank memory to get correct memory | |
373 | * size (return value of this function). | |
374 | */ | |
375 | if (n_ranks == 2) { | |
376 | n_ranks = 1; | |
377 | rank_density /= 2; | |
378 | } else { | |
379 | rank_density /= 2; | |
380 | } | |
debb7354 | 381 | } |
9a655876 JL |
382 | #else /* CONFIG_DDR_INTERLEAVE */ |
383 | ||
384 | if (dimm_num == 1) { | |
385 | /* | |
386 | * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg | |
387 | */ | |
388 | ddr->cs0_bnds = (start_addr >> 8) | |
389 | | (((start_addr + rank_density - 1) >> 24)); | |
390 | ||
391 | ddr->cs0_config = ( 1 << 31 | |
392 | | (odt_rd_cfg << 20) | |
393 | | (odt_wr_cfg << 16) | |
b830b7f1 | 394 | | (ba_bits << 14) |
9a655876 JL |
395 | | (spd.nrow_addr - 12) << 8 |
396 | | (spd.ncol_addr - 8) ); | |
397 | ||
398 | debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds); | |
399 | debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config); | |
400 | ||
401 | if (n_ranks == 2) { | |
402 | /* | |
403 | * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, | |
404 | * second 256 Meg | |
405 | */ | |
406 | ddr->cs1_bnds = (((start_addr + rank_density) >> 8) | |
407 | | (( start_addr + 2*rank_density - 1) | |
408 | >> 24)); | |
409 | ddr->cs1_config = ( 1<<31 | |
410 | | (odt_rd_cfg << 20) | |
411 | | (odt_wr_cfg << 16) | |
b830b7f1 | 412 | | (ba_bits << 14) |
9a655876 JL |
413 | | (spd.nrow_addr - 12) << 8 |
414 | | (spd.ncol_addr - 8) ); | |
415 | debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); | |
416 | debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config); | |
417 | } | |
418 | ||
419 | } else { | |
420 | /* | |
421 | * This is the 2nd DIMM slot for this controller | |
422 | */ | |
423 | /* | |
424 | * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg | |
425 | */ | |
426 | ddr->cs2_bnds = (start_addr >> 8) | |
427 | | (((start_addr + rank_density - 1) >> 24)); | |
428 | ||
429 | ddr->cs2_config = ( 1 << 31 | |
430 | | (odt_rd_cfg << 20) | |
431 | | (odt_wr_cfg << 16) | |
b830b7f1 | 432 | | (ba_bits << 14) |
9a655876 JL |
433 | | (spd.nrow_addr - 12) << 8 |
434 | | (spd.ncol_addr - 8) ); | |
435 | ||
436 | debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds); | |
437 | debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config); | |
438 | ||
439 | if (n_ranks == 2) { | |
440 | /* | |
441 | * Eg: Bounds: 0x1000_0000 to 0x1f00_0000, | |
442 | * second 256 Meg | |
443 | */ | |
444 | ddr->cs3_bnds = (((start_addr + rank_density) >> 8) | |
445 | | (( start_addr + 2*rank_density - 1) | |
446 | >> 24)); | |
447 | ddr->cs3_config = ( 1<<31 | |
448 | | (odt_rd_cfg << 20) | |
449 | | (odt_wr_cfg << 16) | |
b830b7f1 | 450 | | (ba_bits << 14) |
9a655876 JL |
451 | | (spd.nrow_addr - 12) << 8 |
452 | | (spd.ncol_addr - 8) ); | |
453 | debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); | |
454 | debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config); | |
455 | } | |
456 | } | |
457 | #endif /* CONFIG_DDR_INTERLEAVE */ | |
debb7354 JL |
458 | |
459 | /* | |
460 | * Find the largest CAS by locating the highest 1 bit | |
461 | * in the spd.cas_lat field. Translate it to a DDR | |
462 | * controller field value: | |
463 | * | |
464 | * CAS Lat DDR I DDR II Ctrl | |
465 | * Clocks SPD Bit SPD Bit Value | |
466 | * ------- ------- ------- ----- | |
467 | * 1.0 0 0001 | |
468 | * 1.5 1 0010 | |
469 | * 2.0 2 2 0011 | |
470 | * 2.5 3 0100 | |
471 | * 3.0 4 3 0101 | |
472 | * 3.5 5 0110 | |
473 | * 4.0 4 0111 | |
474 | * 4.5 1000 | |
475 | * 5.0 5 1001 | |
476 | */ | |
477 | caslat = __ilog2(spd.cas_lat); | |
478 | if ((spd.mem_type == SPD_MEMTYPE_DDR) | |
479 | && (caslat > 5)) { | |
480 | printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); | |
481 | return 0; | |
482 | ||
483 | } else if (spd.mem_type == SPD_MEMTYPE_DDR2 | |
484 | && (caslat < 2 || caslat > 5)) { | |
485 | printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", | |
486 | spd.cas_lat); | |
487 | return 0; | |
488 | } | |
489 | debug("DDR: caslat SPD bit is %d\n", caslat); | |
490 | ||
491 | /* | |
492 | * Calculate the Maximum Data Rate based on the Minimum Cycle time. | |
493 | * The SPD clk_cycle field (tCKmin) is measured in tenths of | |
494 | * nanoseconds and represented as BCD. | |
495 | */ | |
496 | tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle); | |
497 | debug("DDR: tCKmin = %d ps\n", tCKmin_ps); | |
498 | ||
499 | /* | |
500 | * Double-data rate, scaled 1000 to picoseconds, and back down to MHz. | |
501 | */ | |
502 | max_data_rate = 2 * 1000 * 1000 / tCKmin_ps; | |
503 | debug("DDR: Module max data rate = %d Mhz\n", max_data_rate); | |
504 | ||
505 | ||
506 | /* | |
507 | * Adjust the CAS Latency to allow for bus speeds that | |
508 | * are slower than the DDR module. | |
509 | */ | |
510 | busfreq = get_bus_freq(0) / 1000000; /* MHz */ | |
f55df181 JT |
511 | tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3); |
512 | modfreq = 2 * 1000 * 1000 / tCycle_ps; | |
debb7354 | 513 | |
91a414c7 JT |
514 | if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) { |
515 | printf("DDR: platform frequency too low for correct DDR2 controller operation\n"); | |
debb7354 | 516 | return 0; |
91a414c7 JT |
517 | } else if (busfreq < 90) { |
518 | printf("DDR: platform frequency too low for correct DDR1 operation\n"); | |
debb7354 JL |
519 | return 0; |
520 | } | |
521 | ||
91a414c7 JT |
522 | if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) { |
523 | caslat -= 2; | |
524 | } else { | |
525 | tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2); | |
526 | modfreq = 2 * 1000 * 1000 / tCycle_ps; | |
527 | if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1)))) | |
528 | caslat -= 1; | |
529 | else if (busfreq > max_data_rate) { | |
530 | printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n", | |
53677ef1 | 531 | busfreq, max_data_rate); |
91a414c7 JT |
532 | return 0; |
533 | } | |
534 | } | |
535 | ||
536 | /* | |
537 | * Empirically set ~MCAS-to-preamble override for DDR 2. | |
538 | * Your milage will vary. | |
539 | */ | |
540 | cpo = 0; | |
541 | if (spd.mem_type == SPD_MEMTYPE_DDR2) { | |
542 | if (busfreq <= 333) { | |
543 | cpo = 0x7; | |
544 | } else if (busfreq <= 400) { | |
545 | cpo = 0x9; | |
546 | } else { | |
547 | cpo = 0xa; | |
548 | } | |
549 | } | |
debb7354 JL |
550 | |
551 | /* | |
552 | * Convert caslat clocks to DDR controller value. | |
553 | * Force caslat_ctrl to be DDR Controller field-sized. | |
554 | */ | |
555 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
556 | caslat_ctrl = (caslat + 1) & 0x07; | |
557 | } else { | |
558 | caslat_ctrl = (2 * caslat - 1) & 0x0f; | |
559 | } | |
560 | ||
debb7354 JL |
561 | debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", |
562 | caslat, caslat_ctrl); | |
563 | ||
564 | /* | |
565 | * Timing Config 0. | |
566 | * Avoid writing for DDR I. The new PQ38 DDR controller | |
567 | * dreams up non-zero default values to be backwards compatible. | |
568 | */ | |
569 | if (spd.mem_type == SPD_MEMTYPE_DDR2) { | |
570 | unsigned char taxpd_clk = 8; /* By the book. */ | |
571 | unsigned char tmrd_clk = 2; /* By the book. */ | |
572 | unsigned char act_pd_exit = 2; /* Empirical? */ | |
573 | unsigned char pre_pd_exit = 6; /* Empirical? */ | |
574 | ||
9a655876 | 575 | ddr->timing_cfg_0 = (0 |
debb7354 JL |
576 | | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ |
577 | | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ | |
578 | | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ | |
579 | | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ | |
580 | ); | |
9a655876 | 581 | debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); |
debb7354 | 582 | |
debb7354 JL |
583 | } |
584 | ||
585 | ||
586 | /* | |
587 | * Some Timing Config 1 values now. | |
588 | * Sneak Extended Refresh Recovery in here too. | |
589 | */ | |
590 | ||
591 | /* | |
592 | * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, | |
593 | * use conservative value. | |
594 | * For DDR II, they are bytes 36 and 37, in quarter nanos. | |
595 | */ | |
596 | ||
597 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
598 | twr_clk = 3; /* Clocks */ | |
599 | twtr_clk = 1; /* Clocks */ | |
600 | } else { | |
601 | twr_clk = picos_to_clk(spd.twr * 250); | |
602 | twtr_clk = picos_to_clk(spd.twtr * 250); | |
603 | } | |
604 | ||
605 | /* | |
606 | * Calculate Trfc, in picos. | |
607 | * DDR I: Byte 42 straight up in ns. | |
608 | * DDR II: Byte 40 and 42 swizzled some, in ns. | |
609 | */ | |
610 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
611 | trfc = spd.trfc * 1000; /* up to ps */ | |
612 | } else { | |
613 | unsigned int byte40_table_ps[8] = { | |
614 | 0, | |
615 | 250, | |
616 | 330, | |
617 | 500, | |
618 | 660, | |
619 | 750, | |
620 | 0, | |
621 | 0 | |
622 | }; | |
623 | ||
624 | trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 | |
625 | + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; | |
626 | } | |
627 | trfc_clk = picos_to_clk(trfc); | |
628 | ||
629 | /* | |
630 | * Trcd, Byte 29, from quarter nanos to ps and clocks. | |
631 | */ | |
632 | trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; | |
633 | ||
634 | /* | |
635 | * Convert trfc_clk to DDR controller fields. DDR I should | |
636 | * fit in the REFREC field (16-19) of TIMING_CFG_1, but the | |
637 | * 8548 controller has an extended REFREC field of three bits. | |
638 | * The controller automatically adds 8 clocks to this value, | |
639 | * so preadjust it down 8 first before splitting it up. | |
640 | */ | |
641 | trfc_low = (trfc_clk - 8) & 0xf; | |
642 | trfc_high = ((trfc_clk - 8) >> 4) & 0x3; | |
643 | ||
644 | /* | |
645 | * Sneak in some Extended Refresh Recovery. | |
646 | */ | |
45239cf4 KG |
647 | ddr->timing_cfg_3 = (trfc_high << 16); |
648 | debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); | |
debb7354 | 649 | |
9a655876 | 650 | ddr->timing_cfg_1 = |
debb7354 JL |
651 | (0 |
652 | | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */ | |
653 | | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */ | |
654 | | (trcd_clk << 20) /* ACTTORW */ | |
655 | | (caslat_ctrl << 16) /* CASLAT */ | |
656 | | (trfc_low << 12) /* REFEC */ | |
657 | | ((twr_clk & 0x07) << 8) /* WRRREC */ | |
658 | | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */ | |
659 | | ((twtr_clk & 0x07) << 0) /* WRTORD */ | |
660 | ); | |
661 | ||
9a655876 | 662 | debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); |
debb7354 JL |
663 | |
664 | ||
665 | /* | |
666 | * Timing_Config_2 | |
667 | * Was: 0x00000800; | |
668 | */ | |
669 | ||
670 | /* | |
671 | * Additive Latency | |
672 | * For DDR I, 0. | |
673 | * For DDR II, with ODT enabled, use "a value" less than ACTTORW, | |
674 | * which comes from Trcd, and also note that: | |
675 | * add_lat + caslat must be >= 4 | |
676 | */ | |
677 | add_lat = 0; | |
678 | if (spd.mem_type == SPD_MEMTYPE_DDR2 | |
679 | && (odt_wr_cfg || odt_rd_cfg) | |
680 | && (caslat < 4)) { | |
681 | add_lat = 4 - caslat; | |
91a414c7 | 682 | if (add_lat >= trcd_clk) { |
debb7354 JL |
683 | add_lat = trcd_clk - 1; |
684 | } | |
685 | } | |
686 | ||
687 | /* | |
688 | * Write Data Delay | |
689 | * Historically 0x2 == 4/8 clock delay. | |
690 | * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. | |
691 | */ | |
692 | wr_data_delay = 3; | |
693 | ||
694 | /* | |
695 | * Write Latency | |
696 | * Read to Precharge | |
697 | * Minimum CKE Pulse Width. | |
698 | * Four Activate Window | |
699 | */ | |
700 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
701 | /* | |
702 | * This is a lie. It should really be 1, but if it is | |
703 | * set to 1, bits overlap into the old controller's | |
704 | * otherwise unused ACSM field. If we leave it 0, then | |
705 | * the HW will magically treat it as 1 for DDR 1. Oh Yea. | |
706 | */ | |
707 | wr_lat = 0; | |
708 | ||
709 | trtp_clk = 2; /* By the book. */ | |
710 | cke_min_clk = 1; /* By the book. */ | |
711 | four_act = 1; /* By the book. */ | |
712 | ||
713 | } else { | |
714 | wr_lat = caslat - 1; | |
715 | ||
716 | /* Convert SPD value from quarter nanos to picos. */ | |
717 | trtp_clk = picos_to_clk(spd.trtp * 250); | |
718 | ||
719 | cke_min_clk = 3; /* By the book. */ | |
720 | four_act = picos_to_clk(37500); /* By the book. 1k pages? */ | |
721 | } | |
722 | ||
9a655876 | 723 | ddr->timing_cfg_2 = (0 |
debb7354 | 724 | | ((add_lat & 0x7) << 28) /* ADD_LAT */ |
5c9efb36 | 725 | | ((cpo & 0x1f) << 23) /* CPO */ |
debb7354 JL |
726 | | ((wr_lat & 0x7) << 19) /* WR_LAT */ |
727 | | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ | |
728 | | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ | |
729 | | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ | |
730 | | ((four_act & 0x1f) << 0) /* FOUR_ACT */ | |
731 | ); | |
732 | ||
9a655876 | 733 | debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); |
debb7354 JL |
734 | |
735 | ||
736 | /* | |
737 | * Determine the Mode Register Set. | |
738 | * | |
739 | * This is nominally part specific, but it appears to be | |
740 | * consistent for all DDR I devices, and for all DDR II devices. | |
741 | * | |
742 | * caslat must be programmed | |
743 | * burst length is always 4 | |
744 | * burst type is sequential | |
745 | * | |
746 | * For DDR I: | |
747 | * operating mode is "normal" | |
748 | * | |
749 | * For DDR II: | |
750 | * other stuff | |
751 | */ | |
752 | ||
753 | mode_caslat = 0; | |
754 | ||
755 | /* | |
756 | * Table lookup from DDR I or II Device Operation Specs. | |
757 | */ | |
758 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
759 | if (1 <= caslat && caslat <= 4) { | |
760 | unsigned char mode_caslat_table[4] = { | |
761 | 0x5, /* 1.5 clocks */ | |
762 | 0x2, /* 2.0 clocks */ | |
763 | 0x6, /* 2.5 clocks */ | |
764 | 0x3 /* 3.0 clocks */ | |
765 | }; | |
766 | mode_caslat = mode_caslat_table[caslat - 1]; | |
767 | } else { | |
768 | puts("DDR I: Only CAS Latencies of 1.5, 2.0, " | |
769 | "2.5 and 3.0 clocks are supported.\n"); | |
770 | return 0; | |
771 | } | |
772 | ||
773 | } else { | |
774 | if (2 <= caslat && caslat <= 5) { | |
775 | mode_caslat = caslat; | |
776 | } else { | |
777 | puts("DDR II: Only CAS Latencies of 2.0, 3.0, " | |
778 | "4.0 and 5.0 clocks are supported.\n"); | |
779 | return 0; | |
780 | } | |
781 | } | |
782 | ||
783 | /* | |
9a655876 | 784 | * Encoded Burst Length of 4. |
debb7354 JL |
785 | */ |
786 | burst_len = 2; /* Fiat. */ | |
787 | ||
788 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
789 | twr_auto_clk = 0; /* Historical */ | |
790 | } else { | |
791 | /* | |
792 | * Determine tCK max in picos. Grab tWR and convert to picos. | |
793 | * Auto-precharge write recovery is: | |
794 | * WR = roundup(tWR_ns/tCKmax_ns). | |
795 | * | |
796 | * Ponder: Is twr_auto_clk different than twr_clk? | |
797 | */ | |
798 | tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax); | |
799 | twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps; | |
800 | } | |
801 | ||
debb7354 JL |
802 | /* |
803 | * Mode Reg in bits 16 ~ 31, | |
804 | * Extended Mode Reg 1 in bits 0 ~ 15. | |
805 | */ | |
806 | mode_odt_enable = 0x0; /* Default disabled */ | |
807 | if (odt_wr_cfg || odt_rd_cfg) { | |
808 | /* | |
809 | * Bits 6 and 2 in Extended MRS(1) | |
810 | * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. | |
811 | * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. | |
812 | */ | |
813 | mode_odt_enable = 0x40; /* 150 Ohm */ | |
814 | } | |
815 | ||
9a655876 | 816 | ddr->sdram_mode_1 = |
debb7354 JL |
817 | (0 |
818 | | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | |
819 | | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ | |
820 | | (twr_auto_clk << 9) /* Write Recovery Autopre */ | |
821 | | (mode_caslat << 4) /* caslat */ | |
822 | | (burst_len << 0) /* Burst length */ | |
823 | ); | |
824 | ||
9a655876 | 825 | debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1); |
debb7354 | 826 | |
debb7354 JL |
827 | /* |
828 | * Clear EMRS2 and EMRS3. | |
829 | */ | |
9a655876 JL |
830 | ddr->sdram_mode_2 = 0; |
831 | debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); | |
debb7354 | 832 | |
debb7354 | 833 | /* |
1fd5699a | 834 | * Determine Refresh Rate. |
debb7354 | 835 | */ |
1fd5699a | 836 | refresh_clk = determine_refresh_rate(spd.refresh & 0x7); |
debb7354 | 837 | |
1fd5699a JL |
838 | /* |
839 | * Set BSTOPRE to 0x100 for page mode | |
840 | * If auto-charge is used, set BSTOPRE = 0 | |
841 | */ | |
842 | ddr->sdram_interval = | |
843 | (0 | |
844 | | (refresh_clk & 0x3fff) << 16 | |
845 | | 0x100 | |
846 | ); | |
847 | debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); | |
debb7354 | 848 | |
debb7354 JL |
849 | |
850 | /* | |
851 | * Is this an ECC DDR chip? | |
852 | * But don't mess with it if the DDR controller will init mem. | |
853 | */ | |
854 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
855 | if (spd.config == 0x02) { | |
9a655876 JL |
856 | ddr->err_disable = 0x0000000d; |
857 | ddr->err_sbe = 0x00ff0000; | |
debb7354 | 858 | } |
9a655876 JL |
859 | debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); |
860 | debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); | |
debb7354 JL |
861 | #endif |
862 | ||
cd6d73d5 | 863 | asm volatile("sync;isync"); |
debb7354 JL |
864 | udelay(500); |
865 | ||
866 | /* | |
867 | * SDRAM Cfg 2 | |
868 | */ | |
869 | ||
870 | /* | |
871 | * When ODT is enabled, Chap 9 suggests asserting ODT to | |
872 | * internal IOs only during reads. | |
873 | */ | |
874 | odt_cfg = 0; | |
875 | if (odt_rd_cfg | odt_wr_cfg) { | |
876 | odt_cfg = 0x2; /* ODT to IOs during reads */ | |
877 | } | |
878 | ||
879 | /* | |
880 | * Try to use differential DQS with DDR II. | |
881 | */ | |
882 | if (spd.mem_type == SPD_MEMTYPE_DDR) { | |
883 | dqs_cfg = 0; /* No Differential DQS for DDR I */ | |
884 | } else { | |
885 | dqs_cfg = 0x1; /* Differential DQS for DDR II */ | |
886 | } | |
887 | ||
888 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
889 | /* | |
890 | * Use the DDR controller to auto initialize memory. | |
891 | */ | |
892 | d_init = 1; | |
9a655876 JL |
893 | ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE; |
894 | debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init); | |
debb7354 JL |
895 | #else |
896 | /* | |
897 | * Memory will be initialized via DMA, or not at all. | |
898 | */ | |
5c9efb36 | 899 | d_init = 0; |
debb7354 JL |
900 | #endif |
901 | ||
9a655876 | 902 | ddr->sdram_cfg_2 = (0 |
debb7354 JL |
903 | | (dqs_cfg << 26) /* Differential DQS */ |
904 | | (odt_cfg << 21) /* ODT */ | |
905 | | (d_init << 4) /* D_INIT auto init DDR */ | |
906 | ); | |
907 | ||
9a655876 | 908 | debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2); |
debb7354 JL |
909 | |
910 | ||
911 | #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL | |
1fd5699a JL |
912 | /* |
913 | * Setup the clock control. | |
914 | * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 | |
915 | * SDRAM_CLK_CNTL[5-7] = Clock Adjust | |
916 | * 0110 3/4 cycle late | |
917 | * 0111 7/8 cycle late | |
918 | */ | |
919 | if (spd.mem_type == SPD_MEMTYPE_DDR) | |
920 | clk_adjust = 0x6; | |
921 | else | |
922 | clk_adjust = 0x7; | |
debb7354 | 923 | |
1fd5699a | 924 | ddr->sdram_clk_cntl = (0 |
debb7354 JL |
925 | | 0x80000000 |
926 | | (clk_adjust << 23) | |
927 | ); | |
1fd5699a | 928 | debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); |
debb7354 JL |
929 | #endif |
930 | ||
931 | /* | |
9a655876 | 932 | * Figure out memory size in Megabytes. |
debb7354 | 933 | */ |
9a655876 JL |
934 | debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density); |
935 | memsize = n_ranks * rank_density / 0x100000; | |
936 | return memsize; | |
937 | } | |
938 | ||
939 | ||
940 | unsigned int enable_ddr(unsigned int ddr_num) | |
941 | { | |
942 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
943 | spd_eeprom_t spd1,spd2; | |
944 | volatile ccsr_ddr_t *ddr; | |
945 | unsigned sdram_cfg_1; | |
04efddc8 | 946 | unsigned char sdram_type, mem_type, mod_attr; |
9a655876 JL |
947 | unsigned char d_init; |
948 | unsigned int no_dimm1=0, no_dimm2=0; | |
949 | ||
950 | /* Set up pointer to enable the current ddr controller */ | |
951 | if (ddr_num == 1) | |
952 | ddr = &immap->im_ddr1; | |
953 | else | |
954 | ddr = &immap->im_ddr2; | |
debb7354 JL |
955 | |
956 | /* | |
9a655876 JL |
957 | * Read both dimm slots and decide whether |
958 | * or not to enable this controller. | |
debb7354 | 959 | */ |
2491167c JL |
960 | memset((void *)&spd1, 0, sizeof(spd1)); |
961 | memset((void *)&spd2, 0, sizeof(spd2)); | |
9a655876 JL |
962 | |
963 | if (ddr_num == 1) { | |
964 | CFG_READ_SPD(SPD_EEPROM_ADDRESS1, | |
965 | 0, 1, (uchar *) &spd1, sizeof(spd1)); | |
2491167c | 966 | #if defined(SPD_EEPROM_ADDRESS2) |
9a655876 JL |
967 | CFG_READ_SPD(SPD_EEPROM_ADDRESS2, |
968 | 0, 1, (uchar *) &spd2, sizeof(spd2)); | |
2491167c | 969 | #endif |
9a655876 | 970 | } else { |
2491167c | 971 | #if defined(SPD_EEPROM_ADDRESS3) |
9a655876 JL |
972 | CFG_READ_SPD(SPD_EEPROM_ADDRESS3, |
973 | 0, 1, (uchar *) &spd1, sizeof(spd1)); | |
2491167c JL |
974 | #endif |
975 | #if defined(SPD_EEPROM_ADDRESS4) | |
9a655876 JL |
976 | CFG_READ_SPD(SPD_EEPROM_ADDRESS4, |
977 | 0, 1, (uchar *) &spd2, sizeof(spd2)); | |
2491167c | 978 | #endif |
debb7354 JL |
979 | } |
980 | ||
debb7354 | 981 | /* |
9a655876 | 982 | * Check for supported memory module types. |
debb7354 | 983 | */ |
9a655876 JL |
984 | if (spd1.mem_type != SPD_MEMTYPE_DDR |
985 | && spd1.mem_type != SPD_MEMTYPE_DDR2) { | |
986 | no_dimm1 = 1; | |
987 | } else { | |
988 | debug("\nFound memory of type 0x%02lx ",spd1.mem_type ); | |
989 | if (spd1.mem_type == SPD_MEMTYPE_DDR) | |
990 | debug("DDR I\n"); | |
991 | else | |
992 | debug("DDR II\n"); | |
993 | } | |
994 | ||
995 | if (spd2.mem_type != SPD_MEMTYPE_DDR && | |
996 | spd2.mem_type != SPD_MEMTYPE_DDR2) { | |
997 | no_dimm2 = 1; | |
998 | } else { | |
999 | debug("\nFound memory of type 0x%02lx ",spd2.mem_type ); | |
1000 | if (spd2.mem_type == SPD_MEMTYPE_DDR) | |
1001 | debug("DDR I\n"); | |
1002 | else | |
1003 | debug("DDR II\n"); | |
1004 | } | |
1005 | ||
1006 | #ifdef CONFIG_DDR_INTERLEAVE | |
1007 | if (no_dimm1) { | |
1008 | printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n"); | |
1009 | return 0; | |
debb7354 JL |
1010 | } |
1011 | #endif | |
1012 | ||
1013 | /* | |
9a655876 | 1014 | * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn |
debb7354 | 1015 | */ |
9a655876 JL |
1016 | if (no_dimm1 && no_dimm2) { |
1017 | printf("No memory modules found for DDR controller %d!!\n", ddr_num); | |
1018 | return 0; | |
1019 | } else { | |
04efddc8 JCPV |
1020 | |
1021 | #if defined(CONFIG_DDR_ECC) | |
1022 | unsigned char config; | |
1023 | #endif | |
9a655876 | 1024 | mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type; |
debb7354 | 1025 | |
9a655876 JL |
1026 | /* |
1027 | * Figure out the settings for the sdram_cfg register. | |
1028 | * Build up the entire register in 'sdram_cfg' before | |
1029 | * writing since the write into the register will | |
1030 | * actually enable the memory controller; all settings | |
1031 | * must be done before enabling. | |
1032 | * | |
1033 | * sdram_cfg[0] = 1 (ddr sdram logic enable) | |
1034 | * sdram_cfg[1] = 1 (self-refresh-enable) | |
1035 | * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) | |
1036 | * 010 DDR 1 SDRAM | |
1037 | * 011 DDR 2 SDRAM | |
1038 | */ | |
1039 | sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3; | |
1040 | sdram_cfg_1 = (0 | |
1041 | | (1 << 31) /* Enable */ | |
1042 | | (1 << 30) /* Self refresh */ | |
1043 | | (sdram_type << 24) /* SDRAM type */ | |
1044 | ); | |
1045 | ||
1046 | /* | |
1047 | * sdram_cfg[3] = RD_EN - registered DIMM enable | |
1048 | * A value of 0x26 indicates micron registered | |
1049 | * DIMMS (micron.com) | |
1050 | */ | |
1051 | mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr; | |
1052 | if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) { | |
1053 | sdram_cfg_1 |= 0x10000000; /* RD_EN */ | |
1054 | } | |
1055 | ||
1056 | #if defined(CONFIG_DDR_ECC) | |
1057 | ||
1058 | config = no_dimm2 ? spd1.config : spd2.config; | |
1059 | ||
1060 | /* | |
1061 | * If the user wanted ECC (enabled via sdram_cfg[2]) | |
1062 | */ | |
1063 | if (config == 0x02) { | |
70205e5a | 1064 | ddr->err_disable = 0x00000000; |
cd6d73d5 | 1065 | asm volatile("sync;isync;"); |
70205e5a HW |
1066 | ddr->err_sbe = 0x00ff0000; |
1067 | ddr->err_int_en = 0x0000000d; | |
9a655876 JL |
1068 | sdram_cfg_1 |= 0x20000000; /* ECC_EN */ |
1069 | } | |
1070 | #endif | |
1071 | ||
1072 | /* | |
70205e5a | 1073 | * Set 1T or 2T timing based on 1 or 2 modules |
9a655876 JL |
1074 | */ |
1075 | { | |
70205e5a | 1076 | if (!(no_dimm1 || no_dimm2)) { |
9a655876 | 1077 | /* |
70205e5a | 1078 | * 2T timing,because both DIMMS are present. |
9a655876 JL |
1079 | * Enable 2T timing by setting sdram_cfg[16]. |
1080 | */ | |
1081 | sdram_cfg_1 |= 0x8000; /* 2T_EN */ | |
9a655876 | 1082 | } |
debb7354 | 1083 | } |
debb7354 | 1084 | |
9a655876 JL |
1085 | /* |
1086 | * 200 painful micro-seconds must elapse between | |
1087 | * the DDR clock setup and the DDR config enable. | |
1088 | */ | |
1089 | udelay(200); | |
debb7354 | 1090 | |
9a655876 JL |
1091 | /* |
1092 | * Go! | |
1093 | */ | |
1094 | ddr->sdram_cfg_1 = sdram_cfg_1; | |
debb7354 | 1095 | |
9a655876 JL |
1096 | asm volatile("sync;isync"); |
1097 | udelay(500); | |
debb7354 | 1098 | |
9a655876 | 1099 | debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1); |
debb7354 JL |
1100 | |
1101 | ||
1102 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
9a655876 JL |
1103 | d_init = 1; |
1104 | debug("DDR: memory initializing\n"); | |
1105 | ||
1106 | /* | |
1107 | * Poll until memory is initialized. | |
1108 | * 512 Meg at 400 might hit this 200 times or so. | |
1109 | */ | |
1110 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { | |
1111 | udelay(1000); | |
1112 | } | |
1113 | debug("DDR: memory initialized\n\n"); | |
1114 | #endif | |
1115 | ||
1116 | debug("Enabled DDR Controller %d\n", ddr_num); | |
1117 | return 1; | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | ||
1122 | long int | |
1123 | spd_sdram(void) | |
1124 | { | |
1125 | int memsize_ddr1_dimm1 = 0; | |
1126 | int memsize_ddr1_dimm2 = 0; | |
2491167c JL |
1127 | int memsize_ddr1 = 0; |
1128 | unsigned int law_size_ddr1; | |
409ecdc0 | 1129 | #ifdef CONFIG_DDR_INTERLEAVE |
04efddc8 | 1130 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
409ecdc0 WD |
1131 | volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1; |
1132 | #endif | |
2491167c JL |
1133 | |
1134 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) | |
9a655876 JL |
1135 | int memsize_ddr2_dimm1 = 0; |
1136 | int memsize_ddr2_dimm2 = 0; | |
9a655876 | 1137 | int memsize_ddr2 = 0; |
2491167c JL |
1138 | unsigned int law_size_ddr2; |
1139 | #endif | |
1140 | ||
9a655876 JL |
1141 | unsigned int ddr1_enabled = 0; |
1142 | unsigned int ddr2_enabled = 0; | |
2491167c | 1143 | int memsize_total = 0; |
9a655876 JL |
1144 | |
1145 | #ifdef CONFIG_DDR_INTERLEAVE | |
1146 | unsigned int law_size_interleaved; | |
ea08ff6e | 1147 | volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2; |
9a655876 JL |
1148 | |
1149 | memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, | |
1150 | 1, 1, | |
1151 | (unsigned int)memsize_total * 1024*1024); | |
1152 | memsize_total += memsize_ddr1_dimm1; | |
1153 | ||
1154 | memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, | |
1155 | 2, 1, | |
1156 | (unsigned int)memsize_total * 1024*1024); | |
1157 | memsize_total += memsize_ddr2_dimm1; | |
1158 | ||
1159 | if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) { | |
1160 | if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1) | |
1161 | memsize_total -= memsize_ddr1_dimm1; | |
1162 | else | |
1163 | memsize_total -= memsize_ddr2_dimm1; | |
1164 | debug("Total memory available for interleaving 0x%08lx\n", | |
1165 | memsize_total * 1024 * 1024); | |
1166 | debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n"); | |
1167 | ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; | |
1168 | ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24; | |
1169 | debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds); | |
1170 | debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds); | |
debb7354 | 1171 | } |
9a655876 JL |
1172 | |
1173 | ddr1_enabled = enable_ddr(1); | |
1174 | ddr2_enabled = enable_ddr(2); | |
1175 | ||
1176 | /* | |
1177 | * Both controllers need to be enabled for interleaving. | |
1178 | */ | |
1179 | if (ddr1_enabled && ddr2_enabled) { | |
1180 | law_size_interleaved = 19 + __ilog2(memsize_total); | |
1181 | ||
1182 | /* | |
1183 | * Set up LAWBAR for DDR 1 space. | |
1184 | */ | |
4933b91f | 1185 | #ifdef CONFIG_FSL_LAW |
859a86a2 | 1186 | set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); |
4933b91f | 1187 | #endif |
9a655876 JL |
1188 | debug("Interleaved memory size is 0x%08lx\n", memsize_total); |
1189 | ||
9a655876 JL |
1190 | #if (CFG_PAGE_INTERLEAVING == 1) |
1191 | printf("Page "); | |
1192 | #elif (CFG_BANK_INTERLEAVING == 1) | |
1193 | printf("Bank "); | |
1194 | #elif (CFG_SUPER_BANK_INTERLEAVING == 1) | |
1195 | printf("Super-bank "); | |
1196 | #else | |
1197 | printf("Cache-line "); | |
9a655876 JL |
1198 | #endif |
1199 | printf("Interleaved"); | |
1200 | return memsize_total * 1024 * 1024; | |
1201 | } else { | |
1202 | printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n"); | |
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | #else | |
1207 | /* | |
1208 | * Call spd_sdram() routine to init ddr1 - pass I2c address, | |
1209 | * controller number, dimm number, and starting address. | |
1210 | */ | |
1211 | memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1, | |
1212 | 1, 1, | |
1213 | (unsigned int)memsize_total * 1024*1024); | |
1214 | memsize_total += memsize_ddr1_dimm1; | |
debb7354 | 1215 | |
2491167c | 1216 | #if defined(SPD_EEPROM_ADDRESS2) |
9a655876 JL |
1217 | memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2, |
1218 | 1, 2, | |
1219 | (unsigned int)memsize_total * 1024*1024); | |
2491167c | 1220 | #endif |
9a655876 | 1221 | memsize_total += memsize_ddr1_dimm2; |
debb7354 JL |
1222 | |
1223 | /* | |
9a655876 | 1224 | * Enable the DDR controller - pass ddr controller number. |
debb7354 | 1225 | */ |
9a655876 | 1226 | ddr1_enabled = enable_ddr(1); |
debb7354 | 1227 | |
9a655876 JL |
1228 | /* Keep track of memory to be addressed by DDR1 */ |
1229 | memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2; | |
debb7354 | 1230 | |
9a655876 | 1231 | /* |
debb7354 JL |
1232 | * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord. |
1233 | */ | |
9a655876 JL |
1234 | if (ddr1_enabled) { |
1235 | law_size_ddr1 = 19 + __ilog2(memsize_ddr1); | |
1236 | ||
1237 | /* | |
1238 | * Set up LAWBAR for DDR 1 space. | |
1239 | */ | |
4933b91f | 1240 | #ifdef CONFIG_FSL_LAW |
859a86a2 | 1241 | set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); |
4933b91f | 1242 | #endif |
9a655876 JL |
1243 | } |
1244 | ||
1245 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) | |
1246 | memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3, | |
1247 | 2, 1, | |
1248 | (unsigned int)memsize_total * 1024*1024); | |
1249 | memsize_total += memsize_ddr2_dimm1; | |
1250 | ||
1251 | memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4, | |
1252 | 2, 2, | |
1253 | (unsigned int)memsize_total * 1024*1024); | |
1254 | memsize_total += memsize_ddr2_dimm2; | |
1255 | ||
1256 | ddr2_enabled = enable_ddr(2); | |
1257 | ||
1258 | /* Keep track of memory to be addressed by DDR2 */ | |
1259 | memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2; | |
1260 | ||
1261 | if (ddr2_enabled) { | |
1262 | law_size_ddr2 = 19 + __ilog2(memsize_ddr2); | |
1263 | ||
1264 | /* | |
1265 | * Set up LAWBAR for DDR 2 space. | |
1266 | */ | |
4933b91f | 1267 | #ifdef CONFIG_FSL_LAW |
859a86a2 | 1268 | set_next_law( |
4933b91f BB |
1269 | (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE), |
1270 | law_size_ddr2, LAW_TRGT_IF_DDR_2); | |
4933b91f | 1271 | #endif |
9a655876 | 1272 | } |
d08b7233 JL |
1273 | |
1274 | debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); | |
1275 | ||
9a655876 JL |
1276 | #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ |
1277 | ||
d08b7233 | 1278 | debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1); |
debb7354 JL |
1279 | |
1280 | /* | |
9a655876 | 1281 | * If neither DDR controller is enabled return 0. |
debb7354 | 1282 | */ |
9a655876 JL |
1283 | if (!ddr1_enabled && !ddr2_enabled) |
1284 | return 0; | |
1fd5699a JL |
1285 | |
1286 | printf("Non-interleaved"); | |
1287 | return memsize_total * 1024 * 1024; | |
5c9efb36 | 1288 | |
9a655876 | 1289 | #endif /* CONFIG_DDR_INTERLEAVE */ |
debb7354 JL |
1290 | } |
1291 | ||
9a655876 | 1292 | |
debb7354 JL |
1293 | #endif /* CONFIG_SPD_EEPROM */ |
1294 | ||
1295 | ||
1296 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
1297 | ||
1298 | /* | |
1299 | * Initialize all of memory for ECC, then enable errors. | |
1300 | */ | |
1301 | ||
1302 | void | |
1303 | ddr_enable_ecc(unsigned int dram_size) | |
1304 | { | |
1305 | uint *p = 0; | |
1306 | uint i = 0; | |
1307 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
1308 | volatile ccsr_ddr_t *ddr1= &immap->im_ddr1; | |
1309 | ||
1310 | dma_init(); | |
1311 | ||
1312 | for (*p = 0; p < (uint *)(8 * 1024); p++) { | |
1313 | if (((unsigned int)p & 0x1f) == 0) { | |
1314 | ppcDcbz((unsigned long) p); | |
1315 | } | |
1316 | *p = (unsigned int)CONFIG_MEM_INIT_VALUE; | |
1317 | if (((unsigned int)p & 0x1c) == 0x1c) { | |
1318 | ppcDcbf((unsigned long) p); | |
1319 | } | |
1320 | } | |
1321 | ||
1fd5699a JL |
1322 | dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */ |
1323 | dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */ | |
1324 | dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */ | |
1325 | dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */ | |
1326 | dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */ | |
1327 | dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */ | |
1328 | dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */ | |
1329 | dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ | |
1330 | dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ | |
1331 | dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ | |
debb7354 JL |
1332 | |
1333 | for (i = 1; i < dram_size / 0x800000; i++) { | |
1334 | dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); | |
1335 | } | |
1336 | ||
1337 | /* | |
1338 | * Enable errors for ECC. | |
1339 | */ | |
1340 | debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); | |
1341 | ddr1->err_disable = 0x00000000; | |
cd6d73d5 | 1342 | asm volatile("sync;isync"); |
debb7354 JL |
1343 | debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); |
1344 | } | |
1345 | ||
1346 | #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ |