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c609719b WD |
1 | /* |
2 | * (C) Copyright 2000-2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * m8xx.c | |
26 | * | |
27 | * CPU specific code | |
28 | * | |
29 | * written or collected and sometimes rewritten by | |
30 | * Magnus Damm <damm@bitsmart.com> | |
31 | * | |
32 | * minor modifications by | |
33 | * Wolfgang Denk <wd@denx.de> | |
34 | */ | |
35 | ||
36 | #include <common.h> | |
37 | #include <watchdog.h> | |
38 | #include <command.h> | |
39 | #include <mpc8xx.h> | |
40 | #include <asm/cache.h> | |
41 | ||
42 | static char *cpu_warning = "\n " \ | |
43 | "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***"; | |
44 | ||
45 | #if ((defined(CONFIG_MPC860) || defined(CONFIG_MPC855)) && \ | |
46 | !defined(CONFIG_MPC862)) | |
d126bfbd | 47 | # ifdef CONFIG_MPC855 |
c609719b WD |
48 | # define ID_STR "PC855" |
49 | # else | |
50 | # define ID_STR "PC860" | |
51 | # endif | |
52 | ||
53 | static int check_CPU (long clock, uint pvr, uint immr) | |
54 | { | |
55 | volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); | |
56 | uint k, m; | |
57 | char buf[32]; | |
58 | char pre = 'X'; | |
59 | char *mid = "xx"; | |
60 | char *suf; | |
61 | ||
62 | /* the highest 16 bits should be 0x0050 for a 860 */ | |
63 | ||
64 | if ((pvr >> 16) != 0x0050) | |
65 | return -1; | |
66 | ||
67 | k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); | |
68 | m = 0; | |
69 | ||
70 | switch (k) { | |
71 | case 0x00020001: pre = 'p'; suf = ""; break; | |
72 | case 0x00030001: suf = ""; break; | |
73 | case 0x00120003: suf = "A"; break; | |
74 | case 0x00130003: suf = "A3"; break; | |
75 | ||
76 | case 0x00200004: suf = "B"; break; | |
77 | ||
78 | case 0x00300004: suf = "C"; break; | |
79 | case 0x00310004: suf = "C1"; m = 1; | |
80 | break; | |
81 | ||
82 | case 0x00200064: mid = "SR"; suf = "B"; break; | |
83 | case 0x00300065: mid = "SR"; suf = "C"; break; | |
84 | case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break; | |
85 | case 0x05010000: suf = "D3"; m = 1; break; | |
86 | case 0x05020000: suf = "D4"; m = 1; break; | |
87 | ||
88 | /* this value is not documented anywhere */ | |
89 | case 0x40000000: pre = 'P'; suf = "D"; m = 1; break; | |
90 | ||
91 | default: suf = NULL; break; | |
92 | } | |
93 | ||
94 | if (suf) | |
95 | printf ("%c" ID_STR "%sZPnn%s", pre, mid, suf); | |
96 | else | |
97 | printf ("unknown M" ID_STR " (0x%08x)", k); | |
98 | ||
99 | printf (" at %s MHz:", strmhz (buf, clock)); | |
100 | ||
101 | printf (" %u kB I-Cache", checkicache () >> 10); | |
102 | printf (" %u kB D-Cache", checkdcache () >> 10); | |
103 | ||
104 | /* lets check and see if we're running on a 860T (or P?) */ | |
105 | ||
106 | immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; | |
107 | if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { | |
108 | printf (" FEC present"); | |
109 | } | |
110 | ||
111 | if (!m) { | |
112 | puts (cpu_warning); | |
113 | } | |
114 | ||
115 | putc ('\n'); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
120 | #elif defined(CONFIG_MPC862) | |
121 | ||
122 | static int check_CPU (long clock, uint pvr, uint immr) | |
123 | { | |
124 | volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); | |
125 | uint k, m; | |
126 | char buf[32]; | |
127 | char pre = 'X'; | |
128 | char *mid = "xx"; | |
129 | char *suf; | |
130 | ||
131 | /* the highest 16 bits should be 0x0050 for a 8xx */ | |
132 | ||
133 | if ((pvr >> 16) != 0x0050) | |
134 | return -1; | |
135 | ||
136 | k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); | |
137 | m = 0; | |
138 | ||
139 | switch (k) { | |
140 | ||
141 | /* this value is not documented anywhere */ | |
142 | case 0x06000000: mid = "P"; suf = "0"; break; | |
143 | case 0x06010001: mid = "P"; suf = "A"; m = 1; break; | |
144 | case 0x07000003: mid = "P"; suf = "B"; m = 1; break; | |
145 | default: suf = NULL; break; | |
146 | } | |
147 | ||
148 | if (suf) | |
149 | printf ("%cPC862%sZPnn%s", pre, mid, suf); | |
150 | else | |
151 | printf ("unknown MPC862 (0x%08x)", k); | |
152 | ||
153 | printf (" at %s MHz:", strmhz (buf, clock)); | |
154 | ||
155 | printf (" %u kB I-Cache", checkicache () >> 10); | |
156 | printf (" %u kB D-Cache", checkdcache () >> 10); | |
157 | ||
158 | /* lets check and see if we're running on a 862T (or P?) */ | |
159 | ||
160 | immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; | |
161 | if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { | |
162 | printf (" FEC present"); | |
163 | } | |
164 | ||
165 | if (!m) { | |
166 | puts (cpu_warning); | |
167 | } | |
168 | ||
169 | putc ('\n'); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | #elif defined(CONFIG_MPC823) | |
175 | ||
176 | static int check_CPU (long clock, uint pvr, uint immr) | |
177 | { | |
178 | volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); | |
179 | uint k, m; | |
180 | char buf[32]; | |
181 | char *suf; | |
182 | ||
183 | /* the highest 16 bits should be 0x0050 for a 8xx */ | |
184 | ||
185 | if ((pvr >> 16) != 0x0050) | |
186 | return -1; | |
187 | ||
188 | k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); | |
189 | m = 0; | |
190 | ||
191 | switch (k) { | |
192 | /* MPC823 */ | |
193 | case 0x20000000: suf = "0"; break; | |
194 | case 0x20010000: suf = "0.1"; break; | |
195 | case 0x20020000: suf = "Z2/3"; break; | |
196 | case 0x20020001: suf = "Z3"; break; | |
197 | case 0x21000000: suf = "A"; break; | |
198 | case 0x21010000: suf = "B"; m = 1; break; | |
199 | case 0x21010001: suf = "B2"; m = 1; break; | |
200 | /* MPC823E */ | |
201 | case 0x24010000: suf = NULL; | |
202 | puts ("PPC823EZTnnB2"); | |
203 | m = 1; | |
204 | break; | |
205 | default: | |
206 | suf = NULL; | |
207 | printf ("unknown MPC823 (0x%08x)", k); | |
208 | break; | |
209 | } | |
210 | if (suf) | |
211 | printf ("PPC823ZTnn%s", suf); | |
212 | ||
213 | printf (" at %s MHz:", strmhz (buf, clock)); | |
214 | ||
215 | printf (" %u kB I-Cache", checkicache () >> 10); | |
216 | printf (" %u kB D-Cache", checkdcache () >> 10); | |
217 | ||
218 | /* lets check and see if we're running on a 860T (or P?) */ | |
219 | ||
220 | immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; | |
221 | if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { | |
222 | puts (" FEC present"); | |
223 | } | |
224 | ||
225 | if (!m) { | |
226 | puts (cpu_warning); | |
227 | } | |
228 | ||
229 | putc ('\n'); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | #elif defined(CONFIG_MPC850) | |
235 | ||
236 | static int check_CPU (long clock, uint pvr, uint immr) | |
237 | { | |
238 | volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); | |
239 | uint k, m; | |
240 | char buf[32]; | |
241 | ||
242 | /* the highest 16 bits should be 0x0050 for a 8xx */ | |
243 | ||
244 | if ((pvr >> 16) != 0x0050) | |
245 | return -1; | |
246 | ||
247 | k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); | |
248 | m = 0; | |
249 | ||
250 | switch (k) { | |
251 | case 0x20020001: | |
252 | printf ("XPC850xxZT"); | |
253 | break; | |
254 | case 0x21000065: | |
255 | printf ("XPC850xxZTA"); | |
256 | break; | |
257 | case 0x21010067: | |
258 | printf ("XPC850xxZTB"); | |
259 | m = 1; | |
260 | break; | |
261 | case 0x21020068: | |
262 | printf ("XPC850xxZTC"); | |
263 | m = 1; | |
264 | break; | |
265 | default: | |
266 | printf ("unknown MPC850 (0x%08x)", k); | |
267 | } | |
268 | printf (" at %s MHz:", strmhz (buf, clock)); | |
269 | ||
270 | printf (" %u kB I-Cache", checkicache () >> 10); | |
271 | printf (" %u kB D-Cache", checkdcache () >> 10); | |
272 | ||
273 | /* lets check and see if we're running on a 850T (or P?) */ | |
274 | ||
275 | immap->im_cpm.cp_fec.fec_addr_low = 0x12345678; | |
276 | if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) { | |
277 | printf (" FEC present"); | |
278 | } | |
279 | ||
280 | if (!m) { | |
281 | puts (cpu_warning); | |
282 | } | |
283 | ||
284 | putc ('\n'); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | #else | |
289 | #error CPU undefined | |
290 | #endif | |
291 | /* ------------------------------------------------------------------------- */ | |
292 | ||
293 | int checkcpu (void) | |
294 | { | |
295 | DECLARE_GLOBAL_DATA_PTR; | |
296 | ||
297 | ulong clock = gd->cpu_clk; | |
298 | uint immr = get_immr (0); /* Return full IMMR contents */ | |
299 | uint pvr = get_pvr (); | |
300 | ||
301 | puts ("CPU: "); | |
302 | ||
303 | /* 850 has PARTNUM 20 */ | |
304 | /* 801 has PARTNUM 10 */ | |
305 | return check_CPU (clock, pvr, immr); | |
306 | } | |
307 | ||
308 | /* ------------------------------------------------------------------------- */ | |
309 | /* L1 i-cache */ | |
310 | /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ | |
311 | /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB) */ | |
312 | ||
313 | int checkicache (void) | |
314 | { | |
315 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
316 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
317 | u32 cacheon = rd_ic_cst () & IDC_ENABLED; | |
318 | ||
319 | #ifdef CONFIG_IP860 | |
320 | u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ | |
321 | #else | |
322 | u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ | |
323 | #endif | |
324 | u32 m; | |
325 | u32 lines = -1; | |
326 | ||
327 | wr_ic_cst (IDC_UNALL); | |
328 | wr_ic_cst (IDC_INVALL); | |
329 | wr_ic_cst (IDC_DISABLE); | |
330 | __asm__ volatile ("isync"); | |
331 | ||
332 | while (!((m = rd_ic_cst ()) & IDC_CERR2)) { | |
333 | wr_ic_adr (k); | |
334 | wr_ic_cst (IDC_LDLCK); | |
335 | __asm__ volatile ("isync"); | |
336 | ||
337 | lines++; | |
338 | k += 0x10; /* the number of bytes in a cacheline */ | |
339 | } | |
340 | ||
341 | wr_ic_cst (IDC_UNALL); | |
342 | wr_ic_cst (IDC_INVALL); | |
343 | ||
344 | if (cacheon) | |
345 | wr_ic_cst (IDC_ENABLE); | |
346 | else | |
347 | wr_ic_cst (IDC_DISABLE); | |
348 | ||
349 | __asm__ volatile ("isync"); | |
350 | ||
351 | return lines << 4; | |
352 | }; | |
353 | ||
354 | /* ------------------------------------------------------------------------- */ | |
355 | /* L1 d-cache */ | |
356 | /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB) */ | |
357 | /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB) */ | |
358 | /* call with cache disabled */ | |
359 | ||
360 | int checkdcache (void) | |
361 | { | |
362 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
363 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
364 | u32 cacheon = rd_dc_cst () & IDC_ENABLED; | |
365 | ||
366 | #ifdef CONFIG_IP860 | |
367 | u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */ | |
368 | #else | |
369 | u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */ | |
370 | #endif | |
371 | u32 m; | |
372 | u32 lines = -1; | |
373 | ||
374 | wr_dc_cst (IDC_UNALL); | |
375 | wr_dc_cst (IDC_INVALL); | |
376 | wr_dc_cst (IDC_DISABLE); | |
377 | ||
378 | while (!((m = rd_dc_cst ()) & IDC_CERR2)) { | |
379 | wr_dc_adr (k); | |
380 | wr_dc_cst (IDC_LDLCK); | |
381 | lines++; | |
382 | k += 0x10; /* the number of bytes in a cacheline */ | |
383 | } | |
384 | ||
385 | wr_dc_cst (IDC_UNALL); | |
386 | wr_dc_cst (IDC_INVALL); | |
387 | ||
388 | if (cacheon) | |
389 | wr_dc_cst (IDC_ENABLE); | |
390 | else | |
391 | wr_dc_cst (IDC_DISABLE); | |
392 | ||
393 | return lines << 4; | |
394 | }; | |
395 | ||
396 | /* ------------------------------------------------------------------------- */ | |
397 | ||
398 | void upmconfig (uint upm, uint * table, uint size) | |
399 | { | |
400 | uint i; | |
401 | uint addr = 0; | |
402 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
403 | volatile memctl8xx_t *memctl = &immap->im_memctl; | |
404 | ||
405 | for (i = 0; i < size; i++) { | |
406 | memctl->memc_mdr = table[i]; /* (16-15) */ | |
407 | memctl->memc_mcr = addr | upm; /* (16-16) */ | |
408 | addr++; | |
409 | } | |
410 | } | |
411 | ||
412 | /* ------------------------------------------------------------------------- */ | |
413 | ||
8bde7f77 | 414 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
c609719b WD |
415 | { |
416 | ulong msr, addr; | |
417 | ||
418 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
419 | ||
420 | immap->im_clkrst.car_plprcr |= PLPRCR_CSR; /* Checkstop Reset enable */ | |
421 | ||
422 | /* Interrupts and MMU off */ | |
423 | __asm__ volatile ("mtspr 81, 0"); | |
424 | __asm__ volatile ("mfmsr %0":"=r" (msr)); | |
425 | ||
426 | msr &= ~0x1030; | |
427 | __asm__ volatile ("mtmsr %0"::"r" (msr)); | |
428 | ||
429 | /* | |
430 | * Trying to execute the next instruction at a non-existing address | |
431 | * should cause a machine check, resulting in reset | |
432 | */ | |
433 | #ifdef CFG_RESET_ADDRESS | |
434 | addr = CFG_RESET_ADDRESS; | |
435 | #else | |
436 | /* | |
437 | * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE | |
438 | * - sizeof (ulong) is usually a valid address. Better pick an address | |
439 | * known to be invalid on your system and assign it to CFG_RESET_ADDRESS. | |
440 | * "(ulong)-1" used to be a good choice for many systems... | |
441 | */ | |
442 | addr = CFG_MONITOR_BASE - sizeof (ulong); | |
443 | #endif | |
444 | ((void (*)(void)) addr) (); | |
445 | return 1; | |
446 | } | |
447 | ||
448 | /* ------------------------------------------------------------------------- */ | |
449 | ||
450 | /* | |
451 | * Get timebase clock frequency (like cpu_clk in Hz) | |
452 | * | |
453 | * See table 15-5 pp. 15-16, and SCCR[RTSEL] pp. 15-27. | |
454 | */ | |
455 | unsigned long get_tbclk (void) | |
456 | { | |
457 | DECLARE_GLOBAL_DATA_PTR; | |
458 | ||
459 | volatile immap_t *immr = (volatile immap_t *) CFG_IMMR; | |
460 | ulong oscclk, factor; | |
461 | ||
462 | if (immr->im_clkrst.car_sccr & SCCR_TBS) { | |
463 | return (gd->cpu_clk / 16); | |
464 | } | |
465 | ||
466 | factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1; | |
467 | ||
468 | oscclk = gd->cpu_clk / factor; | |
469 | ||
470 | if ((immr->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) { | |
471 | return (oscclk / 4); | |
472 | } | |
473 | return (oscclk / 16); | |
474 | } | |
475 | ||
476 | /* ------------------------------------------------------------------------- */ | |
477 | ||
478 | #if defined(CONFIG_WATCHDOG) | |
479 | void watchdog_reset (void) | |
480 | { | |
481 | int re_enable = disable_interrupts (); | |
482 | ||
483 | reset_8xx_watchdog ((immap_t *) CFG_IMMR); | |
484 | if (re_enable) | |
485 | enable_interrupts (); | |
486 | } | |
487 | ||
488 | void reset_8xx_watchdog (volatile immap_t * immr) | |
489 | { | |
490 | # if defined(CONFIG_LWMON) | |
491 | /* | |
492 | * The LWMON board uses a MAX6301 Watchdog | |
493 | * with the trigger pin connected to port PA.7 | |
494 | * | |
495 | * (The old board version used a MAX706TESA Watchdog, which | |
496 | * had to be handled exactly the same.) | |
497 | */ | |
498 | # define WATCHDOG_BIT 0x0100 | |
499 | immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT); /* GPIO */ | |
500 | immr->im_ioport.iop_padir |= WATCHDOG_BIT; /* Output */ | |
501 | immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT); /* active output */ | |
502 | ||
503 | immr->im_ioport.iop_padat ^= WATCHDOG_BIT; /* Toggle WDI */ | |
504 | # else | |
505 | /* | |
506 | * All other boards use the MPC8xx Internal Watchdog | |
507 | */ | |
508 | immr->im_siu_conf.sc_swsr = 0x556c; /* write magic1 */ | |
509 | immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ | |
510 | # endif /* CONFIG_LWMON */ | |
511 | } | |
512 | ||
513 | #endif /* CONFIG_WATCHDOG */ | |
514 | ||
515 | /* ------------------------------------------------------------------------- */ |