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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000-2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <watchdog.h> | |
26 | ||
27 | #include <mpc8xx.h> | |
28 | #include <commproc.h> | |
29 | ||
30 | #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) | |
31 | void cpm_load_patch (volatile immap_t * immr); | |
32 | #endif | |
33 | ||
34 | /* | |
35 | * Breath some life into the CPU... | |
36 | * | |
37 | * Set up the memory map, | |
38 | * initialize a bunch of registers, | |
39 | * initialize the UPM's | |
40 | */ | |
41 | void cpu_init_f (volatile immap_t * immr) | |
42 | { | |
43 | #ifndef CONFIG_MBX | |
44 | volatile memctl8xx_t *memctl = &immr->im_memctl; | |
c178d3da | 45 | # ifdef CFG_PLPRCR |
180d3f74 | 46 | ulong mfmask; |
c178d3da | 47 | # endif |
4a9cbbe8 | 48 | #endif |
3bac3513 | 49 | ulong reg; |
4a9cbbe8 WD |
50 | |
51 | /* SYPCR - contains watchdog control (11-9) */ | |
52 | ||
53 | immr->im_siu_conf.sc_sypcr = CFG_SYPCR; | |
54 | ||
55 | #if defined(CONFIG_WATCHDOG) | |
56 | reset_8xx_watchdog (immr); | |
57 | #endif /* CONFIG_WATCHDOG */ | |
58 | ||
59 | /* SIUMCR - contains debug pin configuration (11-6) */ | |
dc7c9a1a | 60 | #ifndef CONFIG_SVM_SC8xx |
4a9cbbe8 | 61 | immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR; |
dc7c9a1a WD |
62 | #else |
63 | immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; | |
64 | #endif | |
4a9cbbe8 WD |
65 | /* initialize timebase status and control register (11-26) */ |
66 | /* unlock TBSCRK */ | |
67 | ||
68 | immr->im_sitk.sitk_tbscrk = KAPWR_KEY; | |
69 | immr->im_sit.sit_tbscr = CFG_TBSCR; | |
70 | ||
71 | /* initialize the PIT (11-31) */ | |
72 | ||
73 | immr->im_sitk.sitk_piscrk = KAPWR_KEY; | |
74 | immr->im_sit.sit_piscr = CFG_PISCR; | |
75 | ||
1cb8e980 WD |
76 | /* System integration timers. Don't change EBDF! (15-27) */ |
77 | ||
78 | immr->im_clkrstk.cark_sccrk = KAPWR_KEY; | |
79 | reg = immr->im_clkrst.car_sccr; | |
80 | reg &= SCCR_MASK; | |
81 | reg |= CFG_SCCR; | |
82 | immr->im_clkrst.car_sccr = reg; | |
83 | ||
4a9cbbe8 WD |
84 | /* PLL (CPU clock) settings (15-30) */ |
85 | ||
86 | immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; | |
87 | ||
88 | #ifndef CONFIG_MBX /* MBX board does things different */ | |
89 | ||
90 | /* If CFG_PLPRCR (set in the various *_config.h files) tries to | |
91 | * set the MF field, then just copy CFG_PLPRCR over car_plprcr, | |
180d3f74 | 92 | * otherwise OR in CFG_PLPRCR so we do not change the current MF |
4a9cbbe8 | 93 | * field value. |
180d3f74 WD |
94 | * |
95 | * For newer (starting MPC866) chips PLPRCR layout is different. | |
4a9cbbe8 | 96 | */ |
c178d3da | 97 | #ifdef CFG_PLPRCR |
180d3f74 WD |
98 | if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) |
99 | mfmask = PLPRCR_MFACT_MSK; | |
100 | else | |
101 | mfmask = PLPRCR_MF_MSK; | |
102 | ||
103 | if ((CFG_PLPRCR & mfmask) != 0) | |
104 | reg = CFG_PLPRCR; /* reset control bits */ | |
105 | else { | |
106 | reg = immr->im_clkrst.car_plprcr; | |
107 | reg &= mfmask; /* isolate MF-related fields */ | |
108 | reg |= CFG_PLPRCR; /* reset control bits */ | |
109 | } | |
4a9cbbe8 | 110 | immr->im_clkrst.car_plprcr = reg; |
c178d3da | 111 | #endif |
4a9cbbe8 | 112 | |
4a9cbbe8 WD |
113 | /* |
114 | * Memory Controller: | |
115 | */ | |
116 | ||
117 | /* perform BR0 reset that MPC850 Rev. A can't guarantee */ | |
118 | reg = memctl->memc_br0; | |
119 | reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ | |
120 | reg |= BR_V; /* then add just the "Bank Valid" bit */ | |
121 | memctl->memc_br0 = reg; | |
122 | ||
123 | /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at | |
124 | * preliminary addresses - these have to be modified later | |
125 | * when FLASH size has been determined | |
126 | * | |
127 | * Depending on the size of the memory region defined by | |
128 | * CFG_OR0_REMAP some boards (wide address mask) allow to map the | |
129 | * CFG_MONITOR_BASE, while others (narrower address mask) can't | |
130 | * map CFG_MONITOR_BASE. | |
131 | * | |
132 | * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is | |
133 | * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000. | |
134 | * | |
135 | * If BR0 wasn't loaded with address base 0xff000000, then BR0's | |
136 | * base address remains as 0x00000000. However, the address mask | |
137 | * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped | |
138 | * into the Bank0. | |
139 | * | |
140 | * This is why CONFIG_IVMS8 and similar boards must load BR0 with | |
141 | * CFG_BR0_PRELIM in advance. | |
142 | * | |
143 | * [Thanks to Michael Liao for this explanation. | |
144 | * I owe him a free beer. - wd] | |
145 | */ | |
146 | ||
26238132 | 147 | #if defined(CONFIG_GTH) || \ |
4a9cbbe8 WD |
148 | defined(CONFIG_HERMES) || \ |
149 | defined(CONFIG_ICU862) || \ | |
150 | defined(CONFIG_IP860) || \ | |
151 | defined(CONFIG_IVML24) || \ | |
152 | defined(CONFIG_IVMS8) || \ | |
153 | defined(CONFIG_LWMON) || \ | |
154 | defined(CONFIG_MHPC) || \ | |
155 | defined(CONFIG_PCU_E) || \ | |
156 | defined(CONFIG_R360MPI) || \ | |
7e780369 | 157 | defined(CONFIG_RMU) || \ |
4a9cbbe8 WD |
158 | defined(CONFIG_RPXCLASSIC) || \ |
159 | defined(CONFIG_RPXLITE) || \ | |
b028f715 | 160 | defined(CONFIG_SPD823TS) |
4a9cbbe8 WD |
161 | |
162 | memctl->memc_br0 = CFG_BR0_PRELIM; | |
163 | #endif | |
164 | ||
165 | #if defined(CFG_OR0_REMAP) | |
166 | memctl->memc_or0 = CFG_OR0_REMAP; | |
167 | #endif | |
168 | #if defined(CFG_OR1_REMAP) | |
169 | memctl->memc_or1 = CFG_OR1_REMAP; | |
170 | #endif | |
171 | #if defined(CFG_OR5_REMAP) | |
172 | memctl->memc_or5 = CFG_OR5_REMAP; | |
173 | #endif | |
174 | ||
175 | /* now restrict to preliminary range */ | |
176 | memctl->memc_br0 = CFG_BR0_PRELIM; | |
177 | memctl->memc_or0 = CFG_OR0_PRELIM; | |
178 | ||
179 | #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) | |
180 | memctl->memc_or1 = CFG_OR1_PRELIM; | |
181 | memctl->memc_br1 = CFG_BR1_PRELIM; | |
182 | #endif | |
183 | ||
184 | #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */ | |
185 | memctl->memc_br0 = 0; | |
186 | #endif | |
187 | ||
188 | #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) | |
189 | memctl->memc_or2 = CFG_OR2_PRELIM; | |
190 | memctl->memc_br2 = CFG_BR2_PRELIM; | |
191 | #endif | |
192 | ||
193 | #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) | |
194 | memctl->memc_or3 = CFG_OR3_PRELIM; | |
195 | memctl->memc_br3 = CFG_BR3_PRELIM; | |
196 | #endif | |
197 | ||
198 | #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) | |
199 | memctl->memc_or4 = CFG_OR4_PRELIM; | |
200 | memctl->memc_br4 = CFG_BR4_PRELIM; | |
201 | #endif | |
202 | ||
203 | #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) | |
204 | memctl->memc_or5 = CFG_OR5_PRELIM; | |
205 | memctl->memc_br5 = CFG_BR5_PRELIM; | |
206 | #endif | |
207 | ||
208 | #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) | |
209 | memctl->memc_or6 = CFG_OR6_PRELIM; | |
210 | memctl->memc_br6 = CFG_BR6_PRELIM; | |
211 | #endif | |
212 | ||
213 | #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) | |
214 | memctl->memc_or7 = CFG_OR7_PRELIM; | |
215 | memctl->memc_br7 = CFG_BR7_PRELIM; | |
216 | #endif | |
217 | ||
218 | #endif /* ! CONFIG_MBX */ | |
219 | ||
220 | /* | |
221 | * Reset CPM | |
222 | */ | |
223 | immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; | |
224 | do { /* Spin until command processed */ | |
225 | __asm__ ("eieio"); | |
226 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
227 | ||
228 | #ifdef CONFIG_MBX | |
229 | /* | |
230 | * on the MBX, things are a little bit different: | |
231 | * - we need to read the VPD to get board information | |
232 | * - the plprcr is set up dynamically | |
233 | * - the memory controller is set up dynamically | |
234 | */ | |
235 | mbx_init (); | |
236 | #endif /* CONFIG_MBX */ | |
237 | ||
238 | #ifdef CONFIG_RPXCLASSIC | |
239 | rpxclassic_init (); | |
240 | #endif | |
241 | ||
e63c8ee3 WD |
242 | #if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM) |
243 | rpxlite_init (); | |
244 | #endif | |
245 | ||
4a9cbbe8 WD |
246 | #ifdef CFG_RCCR /* must be done before cpm_load_patch() */ |
247 | /* write config value */ | |
248 | immr->im_cpm.cp_rccr = CFG_RCCR; | |
249 | #endif | |
250 | ||
251 | #if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) | |
252 | cpm_load_patch (immr); /* load mpc8xx microcode patch */ | |
253 | #endif | |
254 | } | |
255 | ||
256 | /* | |
257 | * initialize higher level parts of CPU like timers | |
258 | */ | |
259 | int cpu_init_r (void) | |
260 | { | |
261 | #if defined(CFG_RTCSC) || defined(CFG_RMDS) | |
262 | DECLARE_GLOBAL_DATA_PTR; | |
263 | ||
264 | bd_t *bd = gd->bd; | |
265 | volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); | |
266 | #endif | |
267 | ||
268 | #ifdef CFG_RTCSC | |
269 | /* Unlock RTSC register */ | |
270 | immr->im_sitk.sitk_rtcsck = KAPWR_KEY; | |
271 | /* write config value */ | |
272 | immr->im_sit.sit_rtcsc = CFG_RTCSC; | |
273 | #endif | |
274 | ||
275 | #ifdef CFG_RMDS | |
276 | /* write config value */ | |
277 | immr->im_cpm.cp_rmds = CFG_RMDS; | |
278 | #endif | |
279 | return (0); | |
280 | } |