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* Patch by George G. Davis, 02 Apr 2004:
[people/ms/u-boot.git] / cpu / mpc8xx / fec.c
CommitLineData
c609719b
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <commproc.h>
27#include <net.h>
28#include <command.h>
29
30#undef ET_DEBUG
31
a6ab4bf9
WD		 32#if (CONFIG_COMMANDS & CFG_CMD_NET) && \
33 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
c609719b 34
a6ab4bf9
WD		 35/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
36#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
37#define CONFIG_ETHER_ON_FEC1 1
38#endif
39
40/* define WANT_MII when MII support is required */
41#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
42#define WANT_MII
43#else
44#undef WANT_MII
45#endif
46
47#if defined(WANT_MII)
c609719b 48#include <miiphy.h>
c609719b
WD		 49#endif
50
a6ab4bf9
WD		 51#if defined(CONFIG_RMII) && !defined(WANT_MII)
52#error RMII support is unusable without a working PHY.
53#endif
54
55#ifdef CFG_DISCOVER_PHY
56static int mii_discover_phy(struct eth_device *dev);
57#endif
58
59static struct ether_fcc_info_s
60{
61 int ether_index;
62 int fecp_offset;
63 int bd_offset;
64 int phy_addr;
65 int actual_phy_addr;
66}
67 ether_fcc_info[] = {
68#if defined(CONFIG_ETHER_ON_FEC1)
69 {
70 0,
71 offsetof(immap_t, im_cpm.cp_fec1),
72 CPM_FEC_BASE,
73#if defined(CONFIG_FEC1_PHY)
74 CONFIG_FEC1_PHY,
75#else
76 -1, /* discover */
77#endif
78 -1,
79
80 },
81#endif
82#if defined(CONFIG_ETHER_ON_FEC2)
83 {
84 1,
85 offsetof(immap_t, im_cpm.cp_fec2),
86 CPM_FEC_BASE + 0x50,
87#if defined(CONFIG_FEC2_PHY)
88 CONFIG_FEC2_PHY,
89#else
90 -1,
91#endif
92 -1,
93 },
94#endif
95};
96
c609719b
WD		 97/* Ethernet Transmit and Receive Buffers */
98#define DBUF_LENGTH 1520
99
100#define TX_BUF_CNT 2
101
102#define TOUT_LOOP 100
103
104#define PKT_MAXBUF_SIZE 1518
105#define PKT_MINBUF_SIZE 64
106#define PKT_MAXBLR_SIZE 1520
107
a6ab4bf9
WD		 108#ifdef __GNUC__
109static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
110#else
111#error txbuf must be aligned.
112#endif
c609719b
WD		 113
114static uint rxIdx; /* index of the current RX buffer */
115static uint txIdx; /* index of the current TX buffer */
116
117/*
118 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
119 * immr->udata_bd address on Dual-Port RAM
120 * Provide for Double Buffering
121 */
122
123typedef volatile struct CommonBufferDescriptor {
124 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
125 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
126} RTXBD;
127
128static RTXBD *rtx = NULL;
129
130static int fec_send(struct eth_device* dev, volatile void *packet, int length);
131static int fec_recv(struct eth_device* dev);
132static int fec_init(struct eth_device* dev, bd_t * bd);
133static void fec_halt(struct eth_device* dev);
134
135int fec_initialize(bd_t *bis)
136{
137 struct eth_device* dev;
a6ab4bf9
WD		 138 struct ether_fcc_info_s *efis;
139 int i;
c609719b 140
a6ab4bf9 141 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
c609719b 142
a6ab4bf9
WD		 143 dev = malloc(sizeof(*dev));
144 if (dev == NULL)
145 hang();
146
147 memset(dev, 0, sizeof(*dev));
148
149 /* for FEC1 make sure that the name of the interface is the same
150 as the old one for compatibility reasons */
151 if (i == 0) {
152 sprintf (dev->name, "FEC ETHERNET");
153 } else {
154 sprintf (dev->name, "FEC%d ETHERNET",
155 ether_fcc_info[i].ether_index + 1);
156 }
c609719b 157
a6ab4bf9 158 efis = &ether_fcc_info[i];
c609719b 159
a6ab4bf9
WD		 160 /*
161 * reset actual phy addr
162 */
163 efis->actual_phy_addr = -1;
164
165 dev->priv = efis;
166 dev->init = fec_init;
167 dev->halt = fec_halt;
168 dev->send = fec_send;
169 dev->recv = fec_recv;
170
171 eth_register(dev);
172 }
c609719b
WD		 173 return 1;
174}
175
176static int fec_send(struct eth_device* dev, volatile void *packet, int length)
177{
178 int j, rc;
a6ab4bf9
WD		 179 struct ether_fcc_info_s *efis = dev->priv;
180 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
c609719b
WD		 181
182 /* section 16.9.23.3
183 * Wait for ready
184 */
185 j = 0;
186 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
187 udelay(1);
188 j++;
189 }
190 if (j>=TOUT_LOOP) {
191 printf("TX not ready\n");
192 }
193
194 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
195 rtx->txbd[txIdx].cbd_datlen = length;
196 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
197 __asm__ ("eieio");
198
199 /* Activate transmit Buffer Descriptor polling */
200 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
201
202 j = 0;
203 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
204#if defined(CONFIG_ICU862)
205 udelay(10);
206#else
207 udelay(1);
208#endif
209 j++;
210 }
211 if (j>=TOUT_LOOP) {
212 printf("TX timeout\n");
213 }
214#ifdef ET_DEBUG
215 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
216 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
217 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
218#endif
219 /* return only status bits */;
220 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
221
222 txIdx = (txIdx + 1) % TX_BUF_CNT;
223
224 return rc;
225}
226
a6ab4bf9 227static int fec_recv (struct eth_device *dev)
c609719b 228{
a6ab4bf9
WD		 229 struct ether_fcc_info_s *efis = dev->priv;
230 volatile fec_t *fecp =
231 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
c609719b 232 int length;
c609719b 233
a6ab4bf9
WD		 234 for (;;) {
235 /* section 16.9.23.2 */
236 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
237 length = -1;
238 break; /* nothing received - leave for() loop */
239 }
c609719b 240
a6ab4bf9 241 length = rtx->rxbd[rxIdx].cbd_datlen;
c609719b 242
a6ab4bf9 243 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
c609719b 244#ifdef ET_DEBUG
a6ab4bf9
WD		 245 printf ("%s[%d] err: %x\n",
246 __FUNCTION__, __LINE__,
247 rtx->rxbd[rxIdx].cbd_sc);
c609719b 248#endif
a6ab4bf9
WD		 249 } else {
250 volatile uchar *rx = NetRxPackets[rxIdx];
c609719b 251
a6ab4bf9 252 length -= 4;
c609719b 253
a6ab4bf9
WD		 254#if (CONFIG_COMMANDS & CFG_CMD_CDP)
255 if ((rx[0] & 1) != 0
256 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
257 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
258 rx = NULL;
259#endif
260 /*
261 * Pass the packet up to the protocol layers.
262 */
263 if (rx != NULL)
264 NetReceive (rx, length);
265 }
c609719b 266
a6ab4bf9
WD		 267 /* Give the buffer back to the FEC. */
268 rtx->rxbd[rxIdx].cbd_datlen = 0;
269
270 /* wrap around buffer index when necessary */
271 if ((rxIdx + 1) >= PKTBUFSRX) {
272 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
273 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
274 rxIdx = 0;
275 } else {
276 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
277 rxIdx++;
278 }
279
280 __asm__ ("eieio");
c609719b 281
a6ab4bf9
WD		 282 /* Try to fill Buffer Descriptors */
283 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
284 }
c609719b 285
a6ab4bf9 286 return length;
c609719b
WD		 287}
288
289/**************************************************************
290 *
291 * FEC Ethernet Initialization Routine
292 *
293 *************************************************************/
294
295#define FEC_ECNTRL_PINMUX 0x00000004
296#define FEC_ECNTRL_ETHER_EN 0x00000002
297#define FEC_ECNTRL_RESET 0x00000001
298
299#define FEC_RCNTRL_BC_REJ 0x00000010
300#define FEC_RCNTRL_PROM 0x00000008
301#define FEC_RCNTRL_MII_MODE 0x00000004
302#define FEC_RCNTRL_DRT 0x00000002
303#define FEC_RCNTRL_LOOP 0x00000001
304
305#define FEC_TCNTRL_FDEN 0x00000004
306#define FEC_TCNTRL_HBC 0x00000002
307#define FEC_TCNTRL_GTS 0x00000001
308
309#define FEC_RESET_DELAY 50
310
a6ab4bf9
WD		 311#if defined(CONFIG_RMII)
312
313static inline void fec_10Mbps(struct eth_device *dev)
c609719b 314{
a6ab4bf9
WD		 315 struct ether_fcc_info_s *efis = dev->priv;
316 int fecidx = efis->ether_index;
317 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
c609719b 318
a6ab4bf9
WD		 319 if ((unsigned int)fecidx >= 2)
320 hang();
321
322 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask;
323}
324
325static inline void fec_100Mbps(struct eth_device *dev)
326{
327 struct ether_fcc_info_s *efis = dev->priv;
328 int fecidx = efis->ether_index;
329 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
330
331 if ((unsigned int)fecidx >= 2)
332 hang();
333
334 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
335}
336
337#endif
338
339static inline void fec_full_duplex(struct eth_device *dev)
340{
341 struct ether_fcc_info_s *efis = dev->priv;
342 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
343
344 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
345 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
346}
347
348static inline void fec_half_duplex(struct eth_device *dev)
349{
350 struct ether_fcc_info_s *efis = dev->priv;
351 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
352
353 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
354 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
355}
356
357static void fec_pin_init(int fecidx)
358{
359 DECLARE_GLOBAL_DATA_PTR;
360 bd_t *bd = gd->bd;
c609719b 361 volatile immap_t *immr = (immap_t *) CFG_IMMR;
a6ab4bf9 362 volatile fec_t *fecp;
c609719b 363
a6ab4bf9
WD		 364 /*
365 * only two FECs please
c609719b 366 */
a6ab4bf9
WD		 367 if ((unsigned int)fecidx >= 2)
368 hang();
369
370 if (fecidx == 0)
371 fecp = &immr->im_cpm.cp_fec1;
372 else
373 fecp = &immr->im_cpm.cp_fec2;
374
375 /*
376 * Set MII speed to 2.5 MHz or slightly below.
377 * * According to the MPC860T (Rev. D) Fast ethernet controller user
378 * * manual (6.2.14),
379 * * the MII management interface clock must be less than or equal
380 * * to 2.5 MHz.
381 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
382 * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
383 */
384 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
385
386#if defined(CONFIG_DUET) && defined(WANT_MII)
387 /* use MDC for MII */
388 immr->im_ioport.iop_pdpar |= 0x0080;
389 immr->im_ioport.iop_pddir &= ~0x0080;
390#endif
391
392 if (fecidx == 0) {
393#if defined(CONFIG_ETHER_ON_FEC1)
394
395#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
396
397#if !defined(CONFIG_RMII)
398
399 immr->im_ioport.iop_papar |= 0xf830;
400 immr->im_ioport.iop_padir |= 0x0830;
401 immr->im_ioport.iop_padir &= ~0xf000;
402
403 immr->im_cpm.cp_pbpar |= 0x00001001;
404 immr->im_cpm.cp_pbdir &= ~0x00001001;
405
406 immr->im_ioport.iop_pcpar |= 0x000c;
407 immr->im_ioport.iop_pcdir &= ~0x000c;
408
409 immr->im_cpm.cp_pepar |= 0x00000003;
410 immr->im_cpm.cp_pedir |= 0x00000003;
411 immr->im_cpm.cp_peso &= ~0x00000003;
412
413 immr->im_cpm.cp_cptr &= ~0x00000100;
414
415#else
416
417#if !defined(CONFIG_FEC1_PHY_NORXERR)
418 immr->im_ioport.iop_papar |= 0x1000;
419 immr->im_ioport.iop_padir &= ~0x1000;
420#endif
421 immr->im_ioport.iop_papar |= 0xe810;
422 immr->im_ioport.iop_padir |= 0x0810;
423 immr->im_ioport.iop_padir &= ~0xe000;
424
425 immr->im_cpm.cp_pbpar |= 0x00000001;
426 immr->im_cpm.cp_pbdir &= ~0x00000001;
427
428 immr->im_cpm.cp_cptr |= 0x00000100;
429 immr->im_cpm.cp_cptr &= ~0x00000050;
430
431#endif /* !CONFIG_RMII */
432
433#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
434 /*
435 * Configure all of port D for MII.
436 */
437 immr->im_ioport.iop_pdpar = 0x1fff;
438
439 /*
440 * Bits moved from Rev. D onward
441 */
442 if ((get_immr(0) & 0xffff) < 0x0501)
443 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
444 else
445 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
446#else
447 /*
448 * Configure port A for MII.
449 */
450
451#if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
452
453 /*
454 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
455 * * of CPU, so for this board we need to configure Utopia and
456 * * enable PD8 to MII-MDC function
457 */
458 immr->im_ioport.iop_pdpar |= 0x4080;
459#endif
460
461 /*
462 * Has Utopia been configured?
463 */
464 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
465 /*
466 * YES - Use MUXED mode for UTOPIA bus.
467 * This frees Port A for use by MII (see 862UM table 41-6).
468 */
469 immr->im_ioport.utmode &= ~0x80;
470 } else {
471 /*
472 * NO - set SPLIT mode for UTOPIA bus.
473 *
474 * This doesn't really effect UTOPIA (which isn't
475 * enabled anyway) but just tells the 862
476 * to use port A for MII (see 862UM table 41-6).
477 */
478 immr->im_ioport.utmode |= 0x80;
479 }
480#endif /* !defined(CONFIG_ICU862) */
481
482#endif /* CONFIG_ETHER_ON_FEC1 */
483 } else if (fecidx == 1) {
484
485#if defined(CONFIG_ETHER_ON_FEC2)
486
487#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
488
489#if !defined(CONFIG_RMII)
490
491#warning this configuration is not tested; please report if it works
492 immr->im_cpm.cp_pepar |= 0x0003fffc;
493 immr->im_cpm.cp_pedir |= 0x0003fffc;
494 immr->im_cpm.cp_peso &= ~0x000087fc;
495 immr->im_cpm.cp_peso |= 0x00037800;
496
497 immr->im_cpm.cp_cptr &= ~0x00000080;
498#else
499
500#if !defined(CONFIG_FEC2_PHY_NORXERR)
501 immr->im_cpm.cp_pepar |= 0x00000010;
502 immr->im_cpm.cp_pedir |= 0x00000010;
503 immr->im_cpm.cp_peso &= ~0x00000010;
504#endif
505 immr->im_cpm.cp_pepar |= 0x00039620;
506 immr->im_cpm.cp_pedir |= 0x00039620;
507 immr->im_cpm.cp_peso |= 0x00031000;
508 immr->im_cpm.cp_peso &= ~0x00008620;
509
510 immr->im_cpm.cp_cptr |= 0x00000080;
511 immr->im_cpm.cp_cptr &= ~0x00000028;
512#endif /* CONFIG_RMII */
513
514#endif /* CONFIG_DUET */
515
516#endif /* CONFIG_ETHER_ON_FEC2 */
517
c609719b 518 }
a6ab4bf9
WD		 519}
520
521static int fec_init (struct eth_device *dev, bd_t * bd)
522{
523 struct ether_fcc_info_s *efis = dev->priv;
524 volatile immap_t *immr = (immap_t *) CFG_IMMR;
525 volatile fec_t *fecp =
526 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
527 int i;
528
529 if (efis->ether_index == 0) {
530#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
531#if defined(CONFIG_DUET_ADS)
532 *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
533#else
534 /* configure FADS for fast (FEC) ethernet, half-duplex */
535 /* The LXT970 needs about 50ms to recover from reset, so
536 * wait for it by discovering the PHY before leaving eth_init().
537 */
538 {
539 volatile uint *bcsr4 = (volatile uint *) BCSR4;
540
541 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
542 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
543 BCSR4_FETHRST);
544
545 /* reset the LXT970 PHY */
546 *bcsr4 &= ~BCSR4_FETHRST;
547 udelay (10);
548 *bcsr4 |= BCSR4_FETHRST;
549 udelay (10);
550 }
180d3f74
WD		 551#endif /* CONFIG_DUET_ADS */
552#endif /* CONFIG_FADS */
a6ab4bf9
WD		 553 }
554
c609719b
WD		 555 /* Whack a reset.
556 * A delay is required between a reset of the FEC block and
557 * initialization of other FEC registers because the reset takes
558 * some time to complete. If you don't delay, subsequent writes
559 * to FEC registers might get killed by the reset routine which is
560 * still in progress.
561 */
562 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
563 for (i = 0;
564 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
565 ++i) {
566 udelay (1);
567 }
568 if (i == FEC_RESET_DELAY) {
569 printf ("FEC_RESET_DELAY timeout\n");
570 return 0;
571 }
572
573 /* We use strictly polling mode only
574 */
575 fecp->fec_imask = 0;
576
577 /* Clear any pending interrupt
578 */
579 fecp->fec_ievent = 0xffc0;
580
581 /* No need to set the IVEC register */
582
583 /* Set station address
584 */
585#define ea eth_get_dev()->enetaddr
a6ab4bf9
WD		 586 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
587 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
c609719b
WD		 588#undef ea
589
a6ab4bf9
WD		 590#if (CONFIG_COMMANDS & CFG_CMD_CDP)
591 /*
592 * Turn on multicast address hash table
593 */
594 fecp->fec_hash_table_high = 0xffffffff;
595 fecp->fec_hash_table_low = 0xffffffff;
596#else
c609719b
WD		 597 /* Clear multicast address hash table
598 */
599 fecp->fec_hash_table_high = 0;
a6ab4bf9
WD		 600 fecp->fec_hash_table_low = 0;
601#endif
c609719b
WD		 602
603 /* Set maximum receive buffer size.
604 */
605 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
606
607 /* Set maximum frame length
608 */
609 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
610
611 /*
612 * Setup Buffers and Buffer Desriptors
613 */
614 rxIdx = 0;
615 txIdx = 0;
616
617 if (!rtx) {
618#ifdef CFG_ALLOC_DPRAM
a6ab4bf9
WD		 619 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
620 dpram_alloc_align (sizeof (RTXBD), 8));
c609719b 621#else
a6ab4bf9 622 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
c609719b
WD		 623#endif
624 }
625 /*
626 * Setup Receiver Buffer Descriptors (13.14.24.18)
627 * Settings:
628 * Empty, Wrap
629 */
630 for (i = 0; i < PKTBUFSRX; i++) {
a6ab4bf9
WD		 631 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
632 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
c609719b
WD		 633 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
634 }
635 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
636
637 /*
638 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
639 * Settings:
640 * Last, Tx CRC
641 */
642 for (i = 0; i < TX_BUF_CNT; i++) {
a6ab4bf9
WD		 643 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
644 rtx->txbd[i].cbd_datlen = 0; /* Reset */
c609719b
WD		 645 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
646 }
647 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
648
649 /* Set receive and transmit descriptor base
650 */
651 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
652 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
653
654 /* Enable MII mode
655 */
a6ab4bf9 656#if 0 /* Full duplex mode */
c609719b
WD		 657 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
658 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
a6ab4bf9 659#else /* Half duplex mode */
c609719b
WD		 660 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
661 fecp->fec_x_cntrl = 0;
662#endif
663
664 /* Enable big endian and don't care about SDMA FC.
665 */
666 fecp->fec_fun_code = 0x78000000;
667
a6ab4bf9
WD		 668 /*
669 * Setup the pin configuration of the FEC
c609719b 670 */
a6ab4bf9 671 fec_pin_init (efis->ether_index);
c609719b 672
a6ab4bf9
WD		 673 rxIdx = 0;
674 txIdx = 0;
c609719b 675
a6ab4bf9
WD		 676 /*
677 * Now enable the transmit and receive processing
678 */
679 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
c609719b 680
a6ab4bf9
WD		 681 if (efis->phy_addr == -1) {
682#ifdef CFG_DISCOVER_PHY
c609719b 683 /*
a6ab4bf9 684 * wait for the PHY to wake up after reset
c609719b 685 */
a6ab4bf9
WD		 686 efis->actual_phy_addr = mii_discover_phy (dev);
687#else
688 efis->actual_phy_addr = -1;
689#endif
690 if (efis->actual_phy_addr == -1) {
691 printf ("Unable to discover phy!\n");
692 return 0;
693 }
c609719b 694 } else {
a6ab4bf9 695 efis->actual_phy_addr = efis->phy_addr;
c609719b 696 }
a6ab4bf9
WD		 697#if defined(CONFIG_MII) && defined(CONFIG_RMII)
698 /*
699 * adapt the RMII speed to the speed of the phy
c609719b 700 */
a6ab4bf9
WD		 701 if (miiphy_speed (efis->actual_phy_addr) == _100BASET) {
702 fec_100Mbps (dev);
703 } else {
704 fec_10Mbps (dev);
705 }
706#endif
c609719b 707
a6ab4bf9
WD		 708#if defined(CONFIG_MII)
709 /*
710 * adapt to the half/full speed settings
c609719b 711 */
a6ab4bf9
WD		 712 if (miiphy_duplex (efis->actual_phy_addr) == FULL) {
713 fec_full_duplex (dev);
714 } else {
715 fec_half_duplex (dev);
716 }
c609719b
WD		 717#endif
718
719 /* And last, try to fill Rx Buffer Descriptors */
a6ab4bf9 720 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
c609719b
WD		 721
722 return 1;
723}
724
725
c609719b
WD		 726static void fec_halt(struct eth_device* dev)
727{
728#if 0
a6ab4bf9
WD		 729 volatile immap_t *immr = (immap_t *)CFG_IMMR;
730 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
c609719b
WD		 731#endif
732}
733
734#if 0
735void restart(void)
736{
a6ab4bf9
WD		 737 volatile immap_t *immr = (immap_t *)CFG_IMMR;
738 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
c609719b
WD		 739}
740#endif
741
a6ab4bf9 742#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
c609719b
WD		 743
744/* Make MII read/write commands for the FEC.
745*/
746
747#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
748 (REG & 0x1f) << 18))
749
750#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
751 (REG & 0x1f) << 18) | \
752 (VAL & 0xffff))
753
754/* Interrupt events/masks.
755*/
756#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
757#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
758#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
759#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
760#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
761#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
762#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
763#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
764#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
765#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
766
767/* PHY identification
768 */
769#define PHY_ID_LXT970 0x78100000 /* LXT970 */
770#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
771#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
772#define PHY_ID_QS6612 0x01814400 /* QS6612 */
773#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
774#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
775#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
180d3f74 776#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
c609719b
WD		 777
778/* send command to phy using mii, wait for result */
779static uint
780mii_send(uint mii_cmd)
781{
782 uint mii_reply;
783 volatile fec_t *ep;
784
785 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
786
787 ep->fec_mii_data = mii_cmd; /* command to phy */
788
789 /* wait for mii complete */
790 while (!(ep->fec_ievent & FEC_ENET_MII))
791 ; /* spin until done */
792 mii_reply = ep->fec_mii_data; /* result from phy */
793 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
794#if 0
795 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
796 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
797#endif
798 return (mii_reply & 0xffff); /* data read from phy */
799}
800#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
801
802#if defined(CFG_DISCOVER_PHY)
a6ab4bf9 803static int mii_discover_phy(struct eth_device *dev)
c609719b
WD		 804{
805#define MAX_PHY_PASSES 11
806 uint phyno;
807 int pass;
a6ab4bf9
WD		 808 uint phytype;
809 int phyaddr;
c609719b
WD		 810
811 phyaddr = -1; /* didn't find a PHY yet */
812 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
813 if (pass > 1) {
814 /* PHY may need more time to recover from reset.
815 * The LXT970 needs 50ms typical, no maximum is
816 * specified, so wait 10ms before try again.
817 * With 11 passes this gives it 100ms to wake up.
818 */
819 udelay(10000); /* wait 10ms */
820 }
821 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
822 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
823#ifdef ET_DEBUG
824 printf("PHY type 0x%x pass %d type ", phytype, pass);
825#endif
826 if (phytype != 0xffff) {
827 phyaddr = phyno;
828 phytype <<= 16;
829 phytype |= mii_send(mk_mii_read(phyno,
830 PHY_PHYIDR2));
831
832#ifdef ET_DEBUG
833 printf("PHY @ 0x%x pass %d type ",phyno,pass);
834 switch (phytype & 0xfffffff0) {
835 case PHY_ID_LXT970:
836 printf("LXT970\n");
837 break;
838 case PHY_ID_LXT971:
839 printf("LXT971\n");
840 break;
841 case PHY_ID_82555:
842 printf("82555\n");
843 break;
844 case PHY_ID_QS6612:
845 printf("QS6612\n");
846 break;
847 case PHY_ID_AMD79C784:
848 printf("AMD79C784\n");
849 break;
850 case PHY_ID_LSI80225B:
851 printf("LSI L80225/B\n");
852 break;
180d3f74
WD		 853 case PHY_ID_DM9161:
854 printf("Davicom DM9161\n");
855 break;
c609719b
WD		 856 default:
857 printf("0x%08x\n", phytype);
858 break;
859 }
860#endif
861 }
862 }
863 }
864 if (phyaddr < 0) {
865 printf("No PHY device found.\n");
866 }
a6ab4bf9 867 return phyaddr;
c609719b
WD		 868}
869#endif /* CFG_DISCOVER_PHY */
870
a6ab4bf9 871#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
c609719b
WD		 872
873static int mii_init_done = 0;
874
875/****************************************************************************
876 * mii_init -- Initialize the MII for MII command without ethernet
877 * This function is a subset of eth_init
878 ****************************************************************************
879 */
880void mii_init (void)
881{
c609719b
WD		 882 volatile immap_t *immr = (immap_t *) CFG_IMMR;
883 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
a6ab4bf9 884 int i, j;
c609719b
WD		 885
886 if (mii_init_done != 0) {
887 return;
888 }
889
a6ab4bf9
WD		 890 for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
891
c609719b
WD		 892 /* Whack a reset.
893 * A delay is required between a reset of the FEC block and
894 * initialization of other FEC registers because the reset takes
895 * some time to complete. If you don't delay, subsequent writes
896 * to FEC registers might get killed by the reset routine which is
897 * still in progress.
898 */
899
900 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
901 for (i = 0;
902 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
903 ++i) {
904 udelay (1);
905 }
906 if (i == FEC_RESET_DELAY) {
907 printf ("FEC_RESET_DELAY timeout\n");
908 return;
909 }
910
911 /* We use strictly polling mode only
912 */
913 fecp->fec_imask = 0;
914
915 /* Clear any pending interrupt
916 */
917 fecp->fec_ievent = 0xffc0;
918
a6ab4bf9 919 /* Setup the pin configuration of the FEC(s)
c609719b 920 */
a6ab4bf9 921 fec_pin_init(ether_fcc_info[i].ether_index);
c609719b 922
c609719b
WD		 923 /* Now enable the transmit and receive processing
924 */
925 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
a6ab4bf9 926 }
c609719b
WD		 927
928 mii_init_done = 1;
929}
a6ab4bf9 930
c609719b
WD		 931/*****************************************************************************
932 * Read and write a MII PHY register, routines used by MII Utilities
933 *
934 * FIXME: These routines are expected to return 0 on success, but mii_send
935 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
936 * no PHY connected...
937 * For now always return 0.
938 * FIXME: These routines only work after calling eth_init() at least once!
939 * Otherwise they hang in mii_send() !!! Sorry!
940 *****************************************************************************/
941
942int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
943{
944 short rdreg; /* register working value */
945
946#ifdef MII_DEBUG
947 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
948#endif
949 rdreg = mii_send(mk_mii_read(addr, reg));
950
951 *value = rdreg;
c609719b
WD		 952#ifdef MII_DEBUG
953 printf ("0x%04x\n", *value);
954#endif
c609719b
WD		 955 return 0;
956}
957
958int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
959{
960 short rdreg; /* register working value */
c609719b
WD		 961#ifdef MII_DEBUG
962 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
963#endif
c609719b
WD		 964 rdreg = mii_send(mk_mii_write(addr, reg, value));
965
966#ifdef MII_DEBUG
967 printf ("0x%04x\n", value);
968#endif
c609719b
WD		 969 return 0;
970}
971#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
972
973#endif /* CFG_CMD_NET, FEC_ENET */
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