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ed247f48
WD		 1/*
2 * File: scc.c
3 * Description:
4 * Basic ET HW initialization and packet RX/TX routines
5 *
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
8 */
9
10/*
11 * MPC823 <-> MC68160 Connections:
12 *
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
15 *
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
25 *
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
32 *
33 */
34
35#include <common.h>
36#include <malloc.h>
37#include <commproc.h>
38#include <net.h>
39#include <command.h>
40
41#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
42
43/* Ethernet Transmit and Receive Buffers */
44#define DBUF_LENGTH 1520
45
46#define TX_BUF_CNT 2
47
48#define TOUT_LOOP 100
49
50static char txbuf[DBUF_LENGTH];
51
52static uint rxIdx; /* index of the current RX buffer */
53static uint txIdx; /* index of the current TX buffer */
54
55/*
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
59 */
60
61typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
64} RTXBD;
65
66static RTXBD *rtx;
67
68static int scc_send(struct eth_device* dev, volatile void *packet, int length);
69static int scc_recv(struct eth_device* dev);
70static int scc_init (struct eth_device* dev, bd_t * bd);
71static void scc_halt(struct eth_device* dev);
72
73int scc_initialize(bd_t *bis)
74{
75 struct eth_device* dev;
76
77 dev = (struct eth_device*) malloc(sizeof *dev);
7f6c2cbc 78 memset(dev, 0, sizeof *dev);
ed247f48
WD		 79
80 sprintf(dev->name, "SCC ETHERNET");
81 dev->iobase = 0;
82 dev->priv = 0;
83 dev->init = scc_init;
84 dev->halt = scc_halt;
85 dev->send = scc_send;
86 dev->recv = scc_recv;
87
88 eth_register(dev);
89
90 return 1;
91}
92
93static int scc_send(struct eth_device* dev, volatile void *packet, int length)
94{
95 int i, j=0;
96#if 0
97 volatile char *in, *out;
98#endif
99
100 /* section 16.9.23.3
101 * Wait for ready
102 */
103#if 0
104 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
105 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
106 in = packet;
107 for(i = 0; i < length; i++) {
108 *out++ = *in++;
109 }
110 rtx->txbd[txIdx].cbd_datlen = length;
111 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
112 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
113
114#ifdef ET_DEBUG
115 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
116#endif
117 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
118
119 /* wrap around buffer index when necessary */
120 if (txIdx >= TX_BUF_CNT) txIdx = 0;
121#endif
122
123 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
124 udelay (1); /* will also trigger Wd if needed */
125 j++;
126 }
127 if (j>=TOUT_LOOP) printf("TX not ready\n");
128 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
129 rtx->txbd[txIdx].cbd_datlen = length;
130 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
131 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
132 udelay (1); /* will also trigger Wd if needed */
133 j++;
134 }
135 if (j>=TOUT_LOOP) printf("TX timeout\n");
136#ifdef ET_DEBUG
137 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
138#endif
139 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
140 return i;
141}
142
3bbc899f 143static int scc_recv (struct eth_device *dev)
ed247f48
WD		 144{
145 int length;
146
3bbc899f
WD		 147 for (;;) {
148 /* section 16.9.23.2 */
149 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
150 length = -1;
151 break; /* nothing received - leave for() loop */
152 }
ed247f48 153
3bbc899f 154 length = rtx->rxbd[rxIdx].cbd_datlen;
ed247f48 155
3bbc899f 156 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
ed247f48 157#ifdef ET_DEBUG
3bbc899f 158 printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
ed247f48 159#endif
3bbc899f
WD		 160 } else {
161 /* Pass the packet up to the protocol layers. */
162 NetReceive (NetRxPackets[rxIdx], length - 4);
163 }
164
165
166 /* Give the buffer back to the SCC. */
167 rtx->rxbd[rxIdx].cbd_datlen = 0;
168
169 /* wrap around buffer index when necessary */
170 if ((rxIdx + 1) >= PKTBUFSRX) {
171 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
172 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
173 rxIdx = 0;
174 } else {
175 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
176 rxIdx++;
177 }
ed247f48 178 }
3bbc899f 179 return length;
ed247f48
WD		 180}
181
182/**************************************************************
183 *
184 * SCC Ethernet Initialization Routine
185 *
186 *************************************************************/
187
3bbc899f 188static int scc_init (struct eth_device *dev, bd_t * bis)
ed247f48
WD		 189{
190
3bbc899f
WD		 191 int i;
192 scc_enet_t *pram_ptr;
ed247f48 193
3bbc899f 194 volatile immap_t *immr = (immap_t *) CFG_IMMR;
ed247f48 195
2535d602
WD		 196#ifdef CONFIG_FADS
197#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
3bbc899f
WD		 198 /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
199 *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
200 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
201 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
ed247f48 202#else
3bbc899f
WD		 203 *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
204 *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
205 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
ed247f48
WD		 206#endif
207#endif
208
3bbc899f 209 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
ed247f48 210
3bbc899f
WD		 211 rxIdx = 0;
212 txIdx = 0;
ed247f48
WD		 213
214#ifdef CFG_ALLOC_DPRAM
3bbc899f
WD		 215 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
216 dpram_alloc_align (sizeof (RTXBD), 8));
ed247f48 217#else
3bbc899f
WD		 218 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
219#endif /* 0 */
ed247f48
WD		 220
221#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
3bbc899f
WD		 222 /* Configure port A pins for Txd and Rxd.
223 */
224 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
225 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
226 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
ed247f48 227#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
3bbc899f
WD		 228 /* Configure port B pins for Txd and Rxd.
229 */
230 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
231 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
232 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
ed247f48
WD		 233#else
234#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
235#endif
236
237#if defined(PC_ENET_LBK)
3bbc899f
WD		 238 /* Configure port C pins to disable External Loopback
239 */
240 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
241 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
242 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
243 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
244#endif /* PC_ENET_LBK */
245
246 /* Configure port C pins to enable CLSN and RENA.
247 */
248 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
249 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
250 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
251
252 /* Configure port A for TCLK and RCLK.
253 */
254 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
255 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
256
257 /*
258 * Configure Serial Interface clock routing -- see section 16.7.5.3
259 * First, clear all SCC bits to zero, then set the ones we want.
260 */
261
262 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
263 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
264
265
266 /*
267 * Initialize SDCR -- see section 16.9.23.7
268 * SDMA configuration register
269 */
270 immr->im_siu_conf.sc_sdcr = 0x01;
271
272
273 /*
274 * Setup SCC Ethernet Parameter RAM
275 */
276
277 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
278 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
279
280 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
281
282 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
283 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
284
285 /*
286 * Setup Receiver Buffer Descriptors (13.14.24.18)
287 * Settings:
288 * Empty, Wrap
289 */
290
291 for (i = 0; i < PKTBUFSRX; i++) {
292 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
293 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
294 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
295 }
296
297 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
298
299 /*
300 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
301 * Settings:
302 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
303 */
304
305 for (i = 0; i < TX_BUF_CNT; i++) {
306 rtx->txbd[i].cbd_sc =
307 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
308 rtx->txbd[i].cbd_datlen = 0; /* Reset */
309 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
310 }
311
312 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
313
314 /*
315 * Enter Command: Initialize Rx Params for SCC
316 */
317
318 do { /* Spin until ready to issue command */
319 __asm__ ("eieio");
320 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
321 /* Issue command */
322 immr->im_cpm.cp_cpcr =
323 ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
324 do { /* Spin until command processed */
325 __asm__ ("eieio");
326 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
327
328 /*
329 * Ethernet Specific Parameter RAM
330 * see table 13-16, pg. 660,
331 * pg. 681 (example with suggested settings)
332 */
333
334 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
335 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
336 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
337 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
338 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
339 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
340
341 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
342 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
343 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
344
345 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
346 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
347
348 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
349 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
350 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
351 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
ed247f48
WD		 352
353#define ea eth_get_dev()->enetaddr
3bbc899f
WD		 354 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
355 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
356 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
ed247f48
WD		 357#undef ea
358
3bbc899f
WD		 359 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
360 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
361 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
362 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
363 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
364 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
365 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
366 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
367
368 /*
369 * Enter Command: Initialize Tx Params for SCC
370 */
371
372 do { /* Spin until ready to issue command */
373 __asm__ ("eieio");
374 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
375 /* Issue command */
376 immr->im_cpm.cp_cpcr =
377 ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
378 do { /* Spin until command processed */
379 __asm__ ("eieio");
380 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
381
382 /*
383 * Mask all Events in SCCM - we use polling mode
384 */
385 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
386
387 /*
388 * Clear Events in SCCE -- Clear bits by writing 1's
389 */
390
391 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
392
393
394 /*
395 * Initialize GSMR High 32-Bits
396 * Settings: Normal Mode
397 */
398
399 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
400
401 /*
402 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
403 * Settings:
404 * TCI = Invert
405 * TPL = 48 bits
406 * TPP = Repeating 10's
407 * MODE = Ethernet
408 */
409
410 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
411 SCC_GSMRL_TPL_48 |
412 SCC_GSMRL_TPP_10 |
413 SCC_GSMRL_MODE_ENET);
414
415 /*
416 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
417 */
418
419 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
420
421 /*
422 * Initialize the PSMR
423 * Settings:
424 * CRC = 32-Bit CCITT
425 * NIB = Begin searching for SFD 22 bits after RENA
426 * FDE = Full Duplex Enable
427 * LPB = Loopback Enable (Needed when FDE is set)
428 * BRO = Reject broadcast packets
429 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
430 */
431 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
432 SCC_PSMR_NIB22 |
ed247f48 433#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
3bbc899f 434 SCC_PSMR_FDE | SCC_PSMR_LPB |
ed247f48
WD		 435#endif
436#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
3bbc899f 437 SCC_PSMR_BRO |
ed247f48
WD		 438#endif
439#if defined(CONFIG_SCC_ENET_PROMISCOUS)
3bbc899f 440 SCC_PSMR_PRO |
ed247f48 441#endif
3bbc899f 442 0;
ed247f48 443
3bbc899f
WD		 444 /*
445 * Configure Ethernet TENA Signal
446 */
ed247f48
WD		 447
448#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
3bbc899f
WD		 449 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
450 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
ed247f48 451#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
3bbc899f
WD		 452 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
453 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
ed247f48
WD		 454#else
455#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
456#endif
457
458#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
3bbc899f
WD		 459 /*
460 * Port C is used to control the PHY,MC68160.
461 */
462 immr->im_ioport.iop_pcdir |=
463 (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
ed247f48 464
3bbc899f
WD		 465 immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
466 immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
467 *((uint *) BCSR1) &= ~BCSR1_ETHEN;
468#endif /* MPC860ADS */
ed247f48
WD		 469
470#if defined(CONFIG_AMX860)
3bbc899f
WD		 471 /*
472 * Port B is used to control the PHY,MC68160.
473 */
474 immr->im_cpm.cp_pbdir |=
475 (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
ed247f48 476
3bbc899f
WD		 477 immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
478 immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
ed247f48 479
3bbc899f
WD		 480 immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
481 immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
482#endif /* AMX860 */
ed247f48
WD		 483
484#ifdef CONFIG_RPXCLASSIC
3bbc899f
WD		 485 *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
486 *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
ed247f48
WD		 487#endif
488
489#ifdef CONFIG_RPXLITE
3bbc899f 490 *((uchar *) BCSR0) |= BCSR0_ETHEN;
ed247f48
WD		 491#endif
492
3bbc899f
WD		 493#if defined(CONFIG_QS860T)
494 /*
495 * PB27=FDE-, set output low for full duplex
496 * PB26=Link Test Enable, normally high output
497 */
498 immr->im_cpm.cp_pbdir |= 0x00000030;
499 immr->im_cpm.cp_pbdat |= 0x00000020;
500 immr->im_cpm.cp_pbdat &= ~0x00000010;
501#endif /* QS860T */
502
ed247f48 503#ifdef CONFIG_MBX
3bbc899f 504 board_ether_init ();
ed247f48
WD		 505#endif
506
507#if defined(CONFIG_NETVIA)
993cad93 508#if defined(PA_ENET_PDN)
3bbc899f
WD		 509 immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
510 immr->im_ioport.iop_padir |= PA_ENET_PDN;
511 immr->im_ioport.iop_padat |= PA_ENET_PDN;
993cad93 512#elif defined(PB_ENET_PDN)
3bbc899f
WD		 513 immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
514 immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
515 immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
ed247f48 516#elif defined(PC_ENET_PDN)
3bbc899f
WD		 517 immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
518 immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
519 immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
993cad93 520#elif defined(PD_ENET_PDN)
3bbc899f
WD		 521 immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
522 immr->im_ioport.iop_pddir |= PD_ENET_PDN;
523 immr->im_ioport.iop_pddat |= PD_ENET_PDN;
ed247f48
WD		 524#endif
525#endif
526
3bbc899f
WD		 527 /*
528 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
529 */
ed247f48 530
3bbc899f
WD		 531 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
532 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
ed247f48 533
3bbc899f
WD		 534 /*
535 * Work around transmit problem with first eth packet
536 */
ed247f48 537#if defined (CONFIG_FADS)
3bbc899f 538 udelay (10000); /* wait 10 ms */
ed247f48 539#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
3bbc899f 540 udelay (100000); /* wait 100 ms */
ed247f48
WD		 541#endif
542
3bbc899f 543 return 1;
ed247f48
WD		 544}
545
546
3bbc899f 547static void scc_halt (struct eth_device *dev)
ed247f48 548{
3bbc899f
WD		 549 volatile immap_t *immr = (immap_t *) CFG_IMMR;
550
551 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
552 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
ed247f48
WD		 553}
554
555#if 0
3bbc899f 556void restart (void)
ed247f48 557{
3bbc899f
WD		 558 volatile immap_t *immr = (immap_t *) CFG_IMMR;
559
560 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
561 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
ed247f48
WD		 562}
563#endif
ed247f48 564#endif /* CFG_CMD_NET, SCC_ENET */
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