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* Add support for USB Mass Storage Devices (BBB)
[people/ms/u-boot.git] / cpu / ppc4xx / 405gp_enet.c
CommitLineData
c609719b
WD		 1/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*/
71
72#include <common.h>
73#include <asm/processor.h>
74#include <ppc4xx.h>
75#include <commproc.h>
76#include <405gp_enet.h>
77#include <405_mal.h>
78#include <miiphy.h>
79#include <net.h>
80#include <malloc.h>
81#include "vecnum.h"
82
b867d705 83#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
c609719b
WD		 84
85#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
149dded2 86#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
c609719b
WD		 87
88#define NUM_TX_BUFF 1
89/* AS.HARNOIS
90 * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
91 * These both variables are used to define the same thing!
92 * #define NUM_RX_BUFF 4
93 */
94#define NUM_RX_BUFF PKTBUFSRX
95
96/* Ethernet Transmit and Receive Buffers */
97/* AS.HARNOIS
98 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
99 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
100 */
101#define ENET_MAX_MTU PKTSIZE
102#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
103
104static char *txbuf_ptr;
105
106/* define the number of channels implemented */
107#define EMAC_RXCHL 1
108#define EMAC_TXCHL 1
109
110/*-----------------------------------------------------------------------------+
111 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
112 * Interrupt Controller).
113 *-----------------------------------------------------------------------------*/
114#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
115#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
116#define EMAC_UIC_DEF UIC_ENET
117
118/*-----------------------------------------------------------------------------+
119 * Global variables. TX and RX descriptors and buffers.
120 *-----------------------------------------------------------------------------*/
121static volatile mal_desc_t *tx;
122static volatile mal_desc_t *rx;
123static mal_desc_t *alloc_tx_buf = NULL;
124static mal_desc_t *alloc_rx_buf = NULL;
125
126/* IER globals */
127static unsigned long emac_ier;
128static unsigned long mal_ier;
129
130
131/* Statistic Areas */
132#define MAX_ERR_LOG 10
133struct emac_stats {
134 int data_len_err;
135 int rx_frames;
136 int rx;
137 int rx_prot_err;
138};
139
140static struct stats { /* Statistic Block */
141 struct emac_stats emac;
142 int int_err;
143 short tx_err_log[MAX_ERR_LOG];
144 short rx_err_log[MAX_ERR_LOG];
145} stats;
146
147static int first_init = 0;
148
149static int tx_err_index = 0; /* Transmit Error Index for tx_err_log */
150static int rx_err_index = 0; /* Receive Error Index for rx_err_log */
151
152static int rx_slot = 0; /* MAL Receive Slot */
153static int rx_i_index = 0; /* Receive Interrupt Queue Index */
154static int rx_u_index = 0; /* Receive User Queue Index */
155static int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
156
157static int tx_slot = 0; /* MAL Transmit Slot */
158static int tx_i_index = 0; /* Transmit Interrupt Queue Index */
159static int tx_u_index = 0; /* Transmit User Queue Index */
160static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
161
162#undef INFO_405_ENET 1
163#ifdef INFO_405_ENET
164static int packetSent = 0;
165static int packetReceived = 0;
166static int packetHandled = 0;
167#endif
168
169static char emac_hwd_addr[ENET_ADDR_LENGTH];
170
171static bd_t *bis_save = NULL; /* for eth_init upon mal error */
172
173static int is_receiving = 0; /* sync with eth interrupt */
174static int print_speed = 1; /* print speed message upon start */
175
c609719b
WD		 176/*-----------------------------------------------------------------------------+
177 * Prototypes and externals.
178 *-----------------------------------------------------------------------------*/
a3ed3996
WD		 179static void enet_rcv (unsigned long malisr);
180static int enetInt(void);
181static void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
c609719b 182 unsigned long mal_errr);
a3ed3996 183static void emac_err (unsigned long isr);
c609719b 184
a3ed3996 185static void ppc_4xx_eth_halt (struct eth_device *dev)
c609719b
WD		 186{
187 mtdcr (malier, 0x00000000); /* disable mal interrupts */
188 out32 (EMAC_IER, 0x00000000); /* disable emac interrupts */
189
190 /* 1st reset MAL */
191 mtdcr (malmcr, MAL_CR_MMSR);
192
193 /* wait for reset */
194 while (mfdcr (malmcr) & MAL_CR_MMSR) {
195 };
196
197 /* EMAC RESET */
198 out32 (EMAC_M0, EMAC_M0_SRST);
199
200 print_speed = 1; /* print speed message again next time */
201}
202
203
a3ed3996 204static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
c609719b
WD		 205{
206 int i;
207 unsigned long reg;
208 unsigned long msr;
209 unsigned long speed;
210 unsigned long duplex;
211 unsigned mode_reg;
212 unsigned short reg_short;
213
214 msr = mfmsr ();
215 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
216
217#ifdef INFO_405_ENET
218 /* AS.HARNOIS
219 * We should have :
220 * packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
8bde7f77
WD		 221 * In the most cases packetHandled = packetReceived, but it
222 * is possible that new packets (without relationship with
223 * current transfer) have got the time to arrived before
224 * netloop calls eth_halt
c609719b
WD		 225 */
226 printf ("About preceeding transfer:\n"
227 "- Sent packet number %d\n"
228 "- Received packet number %d\n"
229 "- Handled packet number %d\n",
230 packetSent, packetReceived, packetHandled);
231 packetSent = 0;
232 packetReceived = 0;
233 packetHandled = 0;
234#endif
235
236 /* MAL RESET */
237 mtdcr (malmcr, MAL_CR_MMSR);
238 /* wait for reset */
239 while (mfdcr (malmcr) & MAL_CR_MMSR) {
240 };
241
242 tx_err_index = 0; /* Transmit Error Index for tx_err_log */
243 rx_err_index = 0; /* Receive Error Index for rx_err_log */
244
245 rx_slot = 0; /* MAL Receive Slot */
246 rx_i_index = 0; /* Receive Interrupt Queue Index */
247 rx_u_index = 0; /* Receive User Queue Index */
248
249 tx_slot = 0; /* MAL Transmit Slot */
250 tx_i_index = 0; /* Transmit Interrupt Queue Index */
251 tx_u_index = 0; /* Transmit User Queue Index */
252
253#if defined(CONFIG_440)
8bde7f77
WD		 254 /* set RMII mode */
255 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
c609719b
WD		 256#endif /* CONFIG_440 */
257
258 /* EMAC RESET */
259 out32 (EMAC_M0, EMAC_M0_SRST);
260
261 /* wait for PHY to complete auto negotiation */
262 reg_short = 0;
263#ifndef CONFIG_CS8952_PHY
264 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
265
266 /*
267 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
268 */
269 if ((reg_short & PHY_BMSR_AUTN_ABLE)
270 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
271 puts ("Waiting for PHY auto negotiation to complete");
272 i = 0;
273 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
c609719b
WD		 274 /*
275 * Timeout reached ?
276 */
149dded2 277 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
c609719b
WD		 278 puts (" TIMEOUT !\n");
279 break;
280 }
149dded2
WD		 281
282 if ((i++ % 1000) == 0)
283 putc ('.');
284 udelay (1000); /* 1 ms */
285 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
c609719b
WD		 286 }
287 puts (" done\n");
288 udelay (500000); /* another 500 ms (results in faster booting) */
289 }
290#endif
291 speed = miiphy_speed (CONFIG_PHY_ADDR);
292 duplex = miiphy_duplex (CONFIG_PHY_ADDR);
293 if (print_speed) {
294 print_speed = 0;
295 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
296 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
297 }
298
299 /* set the Mal configuration reg */
300#if defined(CONFIG_440)
301 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
302 if( get_pvr() == PVR_440GP_RB )
303 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
304 else
305#else
306 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
307#endif
308
309 /* Free "old" buffers */
310 if (alloc_tx_buf) free(alloc_tx_buf);
311 if (alloc_rx_buf) free(alloc_rx_buf);
312
313 /*
314 * Malloc MAL buffer desciptors, make sure they are
315 * aligned on cache line boundary size
316 * (401/403/IOP480 = 16, 405 = 32)
317 * and doesn't cross cache block boundaries.
318 */
319 alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
320 ((2 * CFG_CACHELINE_SIZE) - 2));
321 if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
322 tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
323 ((int)alloc_tx_buf & CACHELINE_MASK));
324 } else {
325 tx = alloc_tx_buf;
326 }
327
328 alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
329 ((2 * CFG_CACHELINE_SIZE) - 2));
330 if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
331 rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
332 ((int)alloc_rx_buf & CACHELINE_MASK));
333 } else {
334 rx = alloc_rx_buf;
335 }
336
337 for (i = 0; i < NUM_TX_BUFF; i++) {
338 tx[i].ctrl = 0;
339 tx[i].data_len = 0;
340 if (first_init == 0)
341 txbuf_ptr = (char *) malloc (ENET_MAX_MTU_ALIGNED);
342 tx[i].data_ptr = txbuf_ptr;
343 if ((NUM_TX_BUFF - 1) == i)
344 tx[i].ctrl |= MAL_TX_CTRL_WRAP;
345 tx_run[i] = -1;
346#if 0
347 printf ("TX_BUFF %d @ 0x%08lx\n", i, (ulong) tx[i].data_ptr);
348#endif
349 }
350
351 for (i = 0; i < NUM_RX_BUFF; i++) {
352 rx[i].ctrl = 0;
353 rx[i].data_len = 0;
354 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
355 rx[i].data_ptr = (char *) NetRxPackets[i];
356 if ((NUM_RX_BUFF - 1) == i)
357 rx[i].ctrl |= MAL_RX_CTRL_WRAP;
358 rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
359 rx_ready[i] = -1;
360#if 0
361 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
362#endif
363 }
364
365 memcpy (emac_hwd_addr, bis->bi_enetaddr, ENET_ADDR_LENGTH);
366
367 reg = 0x00000000;
368
369 reg |= emac_hwd_addr[0]; /* set high address */
370 reg = reg << 8;
371 reg |= emac_hwd_addr[1];
372
373 out32 (EMAC_IAH, reg);
374
375 reg = 0x00000000;
376 reg |= emac_hwd_addr[2]; /* set low address */
377 reg = reg << 8;
378 reg |= emac_hwd_addr[3];
379 reg = reg << 8;
380 reg |= emac_hwd_addr[4];
381 reg = reg << 8;
382 reg |= emac_hwd_addr[5];
383
384 out32 (EMAC_IAL, reg);
385
386 /* setup MAL tx & rx channel pointers */
387 mtdcr (maltxctp0r, tx);
388 mtdcr (malrxctp0r, rx);
389
390 /* Reset transmit and receive channels */
391 mtdcr (malrxcarr, 0x80000000); /* 2 channels */
392 mtdcr (maltxcarr, 0x80000000); /* 2 channels */
393
394 /* Enable MAL transmit and receive channels */
395 mtdcr (maltxcasr, 0x80000000); /* 1 channel */
396 mtdcr (malrxcasr, 0x80000000); /* 1 channel */
397
398 /* set RX buffer size */
399 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
400
401 /* set transmit enable & receive enable */
402 out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
403
404 /* set receive fifo to 4k and tx fifo to 2k */
405 mode_reg = EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
406
407 /* set speed */
408 if (speed == _100BASET)
409 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
410 else
411 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
412 if (duplex == FULL)
413 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
414
415 out32 (EMAC_M1, mode_reg);
416
417 /* Enable broadcast and indvidual address */
418 out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
419 /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
420
421 /* we probably need to set the tx mode1 reg? maybe at tx time */
422
423 /* set transmit request threshold register */
424 out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
425
426 /* set receive low/high water mark register */
427#if defined(CONFIG_440)
428 /* 440GP has a 64 byte burst length */
8bde7f77
WD		 429 out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
430 out32 (EMAC_TXM1, 0xf8640000);
c609719b
WD		 431#else /* CONFIG_440 */
432 /* 405s have a 16 byte burst length */
433 out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
434#endif /* CONFIG_440 */
435
436 /* Frame gap set */
437 out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
438
439 if (first_init == 0) {
440 /*
441 * Connect interrupt service routines
442 */
443 irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
444 irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
445 irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
446 irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
447 irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
448 irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
449 irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
450 }
451
452 /* set up interrupt handler */
453 /* setup interrupt controler to take interrupts from the MAL &
454 EMAC */
455 mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
456 mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
457
458 /* set the MAL IER ??? names may change with new spec ??? */
459 mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
460 MAL_IER_PLBE;
461 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
462 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
463 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
464 mtdcr (malier, mal_ier);
465
466 /* Set EMAC IER */
467 emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
468 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
469 if (speed == _100BASET)
470 emac_ier = emac_ier | EMAC_ISR_SYE;
471
472 out32 (EMAC_ISR, 0xffffffff); /* clear pending interrupts */
473 out32 (EMAC_IER, emac_ier);
474
475 mtmsr (msr); /* enable interrupts again */
476
477 bis_save = bis;
478 first_init = 1;
479
a3ed3996 480 return (1);
c609719b
WD		 481}
482
483
a3ed3996 484static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
c609719b
WD		 485{
486 struct enet_frame *ef_ptr;
487 ulong time_start, time_now;
488 unsigned long temp_txm0;
489
490 ef_ptr = (struct enet_frame *) ptr;
491
492 /*-----------------------------------------------------------------------+
493 * Copy in our address into the frame.
494 *-----------------------------------------------------------------------*/
495 (void) memcpy (ef_ptr->source_addr, emac_hwd_addr, ENET_ADDR_LENGTH);
496
497 /*-----------------------------------------------------------------------+
498 * If frame is too long or too short, modify length.
499 *-----------------------------------------------------------------------*/
500 if (len > ENET_MAX_MTU)
501 len = ENET_MAX_MTU;
502
503 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
504 memcpy ((void *) txbuf_ptr, (const void *) ptr, len);
505
506 /*-----------------------------------------------------------------------+
507 * set TX Buffer busy, and send it
508 *-----------------------------------------------------------------------*/
509 tx[tx_slot].ctrl = (MAL_TX_CTRL_LAST |
510 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
511 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
512 if ((NUM_TX_BUFF - 1) == tx_slot)
513 tx[tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
514
515 tx[tx_slot].data_len = (short) len;
516 tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
517
518 __asm__ volatile ("eieio");
519 out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
520#ifdef INFO_405_ENET
521 packetSent++;
522#endif
523
524 /*-----------------------------------------------------------------------+
525 * poll unitl the packet is sent and then make sure it is OK
526 *-----------------------------------------------------------------------*/
527 time_start = get_timer (0);
528 while (1) {
529 temp_txm0 = in32 (EMAC_TXM0);
530 /* loop until either TINT turns on or 3 seconds elapse */
531 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
532 /* transmit is done, so now check for errors
8bde7f77
WD		 533 * If there is an error, an interrupt should
534 * happen when we return
c609719b
WD		 535 */
536 time_now = get_timer (0);
537 if ((time_now - time_start) > 3000) {
538 return (-1);
539 }
540 } else {
a3ed3996 541 return (len);
c609719b
WD		 542 }
543 }
544}
545
546
547#if defined(CONFIG_440)
548/*-----------------------------------------------------------------------------+
549| EnetInt.
550| EnetInt is the interrupt handler. It will determine the
551| cause of the interrupt and call the apporpriate servive
552| routine.
553+-----------------------------------------------------------------------------*/
554int enetInt ()
555{
556 int serviced;
557 int rc = -1; /* default to not us */
558 unsigned long mal_isr;
559 unsigned long emac_isr = 0;
560 unsigned long mal_rx_eob;
561 unsigned long my_uic0msr, my_uic1msr;
562
563 /* enter loop that stays in interrupt code until nothing to service */
564 do {
565 serviced = 0;
566
567 my_uic0msr = mfdcr (uic0msr);
568 my_uic1msr = mfdcr (uic1msr);
569
570 if (!(my_uic0msr & UIC_MRE)
8bde7f77
WD		 571 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
572 /* not for us */
c609719b
WD		 573 return (rc);
574 }
575
576 /* get and clear controller status interrupts */
577 /* look at Mal and EMAC interrupts */
578 if ((my_uic0msr & UIC_MRE)
8bde7f77
WD		 579 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
580 /* we have a MAL interrupt */
c609719b
WD		 581 mal_isr = mfdcr (malesr);
582 /* look for mal error */
583 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
584 mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
585 serviced = 1;
586 rc = 0;
587 }
588 }
589 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
590 emac_isr = in32 (EMAC_ISR);
591 if ((emac_ier & emac_isr) != 0) {
592 emac_err (emac_isr);
593 serviced = 1;
594 rc = 0;
595 }
596 }
597 if ((emac_ier & emac_isr)
8bde7f77 598 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
c609719b
WD		 599 mtdcr (uic0sr, UIC_MRE); /* Clear */
600 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
601 return (rc); /* we had errors so get out */
602 }
603
604 /* handle MAL RX EOB interupt from a receive */
605 /* check for EOB on valid channels */
606 if (my_uic0msr & UIC_MRE) {
607 mal_rx_eob = mfdcr (malrxeobisr);
608 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
609 /* clear EOB
610 mtdcr(malrxeobisr, mal_rx_eob); */
611 enet_rcv (emac_isr);
612 /* indicate that we serviced an interrupt */
613 serviced = 1;
614 rc = 0;
615 }
616 }
8bde7f77
WD		 617 mtdcr (uic0sr, UIC_MRE); /* Clear */
618 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
c609719b
WD		 619 } while (serviced);
620
621 return (rc);
622}
623#else /* CONFIG_440 */
624/*-----------------------------------------------------------------------------+
625 * EnetInt.
626 * EnetInt is the interrupt handler. It will determine the
627 * cause of the interrupt and call the apporpriate servive
628 * routine.
629 *-----------------------------------------------------------------------------*/
630int enetInt ()
631{
632 int serviced;
633 int rc = -1; /* default to not us */
634 unsigned long mal_isr;
635 unsigned long emac_isr = 0;
636 unsigned long mal_rx_eob;
637 unsigned long my_uicmsr;
638
639 /* enter loop that stays in interrupt code until nothing to service */
640 do {
641 serviced = 0;
642
643 my_uicmsr = mfdcr (uicmsr);
644 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
645 return (rc);
646 }
647
648
649 /* get and clear controller status interrupts */
650 /* look at Mal and EMAC interrupts */
651 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
652 mal_isr = mfdcr (malesr);
653 /* look for mal error */
654 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
655 mal_err (mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
656 serviced = 1;
657 rc = 0;
658 }
659 }
660 if ((EMAC_UIC_DEF & my_uicmsr) != 0) { /* look for EMAC errors */
661 emac_isr = in32 (EMAC_ISR);
662 if ((emac_ier & emac_isr) != 0) {
663 emac_err (emac_isr);
664 serviced = 1;
665 rc = 0;
666 }
667 }
668 if (((emac_ier & emac_isr) != 0) | ((MAL_UIC_ERR & my_uicmsr) != 0)) {
669 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
670 return (rc); /* we had errors so get out */
671 }
672
673
674 /* handle MAL RX EOB interupt from a receive */
675 /* check for EOB on valid channels */
676 if ((my_uicmsr & UIC_MAL_RXEOB) != 0) {
677 mal_rx_eob = mfdcr (malrxeobisr);
678 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
679 /* clear EOB
680 mtdcr(malrxeobisr, mal_rx_eob); */
681 enet_rcv (emac_isr);
682 /* indicate that we serviced an interrupt */
683 serviced = 1;
684 rc = 0;
685 }
686 }
687 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
688 }
689 while (serviced);
690
691 return (rc);
692}
693#endif /* CONFIG_440 */
694
695/*-----------------------------------------------------------------------------+
696 * MAL Error Routine
697 *-----------------------------------------------------------------------------*/
a3ed3996 698static void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
c609719b
WD		 699 unsigned long mal_errr)
700{
701 mtdcr (malesr, isr); /* clear interrupt */
702
703 /* clear DE interrupt */
704 mtdcr (maltxdeir, 0xC0000000);
705 mtdcr (malrxdeir, 0x80000000);
706
b867d705 707#ifdef INFO_405_ENET
c609719b
WD		 708 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
709 isr, uic, maldef, mal_errr);
710#else
711#if 0
712 /*
713 * MAL error is RX DE error (out of rx buffers)! This is OK here, upon
714 * many incoming packets with only 4 rx buffers.
715 */
716 printf ("M"); /* just to see something upon mal error */
717#endif
b867d705 718#endif
c609719b
WD		 719
720 eth_init (bis_save); /* start again... */
721}
722
723/*-----------------------------------------------------------------------------+
724 * EMAC Error Routine
725 *-----------------------------------------------------------------------------*/
a3ed3996 726static void emac_err (unsigned long isr)
c609719b
WD		 727{
728 printf ("EMAC error occured.... ISR = %lx\n", isr);
729 out32 (EMAC_ISR, isr);
730}
731
732/*-----------------------------------------------------------------------------+
733 * enet_rcv() handles the ethernet receive data
734 *-----------------------------------------------------------------------------*/
735static void enet_rcv (unsigned long malisr)
736{
737 struct enet_frame *ef_ptr;
738 unsigned long data_len;
739 unsigned long rx_eob_isr;
740
741 int handled = 0;
742 int i;
743 int loop_count = 0;
744
745 rx_eob_isr = mfdcr (malrxeobisr);
746 if ((0x80000000 >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
747 /* clear EOB */
748 mtdcr (malrxeobisr, rx_eob_isr);
749
750 /* EMAC RX done */
751 while (1) { /* do all */
752 i = rx_slot;
753
754 if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl)
755 || (loop_count >= NUM_RX_BUFF))
756 break;
757 loop_count++;
758 rx_slot++;
759 if (NUM_RX_BUFF == rx_slot)
760 rx_slot = 0;
761 handled++;
762 data_len = (unsigned long) rx[i].data_len; /* Get len */
763 if (data_len) {
764 if (data_len > ENET_MAX_MTU) /* Check len */
765 data_len = 0;
766 else {
767 if (EMAC_RX_ERRORS & rx[i].ctrl) { /* Check Errors */
768 data_len = 0;
769 stats.rx_err_log[rx_err_index] = rx[i].ctrl;
770 rx_err_index++;
771 if (rx_err_index == MAX_ERR_LOG)
772 rx_err_index = 0;
773 } /* emac_erros */
774 } /* data_len < max mtu */
775 } /* if data_len */
776 if (!data_len) { /* no data */
777 rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
778
779 stats.emac.data_len_err++; /* Error at Rx */
780 }
781
782 /* !data_len */
783 /* AS.HARNOIS */
784 /* Check if user has already eaten buffer */
785 /* if not => ERROR */
786 else if (rx_ready[rx_i_index] != -1) {
787 if (is_receiving)
788 printf ("ERROR : Receive buffers are full!\n");
789 break;
790 } else {
791 stats.emac.rx_frames++;
792 stats.emac.rx += data_len;
793 ef_ptr = (struct enet_frame *) rx[i].data_ptr;
794#ifdef INFO_405_ENET
795 packetReceived++;
796#endif
797 /* AS.HARNOIS
798 * use ring buffer
799 */
800 rx_ready[rx_i_index] = i;
801 rx_i_index++;
802 if (NUM_RX_BUFF == rx_i_index)
803 rx_i_index = 0;
804
805 /* printf("X"); /|* test-only *|/ */
806
807 /* AS.HARNOIS
808 * free receive buffer only when
809 * buffer has been handled (eth_rx)
810 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
811 */
812 } /* if data_len */
813 } /* while */
814 } /* if EMACK_RXCHL */
815}
816
817
a3ed3996 818static int ppc_4xx_eth_rx (struct eth_device *dev)
c609719b
WD		 819{
820 int length;
821 int user_index;
822 unsigned long msr;
823
824 is_receiving = 1; /* tell driver */
825
826 for (;;) {
827 /* AS.HARNOIS
828 * use ring buffer and
829 * get index from rx buffer desciptor queue
830 */
831 user_index = rx_ready[rx_u_index];
832 if (user_index == -1) {
833 length = -1;
834 break; /* nothing received - leave for() loop */
835 }
836
837 msr = mfmsr ();
838 mtmsr (msr & ~(MSR_EE));
839
840 length = rx[user_index].data_len;
841
842 /* Pass the packet up to the protocol layers. */
843 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
844 /* NetReceive(NetRxPackets[i], length); */
845 NetReceive (NetRxPackets[user_index], length - 4);
846 /* Free Recv Buffer */
847 rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
848 /* Free rx buffer descriptor queue */
849 rx_ready[rx_u_index] = -1;
850 rx_u_index++;
851 if (NUM_RX_BUFF == rx_u_index)
852 rx_u_index = 0;
853
854#ifdef INFO_405_ENET
855 packetHandled++;
856#endif
857
858 mtmsr (msr); /* Enable IRQ's */
859 }
860
861 is_receiving = 0; /* tell driver */
862
863 return length;
864}
865
a3ed3996
WD		 866#if defined(CONFIG_NET_MULTI)
867int ppc_4xx_eth_initialize(bd_t *bis)
868{
8bde7f77
WD		 869 struct eth_device *dev;
870 int eth_num = 0;
871
872 dev = malloc (sizeof *dev);
873 if (dev == NULL) {
874 printf(__FUNCTION__ ": Cannot allocate eth_device\n");
875 return (-1);
876 }
877
878 sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
879 dev->priv = (void *) eth_num;
880 dev->init = ppc_4xx_eth_init;
881 dev->halt = ppc_4xx_eth_halt;
882 dev->send = ppc_4xx_eth_send;
883 dev->recv = ppc_4xx_eth_rx;
884
885 eth_register (dev);
a3ed3996
WD		 886}
887#else /* !defined(CONFIG_NET_MULTI) */
888void eth_halt (void)
889{
8bde7f77 890 ppc_4xx_eth_halt(NULL);
a3ed3996
WD		 891}
892
893int eth_init (bd_t *bis)
894{
8bde7f77 895 return (ppc_4xx_eth_init(NULL, bis));
a3ed3996
WD		 896}
897int eth_send(volatile void *packet, int length)
898{
8bde7f77 899 return (ppc_4xx_eth_send(NULL, packet, length));
a3ed3996
WD		 900}
901
902int eth_rx(void)
903{
8bde7f77 904 return (ppc_4xx_eth_rx(NULL));
a3ed3996
WD		 905}
906#endif /* !defined(CONFIG_NET_MULTI) */
907
c609719b 908#endif /* CONFIG_405GP */
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