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692519b1 | 1 | /* |
c9240981 | 2 | * (C) Copyright 2006 - 2007 |
692519b1 RJ |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
6 | * Roland Dreier <rolandd@cisco.com> | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | */ | |
22 | ||
4dbee8a9 | 23 | /* define DEBUG for debugging output (obviously ;-)) */ |
ff68f66b | 24 | #if 0 |
4dbee8a9 SR |
25 | #define DEBUG |
26 | #endif | |
27 | ||
692519b1 RJ |
28 | #include <asm/processor.h> |
29 | #include <asm-ppc/io.h> | |
30 | #include <ppc4xx.h> | |
31 | #include <common.h> | |
32 | #include <pci.h> | |
33 | ||
97923770 SR |
34 | #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \ |
35 | defined(CONFIG_PCI) | |
692519b1 | 36 | |
c7c6da23 | 37 | #include <asm/4xx_pcie.h> |
692519b1 RJ |
38 | |
39 | enum { | |
40 | PTYPE_ENDPOINT = 0x0, | |
41 | PTYPE_LEGACY_ENDPOINT = 0x1, | |
42 | PTYPE_ROOT_PORT = 0x4, | |
43 | ||
44 | LNKW_X1 = 0x1, | |
45 | LNKW_X4 = 0x4, | |
46 | LNKW_X8 = 0x8 | |
47 | }; | |
48 | ||
d4cb2d17 SR |
49 | static int validate_endpoint(struct pci_controller *hose) |
50 | { | |
51 | if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE) | |
52 | return (is_end_point(0)); | |
53 | else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE) | |
54 | return (is_end_point(1)); | |
55 | #if CFG_PCIE_NR_PORTS > 2 | |
56 | else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE) | |
57 | return (is_end_point(2)); | |
58 | #endif | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
7f191393 GB |
63 | static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) |
64 | { | |
65 | u8 *base = (u8*)hose->cfg_data; | |
66 | ||
67 | /* use local configuration space for the first bus */ | |
68 | if (PCI_BUS(devfn) == 0) { | |
69 | if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) | |
70 | base = (u8*)CFG_PCIE0_XCFGBASE; | |
71 | if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) | |
72 | base = (u8*)CFG_PCIE1_XCFGBASE; | |
97923770 | 73 | #if CFG_PCIE_NR_PORTS > 2 |
7f191393 GB |
74 | if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) |
75 | base = (u8*)CFG_PCIE2_XCFGBASE; | |
97923770 | 76 | #endif |
7f191393 GB |
77 | } |
78 | ||
79 | return base; | |
80 | } | |
81 | ||
15ee4734 | 82 | static void pcie_dmer_disable(void) |
c9240981 | 83 | { |
15ee4734 GB |
84 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), |
85 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); | |
86 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), | |
87 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); | |
97923770 | 88 | #if CFG_PCIE_NR_PORTS > 2 |
15ee4734 GB |
89 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), |
90 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); | |
97923770 | 91 | #endif |
c9240981 GB |
92 | } |
93 | ||
15ee4734 | 94 | static void pcie_dmer_enable(void) |
c9240981 | 95 | { |
15ee4734 GB |
96 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), |
97 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); | |
98 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), | |
99 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); | |
97923770 | 100 | #if CFG_PCIE_NR_PORTS > 2 |
15ee4734 GB |
101 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), |
102 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); | |
97923770 | 103 | #endif |
c9240981 GB |
104 | } |
105 | ||
692519b1 RJ |
106 | static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, |
107 | int offset, int len, u32 *val) { | |
108 | ||
7f191393 | 109 | u8 *address; |
692519b1 | 110 | *val = 0; |
7f191393 | 111 | |
d4cb2d17 SR |
112 | if (validate_endpoint(hose)) |
113 | return 0; /* No upstream config access */ | |
114 | ||
7f191393 GB |
115 | /* |
116 | * Bus numbers are relative to hose->first_busno | |
117 | */ | |
118 | devfn -= PCI_BDF(hose->first_busno, 0, 0); | |
119 | ||
692519b1 | 120 | /* |
7f191393 GB |
121 | * NOTICE: configuration space ranges are currenlty mapped only for |
122 | * the first 16 buses, so such limit must be imposed. In case more | |
123 | * buses are required the TLB settings in board/amcc/<board>/init.S | |
124 | * need to be altered accordingly (one bus takes 1 MB of memory space). | |
692519b1 | 125 | */ |
7f191393 | 126 | if (PCI_BUS(devfn) >= 16) |
692519b1 RJ |
127 | return 0; |
128 | ||
7f191393 GB |
129 | /* |
130 | * Only single device/single function is supported for the primary and | |
131 | * secondary buses of the 440SPe host bridge. | |
132 | */ | |
133 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && | |
134 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) | |
135 | return 0; | |
738815c0 | 136 | |
7f191393 | 137 | address = pcie_get_base(hose, devfn); |
692519b1 RJ |
138 | offset += devfn << 4; |
139 | ||
15ee4734 GB |
140 | /* |
141 | * Reading from configuration space of non-existing device can | |
142 | * generate transaction errors. For the read duration we suppress | |
143 | * assertion of machine check exceptions to avoid those. | |
144 | */ | |
145 | pcie_dmer_disable (); | |
146 | ||
97923770 | 147 | debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); |
692519b1 RJ |
148 | switch (len) { |
149 | case 1: | |
15ee4734 | 150 | *val = in_8(hose->cfg_data + offset); |
692519b1 RJ |
151 | break; |
152 | case 2: | |
15ee4734 | 153 | *val = in_le16((u16 *)(hose->cfg_data + offset)); |
692519b1 RJ |
154 | break; |
155 | default: | |
15ee4734 | 156 | *val = in_le32((u32*)(hose->cfg_data + offset)); |
692519b1 RJ |
157 | break; |
158 | } | |
15ee4734 GB |
159 | |
160 | pcie_dmer_enable (); | |
161 | ||
692519b1 RJ |
162 | return 0; |
163 | } | |
164 | ||
165 | static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, | |
166 | int offset, int len, u32 val) { | |
167 | ||
7f191393 | 168 | u8 *address; |
738815c0 | 169 | |
d4cb2d17 SR |
170 | if (validate_endpoint(hose)) |
171 | return 0; /* No upstream config access */ | |
172 | ||
692519b1 | 173 | /* |
7f191393 | 174 | * Bus numbers are relative to hose->first_busno |
692519b1 | 175 | */ |
7f191393 | 176 | devfn -= PCI_BDF(hose->first_busno, 0, 0); |
738815c0 | 177 | |
7f191393 GB |
178 | /* |
179 | * Same constraints as in pcie_read_config(). | |
180 | */ | |
181 | if (PCI_BUS(devfn) >= 16) | |
692519b1 RJ |
182 | return 0; |
183 | ||
7f191393 GB |
184 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && |
185 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) | |
186 | return 0; | |
738815c0 | 187 | |
7f191393 | 188 | address = pcie_get_base(hose, devfn); |
692519b1 RJ |
189 | offset += devfn << 4; |
190 | ||
15ee4734 GB |
191 | /* |
192 | * Suppress MCK exceptions, similar to pcie_read_config() | |
193 | */ | |
194 | pcie_dmer_disable (); | |
195 | ||
692519b1 RJ |
196 | switch (len) { |
197 | case 1: | |
198 | out_8(hose->cfg_data + offset, val); | |
199 | break; | |
200 | case 2: | |
201 | out_le16((u16 *)(hose->cfg_data + offset), val); | |
202 | break; | |
203 | default: | |
204 | out_le32((u32 *)(hose->cfg_data + offset), val); | |
205 | break; | |
206 | } | |
15ee4734 GB |
207 | |
208 | pcie_dmer_enable (); | |
209 | ||
692519b1 RJ |
210 | return 0; |
211 | } | |
212 | ||
213 | int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) | |
214 | { | |
215 | u32 v; | |
216 | int rv; | |
217 | ||
7f191393 | 218 | rv = pcie_read_config(hose, dev, offset, 1, &v); |
692519b1 RJ |
219 | *val = (u8)v; |
220 | return rv; | |
221 | } | |
222 | ||
223 | int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) | |
224 | { | |
225 | u32 v; | |
226 | int rv; | |
227 | ||
228 | rv = pcie_read_config(hose, dev, offset, 2, &v); | |
229 | *val = (u16)v; | |
230 | return rv; | |
231 | } | |
232 | ||
233 | int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) | |
234 | { | |
235 | u32 v; | |
236 | int rv; | |
237 | ||
238 | rv = pcie_read_config(hose, dev, offset, 3, &v); | |
239 | *val = (u32)v; | |
240 | return rv; | |
241 | } | |
242 | ||
243 | int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) | |
244 | { | |
245 | return pcie_write_config(hose,(u32)dev,offset,1,val); | |
246 | } | |
247 | ||
248 | int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) | |
249 | { | |
250 | return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); | |
251 | } | |
252 | ||
253 | int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) | |
254 | { | |
255 | return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); | |
256 | } | |
257 | ||
97923770 | 258 | #if defined(CONFIG_440SPE) |
026f7110 | 259 | static void ppc4xx_setup_utl(u32 port) { |
692519b1 RJ |
260 | |
261 | volatile void *utl_base = NULL; | |
262 | ||
263 | /* | |
264 | * Map UTL registers | |
265 | */ | |
266 | switch (port) { | |
267 | case 0: | |
36b904a7 RJ |
268 | mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); |
269 | mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); | |
270 | mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); | |
692519b1 | 271 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); |
692519b1 RJ |
272 | break; |
273 | ||
274 | case 1: | |
36b904a7 RJ |
275 | mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); |
276 | mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); | |
277 | mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); | |
692519b1 | 278 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); |
692519b1 RJ |
279 | break; |
280 | ||
281 | case 2: | |
36b904a7 RJ |
282 | mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); |
283 | mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); | |
284 | mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); | |
692519b1 | 285 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); |
692519b1 RJ |
286 | break; |
287 | } | |
36b904a7 | 288 | utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); |
16850919 | 289 | |
692519b1 RJ |
290 | /* |
291 | * Set buffer allocations and then assert VRB and TXE. | |
292 | */ | |
293 | out_be32(utl_base + PEUTL_OUTTR, 0x08000000); | |
294 | out_be32(utl_base + PEUTL_INTR, 0x02000000); | |
295 | out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); | |
296 | out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); | |
297 | out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); | |
298 | out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); | |
299 | out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
36b904a7 | 300 | out_be32(utl_base + PEUTL_PCTL, 0x80800066); |
692519b1 RJ |
301 | } |
302 | ||
303 | static int check_error(void) | |
304 | { | |
305 | u32 valPE0, valPE1, valPE2; | |
306 | int err = 0; | |
307 | ||
308 | /* SDR0_PEGPLLLCT1 reset */ | |
309 | if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { | |
310 | printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); | |
311 | } | |
312 | ||
313 | valPE0 = SDR_READ(PESDR0_RCSSET); | |
314 | valPE1 = SDR_READ(PESDR1_RCSSET); | |
315 | valPE2 = SDR_READ(PESDR2_RCSSET); | |
316 | ||
317 | /* SDR0_PExRCSSET rstgu */ | |
318 | if (!(valPE0 & 0x01000000) || | |
319 | !(valPE1 & 0x01000000) || | |
320 | !(valPE2 & 0x01000000)) { | |
321 | printf("PCIE: SDR0_PExRCSSET rstgu error\n"); | |
322 | err = -1; | |
323 | } | |
324 | ||
325 | /* SDR0_PExRCSSET rstdl */ | |
326 | if (!(valPE0 & 0x00010000) || | |
327 | !(valPE1 & 0x00010000) || | |
328 | !(valPE2 & 0x00010000)) { | |
329 | printf("PCIE: SDR0_PExRCSSET rstdl error\n"); | |
330 | err = -1; | |
331 | } | |
332 | ||
333 | /* SDR0_PExRCSSET rstpyn */ | |
334 | if ((valPE0 & 0x00001000) || | |
335 | (valPE1 & 0x00001000) || | |
336 | (valPE2 & 0x00001000)) { | |
337 | printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
338 | err = -1; | |
339 | } | |
340 | ||
341 | /* SDR0_PExRCSSET hldplb */ | |
342 | if ((valPE0 & 0x10000000) || | |
343 | (valPE1 & 0x10000000) || | |
344 | (valPE2 & 0x10000000)) { | |
345 | printf("PCIE: SDR0_PExRCSSET hldplb error\n"); | |
346 | err = -1; | |
347 | } | |
348 | ||
349 | /* SDR0_PExRCSSET rdy */ | |
350 | if ((valPE0 & 0x00100000) || | |
351 | (valPE1 & 0x00100000) || | |
352 | (valPE2 & 0x00100000)) { | |
353 | printf("PCIE: SDR0_PExRCSSET rdy error\n"); | |
354 | err = -1; | |
355 | } | |
356 | ||
357 | /* SDR0_PExRCSSET shutdown */ | |
358 | if ((valPE0 & 0x00000100) || | |
359 | (valPE1 & 0x00000100) || | |
360 | (valPE2 & 0x00000100)) { | |
361 | printf("PCIE: SDR0_PExRCSSET shutdown error\n"); | |
362 | err = -1; | |
363 | } | |
364 | return err; | |
365 | } | |
366 | ||
367 | /* | |
368 | * Initialize PCI Express core | |
369 | */ | |
026f7110 | 370 | int ppc4xx_init_pcie(void) |
692519b1 RJ |
371 | { |
372 | int time_out = 20; | |
373 | ||
374 | /* Set PLL clock receiver to LVPECL */ | |
375 | SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); | |
376 | ||
377 | if (check_error()) | |
378 | return -1; | |
379 | ||
380 | if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) | |
381 | { | |
382 | printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", | |
383 | SDR_READ(PESDR0_PLLLCT2)); | |
384 | return -1; | |
385 | } | |
386 | /* De-assert reset of PCIe PLL, wait for lock */ | |
387 | SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); | |
388 | udelay(3); | |
389 | ||
2b393b0f | 390 | while (time_out) { |
692519b1 RJ |
391 | if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { |
392 | time_out--; | |
393 | udelay(1); | |
394 | } else | |
395 | break; | |
396 | } | |
397 | if (!time_out) { | |
398 | printf("PCIE: VCO output not locked\n"); | |
399 | return -1; | |
400 | } | |
401 | return 0; | |
402 | } | |
97923770 | 403 | #else |
f31d38b9 SR |
404 | static void ppc4xx_setup_utl(u32 port) |
405 | { | |
406 | u32 utl_base; | |
407 | ||
408 | /* | |
409 | * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK | |
410 | */ | |
411 | switch (port) { | |
412 | case 0: | |
413 | mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); | |
414 | mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); | |
653811a3 | 415 | mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ |
f31d38b9 SR |
416 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); |
417 | break; | |
418 | ||
419 | case 1: | |
420 | mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); | |
421 | mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); | |
653811a3 | 422 | mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ |
f31d38b9 SR |
423 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); |
424 | ||
425 | break; | |
426 | } | |
427 | utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE; | |
428 | ||
429 | /* | |
430 | * Set buffer allocations and then assert VRB and TXE. | |
431 | */ | |
432 | out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); | |
433 | out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); | |
434 | out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); | |
435 | out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); | |
436 | out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); | |
437 | out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); | |
438 | out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); | |
439 | out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); | |
440 | ||
441 | out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); | |
442 | out_be32((u32 *)(utl_base + PEUTL_RCSTA), | |
443 | in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); | |
444 | } | |
445 | ||
97923770 SR |
446 | int ppc4xx_init_pcie(void) |
447 | { | |
448 | /* | |
449 | * Nothing to do on 405EX | |
450 | */ | |
451 | return 0; | |
452 | } | |
453 | #endif | |
692519b1 | 454 | |
2b393b0f | 455 | /* |
03d344bb SR |
456 | * Board-specific pcie initialization |
457 | * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed | |
458 | */ | |
459 | ||
460 | /* | |
461 | * Initialize various parts of the PCI Express core for our port: | |
462 | * | |
463 | * - Set as a root port and enable max width | |
464 | * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). | |
465 | * - Set up UTL configuration. | |
466 | * - Increase SERDES drive strength to levels suggested by AMCC. | |
467 | * - De-assert RSTPYN, RSTDL and RSTGU. | |
468 | * | |
469 | * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it | |
470 | * with default setting 0x11310000. The register has new fields, | |
471 | * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core | |
472 | * hang. | |
473 | */ | |
474 | #if defined(CONFIG_440SPE) | |
475 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
476 | { | |
477 | u32 val = 1 << 24; | |
478 | u32 utlset1; | |
479 | ||
480 | if (rootport) { | |
481 | val = PTYPE_ROOT_PORT << 20; | |
482 | utlset1 = 0x21222222; | |
483 | } else { | |
484 | val = PTYPE_LEGACY_ENDPOINT << 20; | |
485 | utlset1 = 0x20222222; | |
486 | } | |
487 | ||
488 | if (port == 0) | |
489 | val |= LNKW_X8 << 12; | |
490 | else | |
491 | val |= LNKW_X4 << 12; | |
492 | ||
493 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
494 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); | |
495 | if (!ppc440spe_revB()) | |
496 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); | |
497 | SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); | |
498 | SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); | |
499 | SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); | |
500 | SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); | |
501 | if (port == 0) { | |
502 | SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); | |
503 | SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); | |
504 | SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); | |
505 | SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); | |
506 | } | |
507 | SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & | |
508 | ~(1 << 24 | 1 << 16)) | 1 << 12); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | #endif /* CONFIG_440SPE */ | |
513 | ||
514 | #if defined(CONFIG_405EX) | |
515 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
516 | { | |
517 | u32 val; | |
518 | ||
519 | if (rootport) | |
520 | val = 0x00401000; | |
521 | else | |
522 | val = 0x00101000; | |
523 | ||
524 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
7d0a4066 SR |
525 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); |
526 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); | |
03d344bb SR |
527 | SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); |
528 | SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); | |
529 | ||
530 | /* Assert the PE0_PHY reset */ | |
531 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); | |
532 | udelay(1000); | |
533 | ||
534 | /* deassert the PE0_hotreset */ | |
5cb4af47 SR |
535 | if (is_end_point(port)) |
536 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); | |
537 | else | |
538 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); | |
03d344bb SR |
539 | |
540 | /* poll for phy !reset */ | |
541 | while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) | |
542 | ; | |
543 | ||
544 | /* deassert the PE0_gpl_utl_reset */ | |
545 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); | |
546 | ||
547 | if (port == 0) | |
548 | mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ | |
549 | else | |
550 | mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ | |
551 | ||
552 | return 0; | |
553 | } | |
554 | #endif /* CONFIG_405EX */ | |
555 | ||
556 | int ppc4xx_init_pcie_port_hw(int port, int rootport) | |
653811a3 | 557 | __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); |
03d344bb SR |
558 | |
559 | /* | |
560 | * We map PCI Express configuration access into the 512MB regions | |
561 | * | |
562 | * NOTICE: revB is very strict about PLB real addressess and ranges to | |
563 | * be mapped for config space; it seems to only work with d_nnnn_nnnn | |
564 | * range (hangs the core upon config transaction attempts when set | |
565 | * otherwise) while revA uses c_nnnn_nnnn. | |
566 | * | |
567 | * For revA: | |
568 | * PCIE0: 0xc_4000_0000 | |
569 | * PCIE1: 0xc_8000_0000 | |
570 | * PCIE2: 0xc_c000_0000 | |
571 | * | |
572 | * For revB: | |
573 | * PCIE0: 0xd_0000_0000 | |
574 | * PCIE1: 0xd_2000_0000 | |
575 | * PCIE2: 0xd_4000_0000 | |
576 | * | |
577 | * For 405EX: | |
578 | * PCIE0: 0xa000_0000 | |
579 | * PCIE1: 0xc000_0000 | |
580 | */ | |
581 | static inline u64 ppc4xx_get_cfgaddr(int port) | |
582 | { | |
583 | #if defined(CONFIG_405EX) | |
584 | if (port == 0) | |
585 | return (u64)CFG_PCIE0_CFGBASE; | |
586 | else | |
587 | return (u64)CFG_PCIE1_CFGBASE; | |
588 | #endif | |
589 | #if defined(CONFIG_440SPE) | |
590 | if (ppc440spe_revB()) { | |
591 | switch (port) { | |
592 | default: /* to satisfy compiler */ | |
593 | case 0: | |
594 | return 0x0000000d00000000ULL; | |
595 | case 1: | |
596 | return 0x0000000d20000000ULL; | |
597 | case 2: | |
598 | return 0x0000000d40000000ULL; | |
599 | } | |
600 | } else { | |
601 | switch (port) { | |
602 | default: /* to satisfy compiler */ | |
603 | case 0: | |
604 | return 0x0000000c40000000ULL; | |
605 | case 1: | |
606 | return 0x0000000c80000000ULL; | |
607 | case 2: | |
608 | return 0x0000000cc0000000ULL; | |
609 | } | |
610 | } | |
611 | #endif | |
612 | } | |
613 | ||
614 | /* | |
615 | * 4xx boards as end point and root point setup | |
2b393b0f SR |
616 | * and |
617 | * testing inbound and out bound windows | |
618 | * | |
03d344bb | 619 | * 4xx boards can be plugged into another 4xx boards or you can get PCI-E |
2b393b0f SR |
620 | * cable which can be used to setup loop back from one port to another port. |
621 | * Please rememeber that unless there is a endpoint plugged in to root port it | |
622 | * will not initialize. It is the same in case of endpoint , unless there is | |
623 | * root port attached it will not initialize. | |
624 | * | |
625 | * In this release of software all the PCI-E ports are configured as either | |
626 | * endpoint or rootpoint.In future we will have support for selective ports | |
627 | * setup as endpoint and root point in single board. | |
628 | * | |
629 | * Once your board came up as root point , you can verify by reading | |
630 | * /proc/bus/pci/devices. Where you can see the configuration registers | |
631 | * of end point device attached to the port. | |
632 | * | |
03d344bb SR |
633 | * Enpoint cofiguration can be verified by connecting 4xx board to any |
634 | * host or another 4xx board. Then try to scan the device. In case of | |
2b393b0f SR |
635 | * linux use "lspci" or appripriate os command. |
636 | * | |
03d344bb | 637 | * How do I verify the inbound and out bound windows ? (4xx to 4xx) |
2b393b0f SR |
638 | * in this configuration inbound and outbound windows are setup to access |
639 | * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address | |
640 | * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, | |
641 | * This is waere your POM(PLB out bound memory window) mapped. then | |
03d344bb | 642 | * read the data from other 4xx board's u-boot prompt at address |
2b393b0f SR |
643 | * 0x9000 0000(SRAM). Data should match. |
644 | * In case of inbound , write data to u-boot command prompt at 0xb000 0000 | |
645 | * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check | |
646 | * data at 0x9000 0000(SRAM).Data should match. | |
647 | */ | |
03d344bb | 648 | int ppc4xx_init_pcie_port(int port, int rootport) |
692519b1 RJ |
649 | { |
650 | static int core_init; | |
651 | volatile u32 val = 0; | |
652 | int attempts; | |
03d344bb SR |
653 | u64 addr; |
654 | u32 low, high; | |
692519b1 RJ |
655 | |
656 | if (!core_init) { | |
026f7110 | 657 | if (ppc4xx_init_pcie()) |
692519b1 | 658 | return -1; |
d4cb2d17 | 659 | ++core_init; |
692519b1 RJ |
660 | } |
661 | ||
662 | /* | |
03d344bb | 663 | * Initialize various parts of the PCI Express core for our port |
692519b1 | 664 | */ |
03d344bb | 665 | ppc4xx_init_pcie_port_hw(port, rootport); |
692519b1 | 666 | |
2b393b0f SR |
667 | /* |
668 | * Notice: the following delay has critical impact on device | |
669 | * initialization - if too short (<50ms) the link doesn't get up. | |
670 | */ | |
671 | mdelay(100); | |
672 | ||
6d952892 | 673 | val = SDR_READ(SDRN_PESDR_RCSSTS(port)); |
2b393b0f SR |
674 | if (val & (1 << 20)) { |
675 | printf("PCIE%d: PGRST failed %08x\n", port, val); | |
676 | return -1; | |
677 | } | |
678 | ||
679 | /* | |
680 | * Verify link is up | |
681 | */ | |
6d952892 | 682 | val = SDR_READ(SDRN_PESDR_LOOP(port)); |
2b393b0f SR |
683 | if (!(val & 0x00001000)) { |
684 | printf("PCIE%d: link is not up.\n", port); | |
685 | return -1; | |
686 | } | |
687 | ||
688 | /* | |
689 | * Setup UTL registers - but only on revA! | |
690 | * We use default settings for revB chip. | |
691 | */ | |
692 | if (!ppc440spe_revB()) | |
026f7110 | 693 | ppc4xx_setup_utl(port); |
2b393b0f SR |
694 | |
695 | /* | |
696 | * We map PCI Express configuration access into the 512MB regions | |
2b393b0f | 697 | */ |
03d344bb | 698 | addr = ppc4xx_get_cfgaddr(port); |
97923770 SR |
699 | low = U64_TO_U32_LOW(addr); |
700 | high = U64_TO_U32_HIGH(addr); | |
2b393b0f SR |
701 | |
702 | switch (port) { | |
703 | case 0: | |
03d344bb SR |
704 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); |
705 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); | |
2b393b0f SR |
706 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ |
707 | break; | |
2b393b0f | 708 | case 1: |
03d344bb SR |
709 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); |
710 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); | |
2b393b0f SR |
711 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ |
712 | break; | |
97923770 | 713 | #if CFG_PCIE_NR_PORTS > 2 |
2b393b0f | 714 | case 2: |
03d344bb SR |
715 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); |
716 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); | |
2b393b0f SR |
717 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ |
718 | break; | |
97923770 | 719 | #endif |
2b393b0f SR |
720 | } |
721 | ||
722 | /* | |
723 | * Check for VC0 active and assert RDY. | |
724 | */ | |
725 | attempts = 10; | |
6d952892 | 726 | while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { |
03d344bb SR |
727 | if (!(attempts--)) { |
728 | printf("PCIE%d: VC0 not active\n", port); | |
729 | return -1; | |
2b393b0f | 730 | } |
03d344bb | 731 | mdelay(1000); |
2b393b0f | 732 | } |
6d952892 SR |
733 | SDR_WRITE(SDRN_PESDR_RCSSET(port), |
734 | SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); | |
2b393b0f SR |
735 | mdelay(100); |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
03d344bb | 740 | int ppc4xx_init_pcie_rootport(int port) |
2b393b0f | 741 | { |
03d344bb SR |
742 | return ppc4xx_init_pcie_port(port, 1); |
743 | } | |
692519b1 | 744 | |
03d344bb SR |
745 | int ppc4xx_init_pcie_endport(int port) |
746 | { | |
747 | return ppc4xx_init_pcie_port(port, 0); | |
692519b1 RJ |
748 | } |
749 | ||
026f7110 | 750 | void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) |
692519b1 RJ |
751 | { |
752 | volatile void *mbase = NULL; | |
2b393b0f | 753 | volatile void *rmbase = NULL; |
692519b1 RJ |
754 | |
755 | pci_set_ops(hose, | |
03d344bb SR |
756 | pcie_read_config_byte, |
757 | pcie_read_config_word, | |
758 | pcie_read_config_dword, | |
759 | pcie_write_config_byte, | |
760 | pcie_write_config_word, | |
761 | pcie_write_config_dword); | |
2b393b0f SR |
762 | |
763 | switch (port) { | |
692519b1 RJ |
764 | case 0: |
765 | mbase = (u32 *)CFG_PCIE0_XCFGBASE; | |
2b393b0f | 766 | rmbase = (u32 *)CFG_PCIE0_CFGBASE; |
692519b1 RJ |
767 | hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; |
768 | break; | |
769 | case 1: | |
770 | mbase = (u32 *)CFG_PCIE1_XCFGBASE; | |
2b393b0f | 771 | rmbase = (u32 *)CFG_PCIE1_CFGBASE; |
692519b1 RJ |
772 | hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; |
773 | break; | |
97923770 | 774 | #if CFG_PCIE_NR_PORTS > 2 |
692519b1 RJ |
775 | case 2: |
776 | mbase = (u32 *)CFG_PCIE2_XCFGBASE; | |
2b393b0f | 777 | rmbase = (u32 *)CFG_PCIE2_CFGBASE; |
692519b1 RJ |
778 | hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; |
779 | break; | |
97923770 | 780 | #endif |
692519b1 RJ |
781 | } |
782 | ||
783 | /* | |
784 | * Set bus numbers on our root port | |
785 | */ | |
7f191393 GB |
786 | out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); |
787 | out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); | |
788 | out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); | |
692519b1 RJ |
789 | |
790 | /* | |
791 | * Set up outbound translation to hose->mem_space from PLB | |
792 | * addresses at an offset of 0xd_0000_0000. We set the low | |
793 | * bits of the mask to 11 to turn off splitting into 8 | |
794 | * subregions and to enable the outbound translation. | |
795 | */ | |
796 | out_le32(mbase + PECFG_POM0LAH, 0x00000000); | |
4dbee8a9 SR |
797 | out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE + |
798 | port * CFG_PCIE_MEMSIZE); | |
799 | debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), | |
800 | in_le32(mbase + PECFG_POM0LAL)); | |
692519b1 RJ |
801 | |
802 | switch (port) { | |
803 | case 0: | |
97923770 SR |
804 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); |
805 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + | |
03d344bb | 806 | port * CFG_PCIE_MEMSIZE); |
692519b1 RJ |
807 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
808 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), | |
03d344bb | 809 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
4dbee8a9 SR |
810 | debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", |
811 | mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), | |
812 | mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), | |
813 | mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), | |
814 | mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); | |
692519b1 RJ |
815 | break; |
816 | case 1: | |
97923770 SR |
817 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); |
818 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + | |
03d344bb | 819 | port * CFG_PCIE_MEMSIZE); |
692519b1 RJ |
820 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
821 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), | |
03d344bb | 822 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
4dbee8a9 SR |
823 | debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", |
824 | mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), | |
825 | mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), | |
826 | mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), | |
827 | mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); | |
692519b1 | 828 | break; |
97923770 | 829 | #if CFG_PCIE_NR_PORTS > 2 |
692519b1 | 830 | case 2: |
97923770 SR |
831 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); |
832 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + | |
03d344bb | 833 | port * CFG_PCIE_MEMSIZE); |
692519b1 RJ |
834 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
835 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), | |
03d344bb | 836 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
4dbee8a9 SR |
837 | debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", |
838 | mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), | |
839 | mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), | |
840 | mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), | |
841 | mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); | |
692519b1 | 842 | break; |
97923770 | 843 | #endif |
692519b1 RJ |
844 | } |
845 | ||
846 | /* Set up 16GB inbound memory window at 0 */ | |
847 | out_le32(mbase + PCI_BASE_ADDRESS_0, 0); | |
848 | out_le32(mbase + PCI_BASE_ADDRESS_1, 0); | |
849 | out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); | |
850 | out_le32(mbase + PECFG_BAR0LMPA, 0); | |
2b393b0f SR |
851 | |
852 | out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); | |
853 | out_le32(mbase + PECFG_PIM01SAL, 0x00000000); | |
692519b1 RJ |
854 | out_le32(mbase + PECFG_PIM0LAL, 0); |
855 | out_le32(mbase + PECFG_PIM0LAH, 0); | |
97923770 SR |
856 | out_le32(mbase + PECFG_PIM1LAL, 0x00000000); |
857 | out_le32(mbase + PECFG_PIM1LAH, 0x00000004); | |
2b393b0f SR |
858 | out_le32(mbase + PECFG_PIMEN, 0x1); |
859 | ||
860 | /* Enable I/O, Mem, and Busmaster cycles */ | |
861 | out_le16((u16 *)(mbase + PCI_COMMAND), | |
862 | in_le16((u16 *)(mbase + PCI_COMMAND)) | | |
863 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
738815c0 | 864 | |
7f191393 | 865 | /* Set Device and Vendor Id */ |
97923770 SR |
866 | out_le16(mbase + 0x200, 0xaaa0 + port); |
867 | out_le16(mbase + 0x202, 0xbed0 + port); | |
7f191393 GB |
868 | |
869 | /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ | |
870 | out_le32(mbase + 0x208, 0x06040001); | |
871 | ||
19e93b1e | 872 | printf("PCIE%d: successfully set as root-complex\n", port); |
2b393b0f SR |
873 | } |
874 | ||
026f7110 | 875 | int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) |
2b393b0f SR |
876 | { |
877 | volatile void *mbase = NULL; | |
878 | int attempts = 0; | |
879 | ||
880 | pci_set_ops(hose, | |
881 | pcie_read_config_byte, | |
882 | pcie_read_config_word, | |
883 | pcie_read_config_dword, | |
884 | pcie_write_config_byte, | |
885 | pcie_write_config_word, | |
886 | pcie_write_config_dword); | |
887 | ||
888 | switch (port) { | |
889 | case 0: | |
890 | mbase = (u32 *)CFG_PCIE0_XCFGBASE; | |
891 | hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; | |
892 | break; | |
893 | case 1: | |
894 | mbase = (u32 *)CFG_PCIE1_XCFGBASE; | |
895 | hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; | |
896 | break; | |
97923770 | 897 | #if defined(CFG_PCIE2_CFGBASE) |
2b393b0f SR |
898 | case 2: |
899 | mbase = (u32 *)CFG_PCIE2_XCFGBASE; | |
900 | hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; | |
901 | break; | |
97923770 | 902 | #endif |
2b393b0f SR |
903 | } |
904 | ||
905 | /* | |
906 | * Set up outbound translation to hose->mem_space from PLB | |
907 | * addresses at an offset of 0xd_0000_0000. We set the low | |
908 | * bits of the mask to 11 to turn off splitting into 8 | |
909 | * subregions and to enable the outbound translation. | |
910 | */ | |
911 | out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); | |
912 | out_le32(mbase + PECFG_POM0LAL, 0x00001000); | |
913 | ||
914 | switch (port) { | |
915 | case 0: | |
97923770 SR |
916 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); |
917 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + | |
03d344bb | 918 | port * CFG_PCIE_MEMSIZE); |
2b393b0f SR |
919 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
920 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), | |
03d344bb | 921 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
2b393b0f SR |
922 | break; |
923 | case 1: | |
97923770 SR |
924 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); |
925 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + | |
03d344bb | 926 | port * CFG_PCIE_MEMSIZE); |
2b393b0f SR |
927 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
928 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), | |
03d344bb | 929 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
2b393b0f | 930 | break; |
97923770 | 931 | #if CFG_PCIE_NR_PORTS > 2 |
2b393b0f | 932 | case 2: |
97923770 SR |
933 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); |
934 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + | |
03d344bb | 935 | port * CFG_PCIE_MEMSIZE); |
2b393b0f SR |
936 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
937 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), | |
03d344bb | 938 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
2b393b0f | 939 | break; |
97923770 | 940 | #endif |
2b393b0f SR |
941 | } |
942 | ||
5cb4af47 | 943 | /* Set up 64MB inbound memory window at 0 */ |
2b393b0f SR |
944 | out_le32(mbase + PCI_BASE_ADDRESS_0, 0); |
945 | out_le32(mbase + PCI_BASE_ADDRESS_1, 0); | |
5cb4af47 SR |
946 | |
947 | out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); | |
948 | out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); | |
949 | ||
950 | /* Setup BAR0 */ | |
951 | out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); | |
952 | out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); | |
953 | ||
954 | /* Disable BAR1 & BAR2 */ | |
955 | out_le32(mbase + PECFG_BAR1MPA, 0); | |
956 | out_le32(mbase + PECFG_BAR2HMPA, 0); | |
957 | out_le32(mbase + PECFG_BAR2LMPA, 0); | |
958 | ||
97923770 SR |
959 | out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE)); |
960 | out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE)); | |
692519b1 RJ |
961 | out_le32(mbase + PECFG_PIMEN, 0x1); |
962 | ||
963 | /* Enable I/O, Mem, and Busmaster cycles */ | |
964 | out_le16((u16 *)(mbase + PCI_COMMAND), | |
03d344bb SR |
965 | in_le16((u16 *)(mbase + PCI_COMMAND)) | |
966 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
97923770 SR |
967 | out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ |
968 | out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ | |
03d344bb | 969 | |
5cb4af47 SR |
970 | /* Set Class Code to Processor/PPC */ |
971 | out_le32(mbase + 0x208, 0x0b200001); | |
972 | ||
2b393b0f | 973 | attempts = 10; |
6d952892 | 974 | while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { |
03d344bb SR |
975 | if (!(attempts--)) { |
976 | printf("PCIE%d: BME not active\n", port); | |
977 | return -1; | |
2b393b0f | 978 | } |
03d344bb | 979 | mdelay(1000); |
2b393b0f | 980 | } |
03d344bb | 981 | |
19e93b1e | 982 | printf("PCIE%d: successfully set as endpoint\n", port); |
2b393b0f SR |
983 | |
984 | return 0; | |
692519b1 | 985 | } |
5fb692ca | 986 | #endif /* CONFIG_440SPE && CONFIG_PCI */ |