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692519b1 | 1 | /* |
c9240981 | 2 | * (C) Copyright 2006 - 2007 |
692519b1 RJ |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
6 | * Roland Dreier <rolandd@cisco.com> | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <asm/processor.h> | |
24 | #include <asm-ppc/io.h> | |
25 | #include <ppc4xx.h> | |
26 | #include <common.h> | |
27 | #include <pci.h> | |
28 | ||
5fb692ca | 29 | #if defined(CONFIG_440SPE) && defined(CONFIG_PCI) |
692519b1 | 30 | |
c7c6da23 | 31 | #include <asm/4xx_pcie.h> |
692519b1 RJ |
32 | |
33 | enum { | |
34 | PTYPE_ENDPOINT = 0x0, | |
35 | PTYPE_LEGACY_ENDPOINT = 0x1, | |
36 | PTYPE_ROOT_PORT = 0x4, | |
37 | ||
38 | LNKW_X1 = 0x1, | |
39 | LNKW_X4 = 0x4, | |
40 | LNKW_X8 = 0x8 | |
41 | }; | |
42 | ||
7f191393 GB |
43 | static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) |
44 | { | |
45 | u8 *base = (u8*)hose->cfg_data; | |
46 | ||
47 | /* use local configuration space for the first bus */ | |
48 | if (PCI_BUS(devfn) == 0) { | |
49 | if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) | |
50 | base = (u8*)CFG_PCIE0_XCFGBASE; | |
51 | if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) | |
52 | base = (u8*)CFG_PCIE1_XCFGBASE; | |
53 | if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) | |
54 | base = (u8*)CFG_PCIE2_XCFGBASE; | |
55 | } | |
56 | ||
57 | return base; | |
58 | } | |
59 | ||
15ee4734 | 60 | static void pcie_dmer_disable(void) |
c9240981 | 61 | { |
15ee4734 GB |
62 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), |
63 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); | |
64 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), | |
65 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); | |
66 | mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), | |
67 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); | |
c9240981 GB |
68 | } |
69 | ||
15ee4734 | 70 | static void pcie_dmer_enable(void) |
c9240981 | 71 | { |
15ee4734 GB |
72 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), |
73 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); | |
74 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), | |
75 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); | |
76 | mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), | |
77 | mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); | |
c9240981 GB |
78 | } |
79 | ||
692519b1 RJ |
80 | static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, |
81 | int offset, int len, u32 *val) { | |
82 | ||
7f191393 | 83 | u8 *address; |
692519b1 | 84 | *val = 0; |
7f191393 GB |
85 | |
86 | /* | |
87 | * Bus numbers are relative to hose->first_busno | |
88 | */ | |
89 | devfn -= PCI_BDF(hose->first_busno, 0, 0); | |
90 | ||
692519b1 | 91 | /* |
7f191393 GB |
92 | * NOTICE: configuration space ranges are currenlty mapped only for |
93 | * the first 16 buses, so such limit must be imposed. In case more | |
94 | * buses are required the TLB settings in board/amcc/<board>/init.S | |
95 | * need to be altered accordingly (one bus takes 1 MB of memory space). | |
692519b1 | 96 | */ |
7f191393 | 97 | if (PCI_BUS(devfn) >= 16) |
692519b1 RJ |
98 | return 0; |
99 | ||
7f191393 GB |
100 | /* |
101 | * Only single device/single function is supported for the primary and | |
102 | * secondary buses of the 440SPe host bridge. | |
103 | */ | |
104 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && | |
105 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) | |
106 | return 0; | |
738815c0 | 107 | |
7f191393 | 108 | address = pcie_get_base(hose, devfn); |
692519b1 RJ |
109 | offset += devfn << 4; |
110 | ||
15ee4734 GB |
111 | /* |
112 | * Reading from configuration space of non-existing device can | |
113 | * generate transaction errors. For the read duration we suppress | |
114 | * assertion of machine check exceptions to avoid those. | |
115 | */ | |
116 | pcie_dmer_disable (); | |
117 | ||
692519b1 RJ |
118 | switch (len) { |
119 | case 1: | |
15ee4734 | 120 | *val = in_8(hose->cfg_data + offset); |
692519b1 RJ |
121 | break; |
122 | case 2: | |
15ee4734 | 123 | *val = in_le16((u16 *)(hose->cfg_data + offset)); |
692519b1 RJ |
124 | break; |
125 | default: | |
15ee4734 | 126 | *val = in_le32((u32*)(hose->cfg_data + offset)); |
692519b1 RJ |
127 | break; |
128 | } | |
15ee4734 GB |
129 | |
130 | pcie_dmer_enable (); | |
131 | ||
692519b1 RJ |
132 | return 0; |
133 | } | |
134 | ||
135 | static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, | |
136 | int offset, int len, u32 val) { | |
137 | ||
7f191393 | 138 | u8 *address; |
738815c0 | 139 | |
692519b1 | 140 | /* |
7f191393 | 141 | * Bus numbers are relative to hose->first_busno |
692519b1 | 142 | */ |
7f191393 | 143 | devfn -= PCI_BDF(hose->first_busno, 0, 0); |
738815c0 | 144 | |
7f191393 GB |
145 | /* |
146 | * Same constraints as in pcie_read_config(). | |
147 | */ | |
148 | if (PCI_BUS(devfn) >= 16) | |
692519b1 RJ |
149 | return 0; |
150 | ||
7f191393 GB |
151 | if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && |
152 | ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) | |
153 | return 0; | |
738815c0 | 154 | |
7f191393 | 155 | address = pcie_get_base(hose, devfn); |
692519b1 RJ |
156 | offset += devfn << 4; |
157 | ||
15ee4734 GB |
158 | /* |
159 | * Suppress MCK exceptions, similar to pcie_read_config() | |
160 | */ | |
161 | pcie_dmer_disable (); | |
162 | ||
692519b1 RJ |
163 | switch (len) { |
164 | case 1: | |
165 | out_8(hose->cfg_data + offset, val); | |
166 | break; | |
167 | case 2: | |
168 | out_le16((u16 *)(hose->cfg_data + offset), val); | |
169 | break; | |
170 | default: | |
171 | out_le32((u32 *)(hose->cfg_data + offset), val); | |
172 | break; | |
173 | } | |
15ee4734 GB |
174 | |
175 | pcie_dmer_enable (); | |
176 | ||
692519b1 RJ |
177 | return 0; |
178 | } | |
179 | ||
180 | int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) | |
181 | { | |
182 | u32 v; | |
183 | int rv; | |
184 | ||
7f191393 | 185 | rv = pcie_read_config(hose, dev, offset, 1, &v); |
692519b1 RJ |
186 | *val = (u8)v; |
187 | return rv; | |
188 | } | |
189 | ||
190 | int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) | |
191 | { | |
192 | u32 v; | |
193 | int rv; | |
194 | ||
195 | rv = pcie_read_config(hose, dev, offset, 2, &v); | |
196 | *val = (u16)v; | |
197 | return rv; | |
198 | } | |
199 | ||
200 | int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) | |
201 | { | |
202 | u32 v; | |
203 | int rv; | |
204 | ||
205 | rv = pcie_read_config(hose, dev, offset, 3, &v); | |
206 | *val = (u32)v; | |
207 | return rv; | |
208 | } | |
209 | ||
210 | int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) | |
211 | { | |
212 | return pcie_write_config(hose,(u32)dev,offset,1,val); | |
213 | } | |
214 | ||
215 | int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) | |
216 | { | |
217 | return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); | |
218 | } | |
219 | ||
220 | int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) | |
221 | { | |
222 | return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); | |
223 | } | |
224 | ||
026f7110 | 225 | static void ppc4xx_setup_utl(u32 port) { |
692519b1 RJ |
226 | |
227 | volatile void *utl_base = NULL; | |
228 | ||
229 | /* | |
230 | * Map UTL registers | |
231 | */ | |
232 | switch (port) { | |
233 | case 0: | |
36b904a7 RJ |
234 | mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); |
235 | mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); | |
236 | mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); | |
692519b1 | 237 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); |
692519b1 RJ |
238 | break; |
239 | ||
240 | case 1: | |
36b904a7 RJ |
241 | mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); |
242 | mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); | |
243 | mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); | |
692519b1 | 244 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); |
692519b1 RJ |
245 | break; |
246 | ||
247 | case 2: | |
36b904a7 RJ |
248 | mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); |
249 | mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); | |
250 | mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); | |
692519b1 | 251 | mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); |
692519b1 RJ |
252 | break; |
253 | } | |
36b904a7 | 254 | utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); |
16850919 | 255 | |
692519b1 RJ |
256 | /* |
257 | * Set buffer allocations and then assert VRB and TXE. | |
258 | */ | |
259 | out_be32(utl_base + PEUTL_OUTTR, 0x08000000); | |
260 | out_be32(utl_base + PEUTL_INTR, 0x02000000); | |
261 | out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); | |
262 | out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); | |
263 | out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); | |
264 | out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); | |
265 | out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
36b904a7 | 266 | out_be32(utl_base + PEUTL_PCTL, 0x80800066); |
692519b1 RJ |
267 | } |
268 | ||
269 | static int check_error(void) | |
270 | { | |
271 | u32 valPE0, valPE1, valPE2; | |
272 | int err = 0; | |
273 | ||
274 | /* SDR0_PEGPLLLCT1 reset */ | |
275 | if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { | |
276 | printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); | |
277 | } | |
278 | ||
279 | valPE0 = SDR_READ(PESDR0_RCSSET); | |
280 | valPE1 = SDR_READ(PESDR1_RCSSET); | |
281 | valPE2 = SDR_READ(PESDR2_RCSSET); | |
282 | ||
283 | /* SDR0_PExRCSSET rstgu */ | |
284 | if (!(valPE0 & 0x01000000) || | |
285 | !(valPE1 & 0x01000000) || | |
286 | !(valPE2 & 0x01000000)) { | |
287 | printf("PCIE: SDR0_PExRCSSET rstgu error\n"); | |
288 | err = -1; | |
289 | } | |
290 | ||
291 | /* SDR0_PExRCSSET rstdl */ | |
292 | if (!(valPE0 & 0x00010000) || | |
293 | !(valPE1 & 0x00010000) || | |
294 | !(valPE2 & 0x00010000)) { | |
295 | printf("PCIE: SDR0_PExRCSSET rstdl error\n"); | |
296 | err = -1; | |
297 | } | |
298 | ||
299 | /* SDR0_PExRCSSET rstpyn */ | |
300 | if ((valPE0 & 0x00001000) || | |
301 | (valPE1 & 0x00001000) || | |
302 | (valPE2 & 0x00001000)) { | |
303 | printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
304 | err = -1; | |
305 | } | |
306 | ||
307 | /* SDR0_PExRCSSET hldplb */ | |
308 | if ((valPE0 & 0x10000000) || | |
309 | (valPE1 & 0x10000000) || | |
310 | (valPE2 & 0x10000000)) { | |
311 | printf("PCIE: SDR0_PExRCSSET hldplb error\n"); | |
312 | err = -1; | |
313 | } | |
314 | ||
315 | /* SDR0_PExRCSSET rdy */ | |
316 | if ((valPE0 & 0x00100000) || | |
317 | (valPE1 & 0x00100000) || | |
318 | (valPE2 & 0x00100000)) { | |
319 | printf("PCIE: SDR0_PExRCSSET rdy error\n"); | |
320 | err = -1; | |
321 | } | |
322 | ||
323 | /* SDR0_PExRCSSET shutdown */ | |
324 | if ((valPE0 & 0x00000100) || | |
325 | (valPE1 & 0x00000100) || | |
326 | (valPE2 & 0x00000100)) { | |
327 | printf("PCIE: SDR0_PExRCSSET shutdown error\n"); | |
328 | err = -1; | |
329 | } | |
330 | return err; | |
331 | } | |
332 | ||
333 | /* | |
334 | * Initialize PCI Express core | |
335 | */ | |
026f7110 | 336 | int ppc4xx_init_pcie(void) |
692519b1 RJ |
337 | { |
338 | int time_out = 20; | |
339 | ||
340 | /* Set PLL clock receiver to LVPECL */ | |
341 | SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); | |
342 | ||
343 | if (check_error()) | |
344 | return -1; | |
345 | ||
346 | if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) | |
347 | { | |
348 | printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", | |
349 | SDR_READ(PESDR0_PLLLCT2)); | |
350 | return -1; | |
351 | } | |
352 | /* De-assert reset of PCIe PLL, wait for lock */ | |
353 | SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); | |
354 | udelay(3); | |
355 | ||
2b393b0f | 356 | while (time_out) { |
692519b1 RJ |
357 | if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { |
358 | time_out--; | |
359 | udelay(1); | |
360 | } else | |
361 | break; | |
362 | } | |
363 | if (!time_out) { | |
364 | printf("PCIE: VCO output not locked\n"); | |
365 | return -1; | |
366 | } | |
367 | return 0; | |
368 | } | |
369 | ||
2b393b0f | 370 | /* |
03d344bb SR |
371 | * Board-specific pcie initialization |
372 | * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed | |
373 | */ | |
374 | ||
375 | /* | |
376 | * Initialize various parts of the PCI Express core for our port: | |
377 | * | |
378 | * - Set as a root port and enable max width | |
379 | * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). | |
380 | * - Set up UTL configuration. | |
381 | * - Increase SERDES drive strength to levels suggested by AMCC. | |
382 | * - De-assert RSTPYN, RSTDL and RSTGU. | |
383 | * | |
384 | * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it | |
385 | * with default setting 0x11310000. The register has new fields, | |
386 | * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core | |
387 | * hang. | |
388 | */ | |
389 | #if defined(CONFIG_440SPE) | |
390 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
391 | { | |
392 | u32 val = 1 << 24; | |
393 | u32 utlset1; | |
394 | ||
395 | if (rootport) { | |
396 | val = PTYPE_ROOT_PORT << 20; | |
397 | utlset1 = 0x21222222; | |
398 | } else { | |
399 | val = PTYPE_LEGACY_ENDPOINT << 20; | |
400 | utlset1 = 0x20222222; | |
401 | } | |
402 | ||
403 | if (port == 0) | |
404 | val |= LNKW_X8 << 12; | |
405 | else | |
406 | val |= LNKW_X4 << 12; | |
407 | ||
408 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
409 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); | |
410 | if (!ppc440spe_revB()) | |
411 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); | |
412 | SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); | |
413 | SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); | |
414 | SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); | |
415 | SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); | |
416 | if (port == 0) { | |
417 | SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); | |
418 | SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); | |
419 | SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); | |
420 | SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); | |
421 | } | |
422 | SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & | |
423 | ~(1 << 24 | 1 << 16)) | 1 << 12); | |
424 | ||
425 | return 0; | |
426 | } | |
427 | #endif /* CONFIG_440SPE */ | |
428 | ||
429 | #if defined(CONFIG_405EX) | |
430 | int __ppc4xx_init_pcie_port_hw(int port, int rootport) | |
431 | { | |
432 | u32 val; | |
433 | ||
94276eb0 SR |
434 | /* |
435 | * test-only: | |
436 | * This needs some testing and perhaps changes for | |
437 | * endpoint configuration. Probably no PHY reset at all, etc. | |
438 | * sr, 2007-10-03 | |
439 | */ | |
03d344bb SR |
440 | if (rootport) |
441 | val = 0x00401000; | |
442 | else | |
443 | val = 0x00101000; | |
444 | ||
445 | SDR_WRITE(SDRN_PESDR_DLPSET(port), val); | |
446 | SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x20222222); | |
447 | SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01110000); | |
448 | SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); | |
449 | SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); | |
450 | ||
451 | /* Assert the PE0_PHY reset */ | |
452 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); | |
453 | udelay(1000); | |
454 | ||
455 | /* deassert the PE0_hotreset */ | |
456 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); | |
457 | ||
458 | /* poll for phy !reset */ | |
459 | while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) | |
460 | ; | |
461 | ||
462 | /* deassert the PE0_gpl_utl_reset */ | |
463 | SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); | |
464 | ||
465 | if (port == 0) | |
466 | mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ | |
467 | else | |
468 | mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ | |
469 | ||
470 | return 0; | |
471 | } | |
472 | #endif /* CONFIG_405EX */ | |
473 | ||
474 | int ppc4xx_init_pcie_port_hw(int port, int rootport) | |
475 | __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); | |
476 | ||
477 | /* | |
478 | * We map PCI Express configuration access into the 512MB regions | |
479 | * | |
480 | * NOTICE: revB is very strict about PLB real addressess and ranges to | |
481 | * be mapped for config space; it seems to only work with d_nnnn_nnnn | |
482 | * range (hangs the core upon config transaction attempts when set | |
483 | * otherwise) while revA uses c_nnnn_nnnn. | |
484 | * | |
485 | * For revA: | |
486 | * PCIE0: 0xc_4000_0000 | |
487 | * PCIE1: 0xc_8000_0000 | |
488 | * PCIE2: 0xc_c000_0000 | |
489 | * | |
490 | * For revB: | |
491 | * PCIE0: 0xd_0000_0000 | |
492 | * PCIE1: 0xd_2000_0000 | |
493 | * PCIE2: 0xd_4000_0000 | |
494 | * | |
495 | * For 405EX: | |
496 | * PCIE0: 0xa000_0000 | |
497 | * PCIE1: 0xc000_0000 | |
498 | */ | |
499 | static inline u64 ppc4xx_get_cfgaddr(int port) | |
500 | { | |
501 | #if defined(CONFIG_405EX) | |
502 | if (port == 0) | |
503 | return (u64)CFG_PCIE0_CFGBASE; | |
504 | else | |
505 | return (u64)CFG_PCIE1_CFGBASE; | |
506 | #endif | |
507 | #if defined(CONFIG_440SPE) | |
508 | if (ppc440spe_revB()) { | |
509 | switch (port) { | |
510 | default: /* to satisfy compiler */ | |
511 | case 0: | |
512 | return 0x0000000d00000000ULL; | |
513 | case 1: | |
514 | return 0x0000000d20000000ULL; | |
515 | case 2: | |
516 | return 0x0000000d40000000ULL; | |
517 | } | |
518 | } else { | |
519 | switch (port) { | |
520 | default: /* to satisfy compiler */ | |
521 | case 0: | |
522 | return 0x0000000c40000000ULL; | |
523 | case 1: | |
524 | return 0x0000000c80000000ULL; | |
525 | case 2: | |
526 | return 0x0000000cc0000000ULL; | |
527 | } | |
528 | } | |
529 | #endif | |
530 | } | |
531 | ||
532 | /* | |
533 | * 4xx boards as end point and root point setup | |
2b393b0f SR |
534 | * and |
535 | * testing inbound and out bound windows | |
536 | * | |
03d344bb | 537 | * 4xx boards can be plugged into another 4xx boards or you can get PCI-E |
2b393b0f SR |
538 | * cable which can be used to setup loop back from one port to another port. |
539 | * Please rememeber that unless there is a endpoint plugged in to root port it | |
540 | * will not initialize. It is the same in case of endpoint , unless there is | |
541 | * root port attached it will not initialize. | |
542 | * | |
543 | * In this release of software all the PCI-E ports are configured as either | |
544 | * endpoint or rootpoint.In future we will have support for selective ports | |
545 | * setup as endpoint and root point in single board. | |
546 | * | |
547 | * Once your board came up as root point , you can verify by reading | |
548 | * /proc/bus/pci/devices. Where you can see the configuration registers | |
549 | * of end point device attached to the port. | |
550 | * | |
03d344bb SR |
551 | * Enpoint cofiguration can be verified by connecting 4xx board to any |
552 | * host or another 4xx board. Then try to scan the device. In case of | |
2b393b0f SR |
553 | * linux use "lspci" or appripriate os command. |
554 | * | |
03d344bb | 555 | * How do I verify the inbound and out bound windows ? (4xx to 4xx) |
2b393b0f SR |
556 | * in this configuration inbound and outbound windows are setup to access |
557 | * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address | |
558 | * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, | |
559 | * This is waere your POM(PLB out bound memory window) mapped. then | |
03d344bb | 560 | * read the data from other 4xx board's u-boot prompt at address |
2b393b0f SR |
561 | * 0x9000 0000(SRAM). Data should match. |
562 | * In case of inbound , write data to u-boot command prompt at 0xb000 0000 | |
563 | * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check | |
564 | * data at 0x9000 0000(SRAM).Data should match. | |
565 | */ | |
03d344bb | 566 | int ppc4xx_init_pcie_port(int port, int rootport) |
692519b1 RJ |
567 | { |
568 | static int core_init; | |
569 | volatile u32 val = 0; | |
570 | int attempts; | |
03d344bb SR |
571 | u64 addr; |
572 | u32 low, high; | |
692519b1 RJ |
573 | |
574 | if (!core_init) { | |
575 | ++core_init; | |
026f7110 | 576 | if (ppc4xx_init_pcie()) |
692519b1 RJ |
577 | return -1; |
578 | } | |
579 | ||
580 | /* | |
03d344bb | 581 | * Initialize various parts of the PCI Express core for our port |
692519b1 | 582 | */ |
03d344bb | 583 | ppc4xx_init_pcie_port_hw(port, rootport); |
692519b1 | 584 | |
2b393b0f SR |
585 | /* |
586 | * Notice: the following delay has critical impact on device | |
587 | * initialization - if too short (<50ms) the link doesn't get up. | |
588 | */ | |
589 | mdelay(100); | |
590 | ||
6d952892 | 591 | val = SDR_READ(SDRN_PESDR_RCSSTS(port)); |
2b393b0f SR |
592 | if (val & (1 << 20)) { |
593 | printf("PCIE%d: PGRST failed %08x\n", port, val); | |
594 | return -1; | |
595 | } | |
596 | ||
597 | /* | |
598 | * Verify link is up | |
599 | */ | |
6d952892 | 600 | val = SDR_READ(SDRN_PESDR_LOOP(port)); |
2b393b0f SR |
601 | if (!(val & 0x00001000)) { |
602 | printf("PCIE%d: link is not up.\n", port); | |
603 | return -1; | |
604 | } | |
605 | ||
606 | /* | |
607 | * Setup UTL registers - but only on revA! | |
608 | * We use default settings for revB chip. | |
609 | */ | |
610 | if (!ppc440spe_revB()) | |
026f7110 | 611 | ppc4xx_setup_utl(port); |
2b393b0f SR |
612 | |
613 | /* | |
614 | * We map PCI Express configuration access into the 512MB regions | |
2b393b0f | 615 | */ |
03d344bb SR |
616 | addr = ppc4xx_get_cfgaddr(port); |
617 | low = (u32)(addr & 0x00000000ffffffff); | |
618 | high = (u32)(addr >> 32); | |
2b393b0f SR |
619 | |
620 | switch (port) { | |
621 | case 0: | |
03d344bb SR |
622 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); |
623 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); | |
2b393b0f SR |
624 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ |
625 | break; | |
2b393b0f | 626 | case 1: |
03d344bb SR |
627 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); |
628 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); | |
2b393b0f SR |
629 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ |
630 | break; | |
2b393b0f | 631 | case 2: |
03d344bb SR |
632 | mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); |
633 | mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); | |
2b393b0f SR |
634 | mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ |
635 | break; | |
636 | } | |
637 | ||
638 | /* | |
639 | * Check for VC0 active and assert RDY. | |
640 | */ | |
641 | attempts = 10; | |
6d952892 | 642 | while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { |
03d344bb SR |
643 | if (!(attempts--)) { |
644 | printf("PCIE%d: VC0 not active\n", port); | |
645 | return -1; | |
2b393b0f | 646 | } |
03d344bb | 647 | mdelay(1000); |
2b393b0f | 648 | } |
6d952892 SR |
649 | SDR_WRITE(SDRN_PESDR_RCSSET(port), |
650 | SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); | |
2b393b0f SR |
651 | mdelay(100); |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
03d344bb | 656 | int ppc4xx_init_pcie_rootport(int port) |
2b393b0f | 657 | { |
03d344bb SR |
658 | return ppc4xx_init_pcie_port(port, 1); |
659 | } | |
692519b1 | 660 | |
03d344bb SR |
661 | int ppc4xx_init_pcie_endport(int port) |
662 | { | |
663 | return ppc4xx_init_pcie_port(port, 0); | |
692519b1 RJ |
664 | } |
665 | ||
026f7110 | 666 | void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) |
692519b1 RJ |
667 | { |
668 | volatile void *mbase = NULL; | |
2b393b0f | 669 | volatile void *rmbase = NULL; |
692519b1 RJ |
670 | |
671 | pci_set_ops(hose, | |
03d344bb SR |
672 | pcie_read_config_byte, |
673 | pcie_read_config_word, | |
674 | pcie_read_config_dword, | |
675 | pcie_write_config_byte, | |
676 | pcie_write_config_word, | |
677 | pcie_write_config_dword); | |
2b393b0f SR |
678 | |
679 | switch (port) { | |
692519b1 RJ |
680 | case 0: |
681 | mbase = (u32 *)CFG_PCIE0_XCFGBASE; | |
2b393b0f | 682 | rmbase = (u32 *)CFG_PCIE0_CFGBASE; |
692519b1 RJ |
683 | hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; |
684 | break; | |
685 | case 1: | |
686 | mbase = (u32 *)CFG_PCIE1_XCFGBASE; | |
2b393b0f | 687 | rmbase = (u32 *)CFG_PCIE1_CFGBASE; |
692519b1 RJ |
688 | hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; |
689 | break; | |
690 | case 2: | |
691 | mbase = (u32 *)CFG_PCIE2_XCFGBASE; | |
2b393b0f | 692 | rmbase = (u32 *)CFG_PCIE2_CFGBASE; |
692519b1 RJ |
693 | hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; |
694 | break; | |
695 | } | |
696 | ||
697 | /* | |
698 | * Set bus numbers on our root port | |
699 | */ | |
7f191393 GB |
700 | out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); |
701 | out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); | |
702 | out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); | |
692519b1 RJ |
703 | |
704 | /* | |
705 | * Set up outbound translation to hose->mem_space from PLB | |
706 | * addresses at an offset of 0xd_0000_0000. We set the low | |
707 | * bits of the mask to 11 to turn off splitting into 8 | |
708 | * subregions and to enable the outbound translation. | |
709 | */ | |
710 | out_le32(mbase + PECFG_POM0LAH, 0x00000000); | |
2b393b0f | 711 | out_le32(mbase + PECFG_POM0LAL, 0x00000000); |
692519b1 RJ |
712 | |
713 | switch (port) { | |
714 | case 0: | |
715 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); | |
716 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + | |
03d344bb | 717 | port * CFG_PCIE_MEMSIZE); |
692519b1 RJ |
718 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
719 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), | |
03d344bb | 720 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
692519b1 RJ |
721 | break; |
722 | case 1: | |
723 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); | |
03d344bb SR |
724 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + |
725 | port * CFG_PCIE_MEMSIZE); | |
692519b1 RJ |
726 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
727 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), | |
03d344bb | 728 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
692519b1 RJ |
729 | break; |
730 | case 2: | |
731 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); | |
03d344bb SR |
732 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + |
733 | port * CFG_PCIE_MEMSIZE); | |
692519b1 RJ |
734 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
735 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), | |
03d344bb | 736 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
692519b1 RJ |
737 | break; |
738 | } | |
739 | ||
740 | /* Set up 16GB inbound memory window at 0 */ | |
741 | out_le32(mbase + PCI_BASE_ADDRESS_0, 0); | |
742 | out_le32(mbase + PCI_BASE_ADDRESS_1, 0); | |
743 | out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); | |
744 | out_le32(mbase + PECFG_BAR0LMPA, 0); | |
2b393b0f SR |
745 | |
746 | out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); | |
747 | out_le32(mbase + PECFG_PIM01SAL, 0x00000000); | |
692519b1 RJ |
748 | out_le32(mbase + PECFG_PIM0LAL, 0); |
749 | out_le32(mbase + PECFG_PIM0LAH, 0); | |
2b393b0f SR |
750 | out_le32(mbase + PECFG_PIM1LAL, 0x00000000); |
751 | out_le32(mbase + PECFG_PIM1LAH, 0x00000004); | |
752 | out_le32(mbase + PECFG_PIMEN, 0x1); | |
753 | ||
754 | /* Enable I/O, Mem, and Busmaster cycles */ | |
755 | out_le16((u16 *)(mbase + PCI_COMMAND), | |
756 | in_le16((u16 *)(mbase + PCI_COMMAND)) | | |
757 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
738815c0 | 758 | |
7f191393 GB |
759 | /* Set Device and Vendor Id */ |
760 | switch (port) { | |
761 | case 0: | |
762 | out_le16(mbase + 0x200, 0xaaa0); | |
763 | out_le16(mbase + 0x202, 0xbed0); | |
764 | break; | |
765 | case 1: | |
766 | out_le16(mbase + 0x200, 0xaaa1); | |
767 | out_le16(mbase + 0x202, 0xbed1); | |
768 | break; | |
769 | case 2: | |
770 | out_le16(mbase + 0x200, 0xaaa2); | |
771 | out_le16(mbase + 0x202, 0xbed2); | |
772 | break; | |
773 | default: | |
774 | out_le16(mbase + 0x200, 0xaaa3); | |
775 | out_le16(mbase + 0x202, 0xbed3); | |
776 | } | |
777 | ||
778 | /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ | |
779 | out_le32(mbase + 0x208, 0x06040001); | |
780 | ||
03d344bb | 781 | printf("PCIE:%d successfully set as rootpoint\n", port); |
2b393b0f SR |
782 | } |
783 | ||
026f7110 | 784 | int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) |
2b393b0f SR |
785 | { |
786 | volatile void *mbase = NULL; | |
787 | int attempts = 0; | |
788 | ||
789 | pci_set_ops(hose, | |
790 | pcie_read_config_byte, | |
791 | pcie_read_config_word, | |
792 | pcie_read_config_dword, | |
793 | pcie_write_config_byte, | |
794 | pcie_write_config_word, | |
795 | pcie_write_config_dword); | |
796 | ||
797 | switch (port) { | |
798 | case 0: | |
799 | mbase = (u32 *)CFG_PCIE0_XCFGBASE; | |
800 | hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; | |
801 | break; | |
802 | case 1: | |
803 | mbase = (u32 *)CFG_PCIE1_XCFGBASE; | |
804 | hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; | |
805 | break; | |
806 | case 2: | |
807 | mbase = (u32 *)CFG_PCIE2_XCFGBASE; | |
808 | hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; | |
809 | break; | |
810 | } | |
811 | ||
812 | /* | |
813 | * Set up outbound translation to hose->mem_space from PLB | |
814 | * addresses at an offset of 0xd_0000_0000. We set the low | |
815 | * bits of the mask to 11 to turn off splitting into 8 | |
816 | * subregions and to enable the outbound translation. | |
817 | */ | |
818 | out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); | |
819 | out_le32(mbase + PECFG_POM0LAL, 0x00001000); | |
820 | ||
821 | switch (port) { | |
822 | case 0: | |
823 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); | |
824 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + | |
03d344bb | 825 | port * CFG_PCIE_MEMSIZE); |
2b393b0f SR |
826 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); |
827 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), | |
03d344bb | 828 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
2b393b0f SR |
829 | break; |
830 | case 1: | |
831 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); | |
03d344bb SR |
832 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + |
833 | port * CFG_PCIE_MEMSIZE); | |
2b393b0f SR |
834 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); |
835 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), | |
03d344bb | 836 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
2b393b0f SR |
837 | break; |
838 | case 2: | |
839 | mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); | |
03d344bb SR |
840 | mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + |
841 | port * CFG_PCIE_MEMSIZE); | |
2b393b0f SR |
842 | mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); |
843 | mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), | |
03d344bb | 844 | ~(CFG_PCIE_MEMSIZE - 1) | 3); |
2b393b0f SR |
845 | break; |
846 | } | |
847 | ||
848 | /* Set up 16GB inbound memory window at 0 */ | |
849 | out_le32(mbase + PCI_BASE_ADDRESS_0, 0); | |
850 | out_le32(mbase + PCI_BASE_ADDRESS_1, 0); | |
851 | out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); | |
852 | out_le32(mbase + PECFG_BAR0LMPA, 0); | |
853 | out_le32(mbase + PECFG_PIM0LAL, 0x00000000); | |
854 | out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ | |
692519b1 RJ |
855 | out_le32(mbase + PECFG_PIMEN, 0x1); |
856 | ||
857 | /* Enable I/O, Mem, and Busmaster cycles */ | |
858 | out_le16((u16 *)(mbase + PCI_COMMAND), | |
03d344bb SR |
859 | in_le16((u16 *)(mbase + PCI_COMMAND)) | |
860 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
2b393b0f SR |
861 | out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ |
862 | out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ | |
03d344bb | 863 | |
2b393b0f | 864 | attempts = 10; |
6d952892 | 865 | while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { |
03d344bb SR |
866 | if (!(attempts--)) { |
867 | printf("PCIE%d: BME not active\n", port); | |
868 | return -1; | |
2b393b0f | 869 | } |
03d344bb | 870 | mdelay(1000); |
2b393b0f | 871 | } |
03d344bb | 872 | |
2b393b0f SR |
873 | printf("PCIE:%d successfully set as endpoint\n",port); |
874 | ||
875 | return 0; | |
692519b1 | 876 | } |
5fb692ca | 877 | #endif /* CONFIG_440SPE && CONFIG_PCI */ |