[people/ms/u-boot.git] / cpu / ppc4xx / cpu.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <damm@bitsmart.com>
 *
 * minor modifications by
 * Wolfgang Denk <wd@denx.de>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

void board_reset(void);

/*
 * To provide an interface to detect CPU number for boards that support
 * more then one CPU, we implement the "weak" default functions here.
 *
 * Returns CPU number
 */
int __get_cpu_num(void)
{
	return NA_OR_UNKNOWN_CPU;
}
int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));

#if defined(CONFIG_PCI)
#if defined(CONFIG_405GP) || \
    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)

#define PCI_ASYNC

static int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	unsigned long val;

	mfsdr(SDR0_SDSTP1, val);
	return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif
#endif /* CONFIG_PCI */

#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
    !defined(CONFIG_405) && !defined(CONFIG_405EX)
static int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_405EP)
	return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_440GP)
	return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	unsigned long val;

	mfsdr(SDR0_XCR, val);
	return (val & 0x80000000);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	unsigned long val;

	mfsdr(SDR0_PCI0, val);
	return (val & 0x80000000);
#endif
}
#endif

#if defined(CONFIG_405EP)
#define I2C_BOOTROM

static int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
	return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
#else
	unsigned long val;

	mfsdr(SDR0_SDCS0, val);
	return (val & SDR0_SDCS_SDD);
#endif
}
#endif

#if defined(CONFIG_440GX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (16 bits)",
	"EBC (8 bits)",
	"EBC (32 bits)",
	"EBC (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"Reserved",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
#endif

#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define SDR0_PINSTP_SHIFT	30
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"PCI",
	"NAND (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"I2C (Addr 0x54)",
	"PCI",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"PCI",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"PCI",
	"PCI",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",	/* A8 */
	"I2C (Addr 0x52)",	/* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_460SX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (32 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",      /* A8 */
	"I2C (Addr 0x52)",      /* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
#endif

#if defined(CONFIG_405EZ)
#define SDR0_PINSTP_SHIFT	28
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"SPI (fast)",
	"NAND (512 page, 4 addr cycle)",
	"I2C (Addr 0x50)",
	"EBC (32 bits)",
	"I2C (Addr 0x50)",
	"NAND (2K page, 5 addr cycle)",
	"I2C (Addr 0x50)",
	"EBC (16 bits)",
	"Reserved",
	"NAND (2K page, 4 addr cycle)",
	"I2C (Addr 0x50)",
	"NAND (512 page, 3 addr cycle)",
	"I2C (Addr 0x50)",
	"SPI (slow)",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
				 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
#endif

#if defined(CONFIG_405EX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",
	"EBC (8 bits)",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
{
	unsigned long val;

	mfsdr(SDR0_PINSTP, val);
	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
}
#endif /* SDR0_PINSTP_SHIFT */


#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
	 * reset.
	 */
	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);	/* Set SWE */
	mtdcr (CPC0_SYS0, sys0);
	mtdcr (CPC0_SYS1, sys1);
	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);	/* Clr SWE */
	mtspr (SPRN_DBCR0, 0x20000000);	/* Reset the chip */

	return 1;
}
#endif


int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	u32 reg;
#endif

#if !defined(CONFIG_IOP480)
	char addstr[64] = "";
	sys_info_t sys_info;
	int cpu_num;

	cpu_num = get_cpu_num();
	if (cpu_num >= 0)
		printf("CPU%d:  ", cpu_num);
	else
		puts("CPU:   ");

	get_sys_info(&sys_info);

#if defined(CONFIG_XILINX_440)
	puts("IBM PowerPC 4");
#else
	puts("AMCC PowerPC 4");
#endif

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
    defined(CONFIG_405EX)
	puts("05");
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	puts("60");
#else
	puts("40");
#endif
#endif

	switch (pvr) {
	case PVR_405GP_RB:
		puts("GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("GP Rev. D");
		break;

#ifdef CONFIG_405GP
	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
		puts("GP Rev. E");
		break;
#endif

	case PVR_405CR_RA:
		puts("CR Rev. A");
		break;

	case PVR_405CR_RB:
		puts("CR Rev. B");
		break;

#ifdef CONFIG_405CR
	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
		puts("CR Rev. C");
		break;
#endif

	case PVR_405GPR_RB:
		puts("GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("EP Rev. B");
		break;

	case PVR_405EZ_RA:
		puts("EZ Rev. A");
		break;

	case PVR_405EX1_RA:
		puts("EX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RA:
		puts("EX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RA:
		puts("EXr Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RA:
		puts("EXr Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EX1_RC:
		puts("EX Rev. C");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RC:
		puts("EX Rev. C");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RC:
		puts("EXr Rev. C");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RC:
		puts("EXr Rev. C");
		strcpy(addstr, "No Security support");
		break;

#if defined(CONFIG_440)
	case PVR_440GP_RB:
		puts("GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
		    (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
			do_chip_reset ( mfdcr(CPC0_STRP0),
					mfdcr(CPC0_STRP1) );
		}
		break;

	case PVR_440GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_440GX_RA:
		puts("GX Rev. A");
		break;

	case PVR_440GX_RB:
		puts("GX Rev. B");
		break;

	case PVR_440GX_RC:
		puts("GX Rev. C");
		break;

	case PVR_440GX_RF:
		puts("GX Rev. F");
		break;

	case PVR_440EP_RA:
		puts("EP Rev. A");
		break;

#ifdef CONFIG_440EP
	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
		puts("EP Rev. B");
		break;

	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
		puts("EP Rev. C");
		break;
#endif /*  CONFIG_440EP */

#ifdef CONFIG_440GR
	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
		puts("GR Rev. A");
		break;

	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
		puts("GR Rev. B");
		break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */

#ifdef CONFIG_440EPX
	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("EPx Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("EPx Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;
#endif /* CONFIG_440EPX */

#ifdef CONFIG_440GRX
	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("GRx Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("GRx Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;
#endif /* CONFIG_440GRX */

	case PVR_440SP_6_RAB:
		puts("SP Rev. A/B");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SP_RAB:
		puts("SP Rev. A/B");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SP_6_RC:
		puts("SP Rev. C");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SP_RC:
		puts("SP Rev. C");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SPe_6_RA:
		puts("SPe Rev. A");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SPe_RA:
		puts("SPe Rev. A");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SPe_6_RB:
		puts("SPe Rev. B");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SPe_RB:
		puts("SPe Rev. B");
		strcpy(addstr, "No RAID 6 support");
		break;

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	case PVR_460EX_RA:
		puts("EX Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;

	case PVR_460EX_SE_RA:
		puts("EX Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460EX_RB:
		puts("EX Rev. B");
		mfsdr(SDR0_ECID3, reg);
		if (reg & 0x00100000)
			strcpy(addstr, "No Security/Kasumi support");
		else
			strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460GT_RA:
		puts("GT Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;

	case PVR_460GT_SE_RA:
		puts("GT Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460GT_RB:
		puts("GT Rev. B");
		mfsdr(SDR0_ECID3, reg);
		if (reg & 0x00100000)
			strcpy(addstr, "No Security/Kasumi support");
		else
			strcpy(addstr, "Security/Kasumi support");
		break;
#endif

	case PVR_460SX_RA:
		puts("SX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_460SX_RA_V1:
		puts("SX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_460GX_RA:
		puts("GX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_460GX_RA_V1:
		puts("GX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_VIRTEX5:
		puts("x5 VIRTEX5");
		break;

	default:
		printf (" UNKNOWN (PVR=%08x)", pvr);
		break;
	}

	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
		sys_info.freqPLB / 1000000,
		get_OPB_freq() / 1000000,
		sys_info.freqEBC / 1000000);

	if (addstr[0] != 0)
		printf("       %s\n", addstr);

#if defined(I2C_BOOTROM)
	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif	/* I2C_BOOTROM */
#if defined(SDR0_PINSTP_SHIFT)
	printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
	printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
#ifdef CONFIG_NAND_U_BOOT
	puts(", booting from NAND");
#endif /* CONFIG_NAND_U_BOOT */
	putc('\n');
#endif	/* SDR0_PINSTP_SHIFT */

#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif

#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
	if (pci_async_enabled()) {
		printf (", PCI async ext clock used");
	} else {
		printf (", PCI sync clock at %lu MHz",
		       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
	putc('\n');
#endif

#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
	printf ("       16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
	printf ("       32 kB I-Cache 32 kB D-Cache");
#else
	printf ("       16 kB I-Cache %d kB D-Cache",
		((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */

#if defined(CONFIG_IOP480)
	printf ("PLX IOP480 (PVR=%08x)", pvr);
	printf (" at %s MHz:", strmhz(buf, clock));
	printf (" %u kB I-Cache", 4);
	printf (" %u kB D-Cache", 2);
#endif

#endif /* !defined(CONFIG_405) */

	putc ('\n');

	return 0;
}

int ppc440spe_revB() {
	unsigned int pvr;

	pvr = get_pvr();
	if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
		return 1;
	else
		return 0;
}

/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_BOARD_RESET)
	board_reset();
#else
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
	mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
#else
	/*
	 * Initiate system reset in debug control register DBCR
	 */
	mtspr(SPRN_DBCR0, 0x30000000);
#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
#endif /* defined(CONFIG_BOARD_RESET) */

	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
#if !defined(CONFIG_IOP480)
	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return (sys_info.freqProcessor);
#else
	return (66000000);
#endif

}


#if defined(CONFIG_WATCHDOG)
void watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_4xx_watchdog();
	if (re_enable) enable_interrupts();
}

void reset_4xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit
	 */
	mtspr(SPRN_TSR, 0x40000000);
}
#endif	/* CONFIG_WATCHDOG */

/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_PPC4xx_EMAC)
	ppc_4xx_eth_initialize(bis);
#endif
	return 0;
}
Commit	Line	Data
c609719b	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
c609719b WD	25	* CPU specific code
	26	*
	27	* written or collected and sometimes rewritten by
	28	* Magnus Damm <damm@bitsmart.com>
	29	*
	30	* minor modifications by
	31	* Wolfgang Denk <wd@denx.de>
	32	*/
	33
	34	#include <common.h>
	35	#include <watchdog.h>
	36	#include <command.h>
	37	#include <asm/cache.h>
	38	#include <ppc4xx.h>
25a85906	39	#include <netdev.h>
c609719b	40
d87080b7	41	DECLARE_GLOBAL_DATA_PTR;
d87080b7	42
f3443867	43	void board_reset(void);
f3443867	44
c9c11d75 AG	45	/*
	46	* To provide an interface to detect CPU number for boards that support
	47	* more then one CPU, we implement the "weak" default functions here.
	48	*
	49	* Returns CPU number
	50	*/
	51	int __get_cpu_num(void)
	52	{
	53	return NA_OR_UNKNOWN_CPU;
	54	}
	55	int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
	56
20b3c4b5	57	#if defined(CONFIG_PCI)
887e2ec9 SR	58	#if defined(CONFIG_405GP) \|\| \
	59	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
	60	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
6e7fb6ea SR	61
	62	#define PCI_ASYNC
	63
c7f69c34	64	static int pci_async_enabled(void)
6e7fb6ea SR	65	{
6e7fb6ea SR	66	#if defined(CONFIG_405GP)
d1c3b275	67	return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
3d9569b2 SR	68	#endif
3d9569b2 SR	69
887e2ec9	70	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
2801b2d2 SR	71	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
2801b2d2 SR	72	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
6e7fb6ea SR	73	unsigned long val;
6e7fb6ea SR	74
d1c3b275	75	mfsdr(SDR0_SDSTP1, val);
6e7fb6ea SR	76	return (val & SDR0_SDSTP1_PAME_MASK);
	77	#endif
	78	}
	79	#endif
20b3c4b5	80	#endif /* CONFIG_PCI */
6e7fb6ea	81
dbbd1257 SR	82	#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
dbbd1257 SR	83	!defined(CONFIG_405) && !defined(CONFIG_405EX)
c7f69c34	84	static int pci_arbiter_enabled(void)
6e7fb6ea SR	85	{
6e7fb6ea SR	86	#if defined(CONFIG_405GP)
d1c3b275	87	return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
6e7fb6ea	88	#endif
3d9569b2	89
6e7fb6ea	90	#if defined(CONFIG_405EP)
d1c3b275	91	return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
3d9569b2 SR	92	#endif
	93
	94	#if defined(CONFIG_440GP)
d1c3b275	95	return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
6e7fb6ea SR	96	#endif
6e7fb6ea SR	97
7372ca68	98	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
6e7fb6ea	99	unsigned long val;
3d9569b2	100
d1c3b275	101	mfsdr(SDR0_XCR, val);
7372ca68 SR	102	return (val & 0x80000000);
	103	#endif
	104	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
2801b2d2 SR	105	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
2801b2d2 SR	106	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
7372ca68 SR	107	unsigned long val;
7372ca68 SR	108
d1c3b275	109	mfsdr(SDR0_PCI0, val);
7372ca68	110	return (val & 0x80000000);
3d9569b2	111	#endif
6e7fb6ea SR	112	}
	113	#endif
	114
c7f69c34	115	#if defined(CONFIG_405EP)
6e7fb6ea	116	#define I2C_BOOTROM
3d9569b2	117
c7f69c34	118	static int i2c_bootrom_enabled(void)
6e7fb6ea SR	119	{
6e7fb6ea SR	120	#if defined(CONFIG_405EP)
d1c3b275	121	return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
887e2ec9	122	#else
6e7fb6ea SR	123	unsigned long val;
6e7fb6ea SR	124
d1c3b275	125	mfsdr(SDR0_SDCS0, val);
6e7fb6ea SR	126	return (val & SDR0_SDCS_SDD);
	127	#endif
	128	}
90e6f41c	129	#endif
887e2ec9 SR	130
	131	#if defined(CONFIG_440GX)
	132	#define SDR0_PINSTP_SHIFT 29
	133	static char *bootstrap_str[] = {
	134	"EBC (16 bits)",
	135	"EBC (8 bits)",
	136	"EBC (32 bits)",
	137	"EBC (8 bits)",
	138	"PCI",
	139	"I2C (Addr 0x54)",
	140	"Reserved",
	141	"I2C (Addr 0x50)",
	142	};
e3cbe1f9	143	static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
887e2ec9 SR	144	#endif
	145
	146	#if defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
	147	#define SDR0_PINSTP_SHIFT 30
	148	static char *bootstrap_str[] = {
	149	"EBC (8 bits)",
	150	"PCI",
	151	"I2C (Addr 0x54)",
	152	"I2C (Addr 0x50)",
	153	};
e3cbe1f9	154	static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
887e2ec9 SR	155	#endif
	156
	157	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	158	#define SDR0_PINSTP_SHIFT 29
	159	static char *bootstrap_str[] = {
	160	"EBC (8 bits)",
	161	"PCI",
	162	"NAND (8 bits)",
	163	"EBC (16 bits)",
	164	"EBC (16 bits)",
	165	"I2C (Addr 0x54)",
	166	"PCI",
	167	"I2C (Addr 0x52)",
	168	};
e3cbe1f9	169	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9 SR	170	#endif
	171
	172	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	173	#define SDR0_PINSTP_SHIFT 29
	174	static char *bootstrap_str[] = {
	175	"EBC (8 bits)",
	176	"EBC (16 bits)",
	177	"EBC (16 bits)",
	178	"NAND (8 bits)",
	179	"PCI",
	180	"I2C (Addr 0x54)",
	181	"PCI",
	182	"I2C (Addr 0x52)",
	183	};
e3cbe1f9	184	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9 SR	185	#endif
887e2ec9 SR	186
2801b2d2 SR	187	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	188	#define SDR0_PINSTP_SHIFT 29
	189	static char *bootstrap_str[] = {
	190	"EBC (8 bits)",
	191	"EBC (16 bits)",
	192	"PCI",
	193	"PCI",
	194	"EBC (16 bits)",
	195	"NAND (8 bits)",
	196	"I2C (Addr 0x54)", /* A8 */
	197	"I2C (Addr 0x52)", /* A4 */
	198	};
	199	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
	200	#endif
	201
7d307936 FK	202	#if defined(CONFIG_460SX)
	203	#define SDR0_PINSTP_SHIFT 29
	204	static char *bootstrap_str[] = {
	205	"EBC (8 bits)",
	206	"EBC (16 bits)",
	207	"EBC (32 bits)",
	208	"NAND (8 bits)",
	209	"I2C (Addr 0x54)", /* A8 */
	210	"I2C (Addr 0x52)", /* A4 */
	211	};
	212	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
	213	#endif
	214
90e6f41c SR	215	#if defined(CONFIG_405EZ)
	216	#define SDR0_PINSTP_SHIFT 28
	217	static char *bootstrap_str[] = {
	218	"EBC (8 bits)",
	219	"SPI (fast)",
	220	"NAND (512 page, 4 addr cycle)",
	221	"I2C (Addr 0x50)",
	222	"EBC (32 bits)",
	223	"I2C (Addr 0x50)",
	224	"NAND (2K page, 5 addr cycle)",
	225	"I2C (Addr 0x50)",
	226	"EBC (16 bits)",
	227	"Reserved",
	228	"NAND (2K page, 4 addr cycle)",
	229	"I2C (Addr 0x50)",
	230	"NAND (512 page, 3 addr cycle)",
	231	"I2C (Addr 0x50)",
	232	"SPI (slow)",
	233	"I2C (Addr 0x50)",
	234	};
e3cbe1f9 BM	235	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
e3cbe1f9 BM	236	'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
90e6f41c SR	237	#endif
90e6f41c SR	238
dbbd1257 SR	239	#if defined(CONFIG_405EX)
	240	#define SDR0_PINSTP_SHIFT 29
	241	static char *bootstrap_str[] = {
	242	"EBC (8 bits)",
	243	"EBC (16 bits)",
	244	"EBC (16 bits)",
	245	"NAND (8 bits)",
	246	"NAND (8 bits)",
	247	"I2C (Addr 0x54)",
	248	"EBC (8 bits)",
	249	"I2C (Addr 0x52)",
	250	};
	251	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
	252	#endif
	253
887e2ec9 SR	254	#if defined(SDR0_PINSTP_SHIFT)
	255	static int bootstrap_option(void)
	256	{
	257	unsigned long val;
	258
d1c3b275	259	mfsdr(SDR0_PINSTP, val);
90e6f41c	260	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
887e2ec9 SR	261	}
887e2ec9 SR	262	#endif /* SDR0_PINSTP_SHIFT */
3d9569b2 SR	263
3d9569b2 SR	264
c609719b	265	#if defined(CONFIG_440)
c7f69c34 SR	266	static int do_chip_reset (unsigned long sys0, unsigned long sys1)
c7f69c34 SR	267	{
d1c3b275	268	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
c7f69c34 SR	269	* reset.
c7f69c34 SR	270	*/
d1c3b275 SR	271	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) \| 0x80000000); /* Set SWE */
	272	mtdcr (CPC0_SYS0, sys0);
	273	mtdcr (CPC0_SYS1, sys1);
	274	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
58ea142f	275	mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
c7f69c34 SR	276
	277	return 1;
	278	}
c609719b WD	279	#endif
c609719b WD	280
c609719b WD	281
	282	int checkcpu (void)
	283	{
3d9569b2	284	#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
3d9569b2	285	uint pvr = get_pvr();
c609719b WD	286	ulong clock = gd->cpu_clk;
c609719b WD	287	char buf[32];
89bcc487 SR	288	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	289	u32 reg;
	290	#endif
c609719b	291
3d9569b2	292	#if !defined(CONFIG_IOP480)
ba999c53	293	char addstr[64] = "";
3d9569b2	294	sys_info_t sys_info;
c9c11d75	295	int cpu_num;
c609719b	296
c9c11d75 AG	297	cpu_num = get_cpu_num();
	298	if (cpu_num >= 0)
	299	printf("CPU%d: ", cpu_num);
	300	else
	301	puts("CPU: ");
c609719b WD	302
	303	get_sys_info(&sys_info);
	304
d865fd09 RR	305	#if defined(CONFIG_XILINX_440)
	306	puts("IBM PowerPC 4");
	307	#else
3d9569b2	308	puts("AMCC PowerPC 4");
d865fd09	309	#endif
3d9569b2	310
e01bd218	311	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| \
dbbd1257 SR	312	defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| \
dbbd1257 SR	313	defined(CONFIG_405EX)
3d9569b2	314	puts("05");
b867d705	315	#endif
3d9569b2	316	#if defined(CONFIG_440)
2801b2d2 SR	317	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	318	puts("60");
	319	#else
3d9569b2	320	puts("40");
2801b2d2	321	#endif
c609719b	322	#endif
3d9569b2	323
c609719b WD	324	switch (pvr) {
c609719b WD	325	case PVR_405GP_RB:
3d9569b2	326	puts("GP Rev. B");
c609719b	327	break;
3d9569b2	328
c609719b	329	case PVR_405GP_RC:
3d9569b2	330	puts("GP Rev. C");
c609719b	331	break;
3d9569b2	332
c609719b	333	case PVR_405GP_RD:
3d9569b2	334	puts("GP Rev. D");
c609719b	335	break;
3d9569b2	336
42dfe7a1	337	#ifdef CONFIG_405GP
3d9569b2 SR	338	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
3d9569b2 SR	339	puts("GP Rev. E");
c609719b WD	340	break;
c609719b WD	341	#endif
3d9569b2	342
c609719b	343	case PVR_405CR_RA:
3d9569b2	344	puts("CR Rev. A");
c609719b	345	break;
3d9569b2	346
c609719b	347	case PVR_405CR_RB:
3d9569b2	348	puts("CR Rev. B");
c609719b	349	break;
c609719b	350
3d9569b2 SR	351	#ifdef CONFIG_405CR
	352	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
	353	puts("CR Rev. C");
	354	break;
c609719b WD	355	#endif
c609719b WD	356
3d9569b2 SR	357	case PVR_405GPR_RB:
	358	puts("GPr Rev. B");
	359	break;
c609719b	360
3d9569b2 SR	361	case PVR_405EP_RB:
	362	puts("EP Rev. B");
	363	break;
c609719b	364
e01bd218 SR	365	case PVR_405EZ_RA:
	366	puts("EZ Rev. A");
	367	break;
	368
dbbd1257 SR	369	case PVR_405EX1_RA:
	370	puts("EX Rev. A");
	371	strcpy(addstr, "Security support");
	372	break;
	373
	374	case PVR_405EX2_RA:
	375	puts("EX Rev. A");
	376	strcpy(addstr, "No Security support");
	377	break;
	378
	379	case PVR_405EXR1_RA:
	380	puts("EXr Rev. A");
	381	strcpy(addstr, "Security support");
	382	break;
	383
	384	case PVR_405EXR2_RA:
	385	puts("EXr Rev. A");
	386	strcpy(addstr, "No Security support");
	387	break;
	388
70fab190 SR	389	case PVR_405EX1_RC:
	390	puts("EX Rev. C");
	391	strcpy(addstr, "Security support");
	392	break;
	393
	394	case PVR_405EX2_RC:
	395	puts("EX Rev. C");
	396	strcpy(addstr, "No Security support");
	397	break;
	398
	399	case PVR_405EXR1_RC:
	400	puts("EXr Rev. C");
	401	strcpy(addstr, "Security support");
	402	break;
	403
	404	case PVR_405EXR2_RC:
	405	puts("EXr Rev. C");
	406	strcpy(addstr, "No Security support");
	407	break;
	408
c609719b	409	#if defined(CONFIG_440)
8bde7f77	410	case PVR_440GP_RB:
c157d8e2	411	puts("GP Rev. B");
4d816774	412	/* See errata 1.12: CHIP_4 */
d1c3b275 SR	413	if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) \|\|
d1c3b275 SR	414	(mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
4d816774 WD	415	puts ( "\n\t CPC0_SYSx DCRs corrupted. "
	416	"Resetting chip ...\n");
	417	udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
d1c3b275 SR	418	do_chip_reset ( mfdcr(CPC0_STRP0),
d1c3b275 SR	419	mfdcr(CPC0_STRP1) );
4d816774	420	}
c609719b	421	break;
3d9569b2	422
8bde7f77	423	case PVR_440GP_RC:
c157d8e2	424	puts("GP Rev. C");
ba56f625	425	break;
3d9569b2	426
ba56f625	427	case PVR_440GX_RA:
c157d8e2	428	puts("GX Rev. A");
ba56f625	429	break;
3d9569b2	430
ba56f625	431	case PVR_440GX_RB:
c157d8e2	432	puts("GX Rev. B");
c609719b	433	break;
3d9569b2	434
0a7c5391	435	case PVR_440GX_RC:
c157d8e2	436	puts("GX Rev. C");
0a7c5391	437	break;
3d9569b2	438
57275b69 SR	439	case PVR_440GX_RF:
	440	puts("GX Rev. F");
	441	break;
3d9569b2	442
c157d8e2 SR	443	case PVR_440EP_RA:
	444	puts("EP Rev. A");
	445	break;
3d9569b2	446
9a8d82fd SR	447	#ifdef CONFIG_440EP
9a8d82fd SR	448	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
c157d8e2 SR	449	puts("EP Rev. B");
c157d8e2 SR	450	break;
512f8d5d SR	451
	452	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
	453	puts("EP Rev. C");
	454	break;
9a8d82fd	455	#endif /* CONFIG_440EP */
3d9569b2	456
9a8d82fd SR	457	#ifdef CONFIG_440GR
	458	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
	459	puts("GR Rev. A");
	460	break;
512f8d5d	461
5770a1e4	462	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
512f8d5d SR	463	puts("GR Rev. B");
512f8d5d SR	464	break;
9a8d82fd	465	#endif /* CONFIG_440GR */
3d9569b2 SR	466	#endif /* CONFIG_440 */
3d9569b2 SR	467
2902fada SR	468	#ifdef CONFIG_440EPX
2902fada SR	469	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	470	puts("EPx Rev. A");
edf0b543 SR	471	strcpy(addstr, "Security/Kasumi support");
887e2ec9 SR	472	break;
887e2ec9 SR	473
2902fada	474	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	475	puts("EPx Rev. A");
edf0b543 SR	476	strcpy(addstr, "No Security/Kasumi support");
887e2ec9	477	break;
2902fada	478	#endif /* CONFIG_440EPX */
887e2ec9	479
2902fada SR	480	#ifdef CONFIG_440GRX
2902fada SR	481	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	482	puts("GRx Rev. A");
edf0b543 SR	483	strcpy(addstr, "Security/Kasumi support");
887e2ec9 SR	484	break;
887e2ec9 SR	485
2902fada	486	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
edf0b543 SR	487	puts("GRx Rev. A");
edf0b543 SR	488	strcpy(addstr, "No Security/Kasumi support");
887e2ec9	489	break;
2902fada	490	#endif /* CONFIG_440GRX */
887e2ec9	491
95981778 SR	492	case PVR_440SP_6_RAB:
	493	puts("SP Rev. A/B");
	494	strcpy(addstr, "RAID 6 support");
6e7fb6ea SR	495	break;
6e7fb6ea SR	496
95981778 SR	497	case PVR_440SP_RAB:
	498	puts("SP Rev. A/B");
	499	strcpy(addstr, "No RAID 6 support");
	500	break;
	501
	502	case PVR_440SP_6_RC:
	503	puts("SP Rev. C");
	504	strcpy(addstr, "RAID 6 support");
6e7fb6ea SR	505	break;
6e7fb6ea SR	506
e732faec SR	507	case PVR_440SP_RC:
e732faec SR	508	puts("SP Rev. C");
95981778 SR	509	strcpy(addstr, "No RAID 6 support");
	510	break;
	511
	512	case PVR_440SPe_6_RA:
	513	puts("SPe Rev. A");
	514	strcpy(addstr, "RAID 6 support");
e732faec SR	515	break;
e732faec SR	516
6c5879f3	517	case PVR_440SPe_RA:
fe84b48a	518	puts("SPe Rev. A");
95981778 SR	519	strcpy(addstr, "No RAID 6 support");
	520	break;
	521
	522	case PVR_440SPe_6_RB:
	523	puts("SPe Rev. B");
	524	strcpy(addstr, "RAID 6 support");
6c5879f3	525	break;
fe84b48a	526
6c5879f3	527	case PVR_440SPe_RB:
fe84b48a	528	puts("SPe Rev. B");
95981778	529	strcpy(addstr, "No RAID 6 support");
6c5879f3	530	break;
fe84b48a	531
89bcc487	532	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
2801b2d2 SR	533	case PVR_460EX_RA:
	534	puts("EX Rev. A");
	535	strcpy(addstr, "No Security/Kasumi support");
	536	break;
	537
	538	case PVR_460EX_SE_RA:
	539	puts("EX Rev. A");
	540	strcpy(addstr, "Security/Kasumi support");
	541	break;
	542
89bcc487 SR	543	case PVR_460EX_RB:
	544	puts("EX Rev. B");
	545	mfsdr(SDR0_ECID3, reg);
	546	if (reg & 0x00100000)
	547	strcpy(addstr, "No Security/Kasumi support");
	548	else
	549	strcpy(addstr, "Security/Kasumi support");
	550	break;
	551
2801b2d2 SR	552	case PVR_460GT_RA:
	553	puts("GT Rev. A");
	554	strcpy(addstr, "No Security/Kasumi support");
	555	break;
	556
	557	case PVR_460GT_SE_RA:
	558	puts("GT Rev. A");
	559	strcpy(addstr, "Security/Kasumi support");
	560	break;
	561
89bcc487 SR	562	case PVR_460GT_RB:
	563	puts("GT Rev. B");
	564	mfsdr(SDR0_ECID3, reg);
	565	if (reg & 0x00100000)
	566	strcpy(addstr, "No Security/Kasumi support");
	567	else
	568	strcpy(addstr, "Security/Kasumi support");
	569	break;
	570	#endif
	571
7d307936 FK	572	case PVR_460SX_RA:
	573	puts("SX Rev. A");
	574	strcpy(addstr, "Security support");
	575	break;
	576
	577	case PVR_460SX_RA_V1:
	578	puts("SX Rev. A");
	579	strcpy(addstr, "No Security support");
	580	break;
	581
	582	case PVR_460GX_RA:
	583	puts("GX Rev. A");
	584	strcpy(addstr, "Security support");
	585	break;
	586
	587	case PVR_460GX_RA_V1:
	588	puts("GX Rev. A");
	589	strcpy(addstr, "No Security support");
	590	break;
	591
d865fd09 RR	592	case PVR_VIRTEX5:
	593	puts("x5 VIRTEX5");
	594	break;
	595
8bde7f77	596	default:
17f50f22	597	printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b WD	598	break;
c609719b WD	599	}
3d9569b2 SR	600
3d9569b2 SR	601	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
e01bd218 SR	602	sys_info.freqPLB / 1000000,
e01bd218 SR	603	get_OPB_freq() / 1000000,
dbbd1257	604	sys_info.freqEBC / 1000000);
3d9569b2	605
edf0b543 SR	606	if (addstr[0] != 0)
	607	printf(" %s\n", addstr);
	608
6e7fb6ea SR	609	#if defined(I2C_BOOTROM)
6e7fb6ea SR	610	printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
90e6f41c	611	#endif /* I2C_BOOTROM */
887e2ec9	612	#if defined(SDR0_PINSTP_SHIFT)
e3cbe1f9	613	printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
cf940988 SR	614	printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
	615	#ifdef CONFIG_NAND_U_BOOT
	616	puts(", booting from NAND");
	617	#endif /* CONFIG_NAND_U_BOOT */
	618	putc('\n');
ba999c53	619	#endif /* SDR0_PINSTP_SHIFT */
3d9569b2	620
dbbd1257	621	#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
6e7fb6ea	622	printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2 SR	623	#endif
3d9569b2 SR	624
1bbae2b8	625	#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
6e7fb6ea	626	if (pci_async_enabled()) {
3d9569b2 SR	627	printf (", PCI async ext clock used");
	628	} else {
	629	printf (", PCI sync clock at %lu MHz",
	630	sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	631	}
c609719b	632	#endif
3d9569b2	633
dbbd1257	634	#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
3d9569b2 SR	635	putc('\n');
	636	#endif
	637
dbbd1257	638	#if defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| defined(CONFIG_405EX)
3d9569b2 SR	639	printf (" 16 kB I-Cache 16 kB D-Cache");
	640	#elif defined(CONFIG_440)
	641	printf (" 32 kB I-Cache 32 kB D-Cache");
	642	#else
	643	printf (" 16 kB I-Cache %d kB D-Cache",
	644	((pvr \| 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
	645	#endif
	646	#endif /* !defined(CONFIG_IOP480) */
	647
	648	#if defined(CONFIG_IOP480)
	649	printf ("PLX IOP480 (PVR=%08x)", pvr);
	650	printf (" at %s MHz:", strmhz(buf, clock));
	651	printf (" %u kB I-Cache", 4);
	652	printf (" %u kB D-Cache", 2);
	653	#endif
	654
	655	#endif /* !defined(CONFIG_405) */
	656
	657	putc ('\n');
c609719b WD	658
	659	return 0;
	660	}
	661
692519b1 RJ	662	int ppc440spe_revB() {
	663	unsigned int pvr;
	664
	665	pvr = get_pvr();
5a5c5698	666	if ((pvr == PVR_440SPe_6_RB) \|\| (pvr == PVR_440SPe_RB))
692519b1 RJ	667	return 1;
	668	else
	669	return 0;
	670	}
c609719b WD	671
	672	/* ------------------------------------------------------------------------- */
	673
8bde7f77	674	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
c609719b	675	{
1f94d162 SR	676	#if defined(CONFIG_BOARD_RESET)
1f94d162 SR	677	board_reset();
1729b92c	678	#else
6d0f6bcf	679	#if defined(CONFIG_SYS_4xx_RESET_TYPE)
58ea142f	680	mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
c157d8e2	681	#else
8bde7f77 WD	682	/*
	683	* Initiate system reset in debug control register DBCR
	684	*/
58ea142f	685	mtspr(SPRN_DBCR0, 0x30000000);
6d0f6bcf	686	#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
f3443867	687	#endif /* defined(CONFIG_BOARD_RESET) */
c157d8e2	688
c609719b WD	689	return 1;
	690	}
	691
c609719b WD	692
	693	/*
	694	* Get timebase clock frequency
	695	*/
	696	unsigned long get_tbclk (void)
	697	{
3d9569b2	698	#if !defined(CONFIG_IOP480)
c609719b WD	699	sys_info_t sys_info;
	700
	701	get_sys_info(&sys_info);
	702	return (sys_info.freqProcessor);
c609719b	703	#else
3d9569b2	704	return (66000000);
c609719b WD	705	#endif
	706
	707	}
	708
	709
	710	#if defined(CONFIG_WATCHDOG)
c7f69c34	711	void watchdog_reset(void)
c609719b WD	712	{
	713	int re_enable = disable_interrupts();
	714	reset_4xx_watchdog();
	715	if (re_enable) enable_interrupts();
	716	}
	717
c7f69c34	718	void reset_4xx_watchdog(void)
c609719b WD	719	{
	720	/*
	721	* Clear TSR(WIS) bit
	722	*/
58ea142f	723	mtspr(SPRN_TSR, 0x40000000);
c609719b WD	724	}
c609719b WD	725	#endif /* CONFIG_WATCHDOG */
25a85906 BW	726
	727	/*
	728	* Initializes on-chip ethernet controllers.
	729	* to override, implement board_eth_init()
	730	*/
	731	int cpu_eth_init(bd_t *bis)
	732	{
	733	#if defined(CONFIG_PPC4xx_EMAC)
	734	ppc_4xx_eth_initialize(bis);
	735	#endif
	736	return 0;
	737	}