[thirdparty/u-boot.git] / cpu / ppc4xx / cpu.c

/*
 * (C) Copyright 2000-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <damm@bitsmart.com>
 *
 * minor modifications by
 * Wolfgang Denk <wd@denx.de>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>

#if !defined(CONFIG_405)
DECLARE_GLOBAL_DATA_PTR;
#endif


#if defined(CONFIG_440)
#define FREQ_EBC		(sys_info.freqEPB)
#else
#define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif

#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)

#define PCI_ASYNC

int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_440GP)
	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
     defined(CONFIG_440SPE)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAE_MASK);
#endif
}
#endif

#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) ||  \
     defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)

#define I2C_BOOTROM

int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
	defined(CONFIG_440SPE)
	unsigned long val;

	mfsdr(sdr_sdcs, val);
	return (val & SDR0_SDCS_SDD);
#endif
}
#endif


#if defined(CONFIG_440)
static int do_chip_reset(unsigned long sys0, unsigned long sys1);
#endif


int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];

#if !defined(CONFIG_IOP480)
	sys_info_t sys_info;

	puts ("CPU:   ");

	get_sys_info(&sys_info);

	puts("AMCC PowerPC 4");

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
	puts("05");
#endif
#if defined(CONFIG_440)
	puts("40");
#endif

	switch (pvr) {
	case PVR_405GP_RB:
		puts("GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("GP Rev. D");
		break;

#ifdef CONFIG_405GP
	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
		puts("GP Rev. E");
		break;
#endif

	case PVR_405CR_RA:
		puts("CR Rev. A");
		break;

	case PVR_405CR_RB:
		puts("CR Rev. B");
		break;

#ifdef CONFIG_405CR
	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
		puts("CR Rev. C");
		break;
#endif

	case PVR_405GPR_RB:
		puts("GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("EP Rev. B");
		break;

#if defined(CONFIG_440)
	case PVR_440GP_RB:
		puts("GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
			do_chip_reset ( mfdcr(cpc0_strp0),
					mfdcr(cpc0_strp1) );
		}
		break;

	case PVR_440GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_440GX_RA:
		puts("GX Rev. A");
		break;

	case PVR_440GX_RB:
		puts("GX Rev. B");
		break;

	case PVR_440GX_RC:
		puts("GX Rev. C");
		break;

	case PVR_440GX_RF:
		puts("GX Rev. F");
		break;

	case PVR_440EP_RA:
		puts("EP Rev. A");
		break;

#ifdef CONFIG_440EP
	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
		puts("EP Rev. B");
		break;

	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
		puts("EP Rev. C");
		break;
#endif /*  CONFIG_440EP */

#ifdef CONFIG_440GR
	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
		puts("GR Rev. A");
		break;

	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
		puts("GR Rev. B");
		break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */

	case PVR_440SP_RA:
		puts("SP Rev. A");
		break;

	case PVR_440SP_RB:
		puts("SP Rev. B");
		break;

	case PVR_440SPe_RA:
		puts("SPe Rev. A");
		break;

	case PVR_440SPe_RB:
		puts("SPe Rev. B");
		break;

	default:
		printf (" UNKNOWN (PVR=%08x)", pvr);
		break;
	}

	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
	       sys_info.freqPLB / 1000000,
	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
	       FREQ_EBC / 1000000);

#if defined(I2C_BOOTROM)
	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif

#if defined(CONFIG_PCI)
	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif

#if defined(PCI_ASYNC)
	if (pci_async_enabled()) {
		printf (", PCI async ext clock used");
	} else {
		printf (", PCI sync clock at %lu MHz",
		       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	}
#endif

#if defined(CONFIG_PCI)
	putc('\n');
#endif

#if defined(CONFIG_405EP)
	printf ("       16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
	printf ("       32 kB I-Cache 32 kB D-Cache");
#else
	printf ("       16 kB I-Cache %d kB D-Cache",
		((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */

#if defined(CONFIG_IOP480)
	printf ("PLX IOP480 (PVR=%08x)", pvr);
	printf (" at %s MHz:", strmhz(buf, clock));
	printf (" %u kB I-Cache", 4);
	printf (" %u kB D-Cache", 2);
#endif

#endif /* !defined(CONFIG_405) */

	putc ('\n');

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
	/*give reset to BCSR*/
	*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;

#else

	/*
	 * Initiate system reset in debug control register DBCR
	 */
	__asm__ __volatile__("lis   3, 0x3000" ::: "r3");
#if defined(CONFIG_440)
	__asm__ __volatile__("mtspr 0x134, 3");
#else
	__asm__ __volatile__("mtspr 0x3f2, 3");
#endif

#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
	return 1;
}

#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	 * reset.
	 */
	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
	mtdcr (cpc0_sys0, sys0);
	mtdcr (cpc0_sys1, sys1);
	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
	mtspr (dbcr0, 0x20000000);	/* Reset the chip */

	return 1;
}
#endif


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
#if !defined(CONFIG_IOP480)
	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return (sys_info.freqProcessor);
#else
	return (66000000);
#endif

}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_4xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_4xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit
	 */
	mtspr(tsr, 0x40000000);
}
#endif	/* CONFIG_WATCHDOG */
Commit	Line	Data
c609719b	1	/*
512f8d5d	2	* (C) Copyright 2000-2006
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
c609719b WD	25	* CPU specific code
	26	*
	27	* written or collected and sometimes rewritten by
	28	* Magnus Damm <damm@bitsmart.com>
	29	*
	30	* minor modifications by
	31	* Wolfgang Denk <wd@denx.de>
	32	*/
	33
	34	#include <common.h>
	35	#include <watchdog.h>
	36	#include <command.h>
	37	#include <asm/cache.h>
	38	#include <ppc4xx.h>
	39
d87080b7 WD	40	#if !defined(CONFIG_405)
	41	DECLARE_GLOBAL_DATA_PTR;
	42	#endif
	43
c609719b	44
6e7fb6ea SR	45	#if defined(CONFIG_440)
	46	#define FREQ_EBC (sys_info.freqEPB)
	47	#else
	48	#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
3d9569b2 SR	49	#endif
3d9569b2 SR	50
6e7fb6ea SR	51	#if defined(CONFIG_405GP) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	52
	53	#define PCI_ASYNC
	54
	55	int pci_async_enabled(void)
	56	{
	57	#if defined(CONFIG_405GP)
	58	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
3d9569b2 SR	59	#endif
	60
	61	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
6e7fb6ea SR	62	unsigned long val;
6e7fb6ea SR	63
7481266e	64	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	65	return (val & SDR0_SDSTP1_PAME_MASK);
	66	#endif
	67	}
	68	#endif
	69
a46726fd	70	#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
6e7fb6ea SR	71	int pci_arbiter_enabled(void)
	72	{
	73	#if defined(CONFIG_405GP)
	74	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
	75	#endif
3d9569b2	76
6e7fb6ea SR	77	#if defined(CONFIG_405EP)
6e7fb6ea SR	78	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
3d9569b2 SR	79	#endif
	80
	81	#if defined(CONFIG_440GP)
6e7fb6ea SR	82	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
	83	#endif
	84
6c5879f3 MB	85	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| \
	86	defined(CONFIG_440GR) \|\| defined(CONFIG_440SP) \|\| \
	87	defined(CONFIG_440SPE)
6e7fb6ea	88	unsigned long val;
3d9569b2	89
6e7fb6ea SR	90	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	91	return (val & SDR0_SDSTP1_PAE_MASK);
3d9569b2	92	#endif
6e7fb6ea SR	93	}
	94	#endif
	95
6c5879f3 MB	96	#if defined(CONFIG_405EP) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
6c5879f3 MB	97	defined(CONFIG_440GX) \|\| defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
3d9569b2	98
6e7fb6ea	99	#define I2C_BOOTROM
3d9569b2	100
6e7fb6ea SR	101	int i2c_bootrom_enabled(void)
	102	{
	103	#if defined(CONFIG_405EP)
	104	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
3d9569b2 SR	105	#endif
3d9569b2 SR	106
6c5879f3 MB	107	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| \
	108	defined(CONFIG_440GR) \|\| defined(CONFIG_440SP) \|\| \
	109	defined(CONFIG_440SPE)
6e7fb6ea SR	110	unsigned long val;
	111
	112	mfsdr(sdr_sdcs, val);
	113	return (val & SDR0_SDCS_SDD);
	114	#endif
	115	}
3d9569b2 SR	116	#endif
	117
	118
c609719b	119	#if defined(CONFIG_440)
3d9569b2	120	static int do_chip_reset(unsigned long sys0, unsigned long sys1);
c609719b WD	121	#endif
c609719b WD	122
c609719b WD	123
	124	int checkcpu (void)
	125	{
3d9569b2	126	#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
3d9569b2	127	uint pvr = get_pvr();
c609719b WD	128	ulong clock = gd->cpu_clk;
c609719b WD	129	char buf[32];
c609719b	130
3d9569b2 SR	131	#if !defined(CONFIG_IOP480)
3d9569b2 SR	132	sys_info_t sys_info;
c609719b WD	133
	134	puts ("CPU: ");
	135
	136	get_sys_info(&sys_info);
	137
3d9569b2 SR	138	puts("AMCC PowerPC 4");
	139
	140	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405EP)
	141	puts("05");
b867d705	142	#endif
3d9569b2 SR	143	#if defined(CONFIG_440)
3d9569b2 SR	144	puts("40");
c609719b	145	#endif
3d9569b2	146
c609719b WD	147	switch (pvr) {
c609719b WD	148	case PVR_405GP_RB:
3d9569b2	149	puts("GP Rev. B");
c609719b	150	break;
3d9569b2	151
c609719b	152	case PVR_405GP_RC:
3d9569b2	153	puts("GP Rev. C");
c609719b	154	break;
3d9569b2	155
c609719b	156	case PVR_405GP_RD:
3d9569b2	157	puts("GP Rev. D");
c609719b	158	break;
3d9569b2	159
42dfe7a1	160	#ifdef CONFIG_405GP
3d9569b2 SR	161	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
3d9569b2 SR	162	puts("GP Rev. E");
c609719b WD	163	break;
c609719b WD	164	#endif
3d9569b2	165
c609719b	166	case PVR_405CR_RA:
3d9569b2	167	puts("CR Rev. A");
c609719b	168	break;
3d9569b2	169
c609719b	170	case PVR_405CR_RB:
3d9569b2	171	puts("CR Rev. B");
c609719b	172	break;
c609719b	173
3d9569b2 SR	174	#ifdef CONFIG_405CR
	175	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
	176	puts("CR Rev. C");
	177	break;
c609719b WD	178	#endif
c609719b WD	179
3d9569b2 SR	180	case PVR_405GPR_RB:
	181	puts("GPr Rev. B");
	182	break;
c609719b	183
3d9569b2 SR	184	case PVR_405EP_RB:
	185	puts("EP Rev. B");
	186	break;
c609719b WD	187
c609719b WD	188	#if defined(CONFIG_440)
8bde7f77	189	case PVR_440GP_RB:
c157d8e2	190	puts("GP Rev. B");
4d816774 WD	191	/* See errata 1.12: CHIP_4 */
	192	if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) \|\|
	193	(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
	194	puts ( "\n\t CPC0_SYSx DCRs corrupted. "
	195	"Resetting chip ...\n");
	196	udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
	197	do_chip_reset ( mfdcr(cpc0_strp0),
	198	mfdcr(cpc0_strp1) );
	199	}
c609719b	200	break;
3d9569b2	201
8bde7f77	202	case PVR_440GP_RC:
c157d8e2	203	puts("GP Rev. C");
ba56f625	204	break;
3d9569b2	205
ba56f625	206	case PVR_440GX_RA:
c157d8e2	207	puts("GX Rev. A");
ba56f625	208	break;
3d9569b2	209
ba56f625	210	case PVR_440GX_RB:
c157d8e2	211	puts("GX Rev. B");
c609719b	212	break;
3d9569b2	213
0a7c5391	214	case PVR_440GX_RC:
c157d8e2	215	puts("GX Rev. C");
0a7c5391	216	break;
3d9569b2	217
57275b69 SR	218	case PVR_440GX_RF:
	219	puts("GX Rev. F");
	220	break;
3d9569b2	221
c157d8e2 SR	222	case PVR_440EP_RA:
	223	puts("EP Rev. A");
	224	break;
3d9569b2	225
9a8d82fd SR	226	#ifdef CONFIG_440EP
9a8d82fd SR	227	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
c157d8e2 SR	228	puts("EP Rev. B");
c157d8e2 SR	229	break;
512f8d5d SR	230
	231	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
	232	puts("EP Rev. C");
	233	break;
9a8d82fd	234	#endif /* CONFIG_440EP */
3d9569b2	235
9a8d82fd SR	236	#ifdef CONFIG_440GR
	237	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
	238	puts("GR Rev. A");
	239	break;
512f8d5d	240
5770a1e4	241	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
512f8d5d SR	242	puts("GR Rev. B");
512f8d5d SR	243	break;
9a8d82fd	244	#endif /* CONFIG_440GR */
3d9569b2 SR	245	#endif /* CONFIG_440 */
3d9569b2 SR	246
6e7fb6ea SR	247	case PVR_440SP_RA:
	248	puts("SP Rev. A");
	249	break;
	250
	251	case PVR_440SP_RB:
	252	puts("SP Rev. B");
	253	break;
	254
6c5879f3	255	case PVR_440SPe_RA:
fe84b48a	256	puts("SPe Rev. A");
6c5879f3	257	break;
fe84b48a	258
6c5879f3	259	case PVR_440SPe_RB:
fe84b48a	260	puts("SPe Rev. B");
6c5879f3	261	break;
fe84b48a	262
8bde7f77	263	default:
17f50f22	264	printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b WD	265	break;
c609719b WD	266	}
3d9569b2 SR	267
	268	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
	269	sys_info.freqPLB / 1000000,
	270	sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
	271	FREQ_EBC / 1000000);
	272
6e7fb6ea SR	273	#if defined(I2C_BOOTROM)
6e7fb6ea SR	274	printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
3d9569b2 SR	275	#endif
3d9569b2 SR	276
6e7fb6ea SR	277	#if defined(CONFIG_PCI)
6e7fb6ea SR	278	printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2 SR	279	#endif
3d9569b2 SR	280
6e7fb6ea SR	281	#if defined(PCI_ASYNC)
6e7fb6ea SR	282	if (pci_async_enabled()) {
3d9569b2 SR	283	printf (", PCI async ext clock used");
	284	} else {
	285	printf (", PCI sync clock at %lu MHz",
	286	sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	287	}
c609719b	288	#endif
3d9569b2	289
6e7fb6ea	290	#if defined(CONFIG_PCI)
3d9569b2 SR	291	putc('\n');
	292	#endif
	293
	294	#if defined(CONFIG_405EP)
	295	printf (" 16 kB I-Cache 16 kB D-Cache");
	296	#elif defined(CONFIG_440)
	297	printf (" 32 kB I-Cache 32 kB D-Cache");
	298	#else
	299	printf (" 16 kB I-Cache %d kB D-Cache",
	300	((pvr \| 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
	301	#endif
	302	#endif /* !defined(CONFIG_IOP480) */
	303
	304	#if defined(CONFIG_IOP480)
	305	printf ("PLX IOP480 (PVR=%08x)", pvr);
	306	printf (" at %s MHz:", strmhz(buf, clock));
	307	printf (" %u kB I-Cache", 4);
	308	printf (" %u kB D-Cache", 2);
	309	#endif
	310
	311	#endif /* !defined(CONFIG_405) */
	312
	313	putc ('\n');
c609719b WD	314
	315	return 0;
	316	}
	317
	318
	319	/* ------------------------------------------------------------------------- */
	320
8bde7f77	321	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
c609719b	322	{
c157d8e2 SR	323	#if defined(CONFIG_YOSEMITE) \|\| defined(CONFIG_YELLOWSTONE)
	324	/give reset to BCSR/
	325	(unsigned char)(CFG_BCSR_BASE \| 0x06) = 0x09;
	326
	327	#else
	328
8bde7f77 WD	329	/*
	330	* Initiate system reset in debug control register DBCR
	331	*/
c609719b WD	332	__asm__ __volatile__("lis 3, 0x3000" ::: "r3");
	333	#if defined(CONFIG_440)
	334	__asm__ __volatile__("mtspr 0x134, 3");
	335	#else
	336	__asm__ __volatile__("mtspr 0x3f2, 3");
	337	#endif
c157d8e2 SR	338
c157d8e2 SR	339	#endif/* defined(CONFIG_YOSEMITE) \|\| defined(CONFIG_YELLOWSTONE)*/
c609719b WD	340	return 1;
	341	}
	342
	343	#if defined(CONFIG_440)
3d9569b2	344	static int do_chip_reset (unsigned long sys0, unsigned long sys1)
c609719b	345	{
4d816774 WD	346	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	347	* reset.
	348	*/
	349	mtdcr (cntrl0, mfdcr (cntrl0) \| 0x80000000); /* Set SWE */
	350	mtdcr (cpc0_sys0, sys0);
	351	mtdcr (cpc0_sys1, sys1);
	352	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
	353	mtspr (dbcr0, 0x20000000); /* Reset the chip */
	354
	355	return 1;
c609719b WD	356	}
	357	#endif
	358
	359
	360	/*
	361	* Get timebase clock frequency
	362	*/
	363	unsigned long get_tbclk (void)
	364	{
3d9569b2	365	#if !defined(CONFIG_IOP480)
c609719b WD	366	sys_info_t sys_info;
	367
	368	get_sys_info(&sys_info);
	369	return (sys_info.freqProcessor);
c609719b	370	#else
3d9569b2	371	return (66000000);
c609719b WD	372	#endif
	373
	374	}
	375
	376
	377	#if defined(CONFIG_WATCHDOG)
	378	void
	379	watchdog_reset(void)
	380	{
	381	int re_enable = disable_interrupts();
	382	reset_4xx_watchdog();
	383	if (re_enable) enable_interrupts();
	384	}
	385
	386	void
	387	reset_4xx_watchdog(void)
	388	{
	389	/*
	390	* Clear TSR(WIS) bit
	391	*/
	392	mtspr(tsr, 0x40000000);
	393	}
	394	#endif /* CONFIG_WATCHDOG */