[thirdparty/u-boot.git] / cpu / ppc4xx / cpu.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <damm@bitsmart.com>
 *
 * minor modifications by
 * Wolfgang Denk <wd@denx.de>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>


#if defined(CONFIG_440)
#define FREQ_EBC		(sys_info.freqEPB)
#else
#define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif

#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)

#define PCI_ASYNC

int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_440GP)
	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
	unsigned long val;

	mfsdr(sdr_sdstp1, val);
	return (val & SDR0_SDSTP1_PAE_MASK);
#endif
}
#endif

#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
	defined(CONFIG_440GX) || defined(CONFIG_440SP)

#define I2C_BOOTROM

int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
	unsigned long val;

	mfsdr(sdr_sdcs, val);
	return (val & SDR0_SDCS_SDD);
#endif
}
#endif


#if defined(CONFIG_440)
static int do_chip_reset(unsigned long sys0, unsigned long sys1);
#endif


int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	DECLARE_GLOBAL_DATA_PTR;
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];

#if !defined(CONFIG_IOP480)
	sys_info_t sys_info;

	puts ("CPU:   ");

	get_sys_info(&sys_info);

	puts("AMCC PowerPC 4");

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
	puts("05");
#endif
#if defined(CONFIG_440)
	puts("40");
#endif

	switch (pvr) {
	case PVR_405GP_RB:
		puts("GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("GP Rev. D");
		break;

#ifdef CONFIG_405GP
	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
		puts("GP Rev. E");
		break;
#endif

	case PVR_405CR_RA:
		puts("CR Rev. A");
		break;

	case PVR_405CR_RB:
		puts("CR Rev. B");
		break;

#ifdef CONFIG_405CR
	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
		puts("CR Rev. C");
		break;
#endif

	case PVR_405GPR_RB:
		puts("GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("EP Rev. B");
		break;

#if defined(CONFIG_440)
	case PVR_440GP_RB:
		puts("GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
			do_chip_reset ( mfdcr(cpc0_strp0),
					mfdcr(cpc0_strp1) );
		}
		break;

	case PVR_440GP_RC:
		puts("GP Rev. C");
		break;

	case PVR_440GX_RA:
		puts("GX Rev. A");
		break;

	case PVR_440GX_RB:
		puts("GX Rev. B");
		break;

	case PVR_440GX_RC:
		puts("GX Rev. C");
		break;

	case PVR_440GX_RF:
		puts("GX Rev. F");
		break;

	case PVR_440EP_RA:
		puts("EP Rev. A");
		break;

#ifdef CONFIG_440EP
	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
		puts("EP Rev. B");
		break;
#endif /*  CONFIG_440EP */

#ifdef CONFIG_440GR
	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
		puts("GR Rev. A");
		break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */

	case PVR_440SP_RA:
		puts("SP Rev. A");
		break;

	case PVR_440SP_RB:
		puts("SP Rev. B");
		break;

	default:
		printf (" UNKNOWN (PVR=%08x)", pvr);
		break;
	}

	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
	       sys_info.freqPLB / 1000000,
	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
	       FREQ_EBC / 1000000);

#if defined(I2C_BOOTROM)
	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif

#if defined(CONFIG_PCI)
	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif

#if defined(PCI_ASYNC)
	if (pci_async_enabled()) {
		printf (", PCI async ext clock used");
	} else {
		printf (", PCI sync clock at %lu MHz",
		       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	}
#endif

#if defined(CONFIG_PCI)
	putc('\n');
#endif

#if defined(CONFIG_405EP)
	printf ("       16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
	printf ("       32 kB I-Cache 32 kB D-Cache");
#else
	printf ("       16 kB I-Cache %d kB D-Cache",
		((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */

#if defined(CONFIG_IOP480)
	printf ("PLX IOP480 (PVR=%08x)", pvr);
	printf (" at %s MHz:", strmhz(buf, clock));
	printf (" %u kB I-Cache", 4);
	printf (" %u kB D-Cache", 2);
#endif

#endif /* !defined(CONFIG_405) */

	putc ('\n');

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
	/*give reset to BCSR*/
	*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;

#else

	/*
	 * Initiate system reset in debug control register DBCR
	 */
	__asm__ __volatile__("lis   3, 0x3000" ::: "r3");
#if defined(CONFIG_440)
	__asm__ __volatile__("mtspr 0x134, 3");
#else
	__asm__ __volatile__("mtspr 0x3f2, 3");
#endif

#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
	return 1;
}

#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	 * reset.
	 */
	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
	mtdcr (cpc0_sys0, sys0);
	mtdcr (cpc0_sys1, sys1);
	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
	mtspr (dbcr0, 0x20000000);	/* Reset the chip */

	return 1;
}
#endif


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
#if !defined(CONFIG_IOP480)
	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return (sys_info.freqProcessor);
#else
	return (66000000);
#endif

}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_4xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_4xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit
	 */
	mtspr(tsr, 0x40000000);
}
#endif	/* CONFIG_WATCHDOG */
Commit	Line	Data
c609719b	1	/*
4d816774	2	* (C) Copyright 2000-2003
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
c609719b WD	25	* CPU specific code
	26	*
	27	* written or collected and sometimes rewritten by
	28	* Magnus Damm <damm@bitsmart.com>
	29	*
	30	* minor modifications by
	31	* Wolfgang Denk <wd@denx.de>
	32	*/
	33
	34	#include <common.h>
	35	#include <watchdog.h>
	36	#include <command.h>
	37	#include <asm/cache.h>
	38	#include <ppc4xx.h>
	39
	40
6e7fb6ea SR	41	#if defined(CONFIG_440)
	42	#define FREQ_EBC (sys_info.freqEPB)
	43	#else
	44	#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
3d9569b2 SR	45	#endif
3d9569b2 SR	46
6e7fb6ea SR	47	#if defined(CONFIG_405GP) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	48
	49	#define PCI_ASYNC
	50
	51	int pci_async_enabled(void)
	52	{
	53	#if defined(CONFIG_405GP)
	54	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
3d9569b2 SR	55	#endif
	56
	57	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
6e7fb6ea SR	58	unsigned long val;
6e7fb6ea SR	59
7481266e	60	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	61	return (val & SDR0_SDSTP1_PAME_MASK);
	62	#endif
	63	}
	64	#endif
	65
a46726fd	66	#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
6e7fb6ea SR	67	int pci_arbiter_enabled(void)
	68	{
	69	#if defined(CONFIG_405GP)
	70	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
	71	#endif
3d9569b2	72
6e7fb6ea SR	73	#if defined(CONFIG_405EP)
6e7fb6ea SR	74	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
3d9569b2 SR	75	#endif
	76
	77	#if defined(CONFIG_440GP)
6e7fb6ea SR	78	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
	79	#endif
	80
	81	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| defined(CONFIG_440SP)
	82	unsigned long val;
3d9569b2	83
6e7fb6ea SR	84	mfsdr(sdr_sdstp1, val);
6e7fb6ea SR	85	return (val & SDR0_SDSTP1_PAE_MASK);
3d9569b2	86	#endif
6e7fb6ea SR	87	}
	88	#endif
	89
	90	#if defined(CONFIG_405EP)\|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
	91	defined(CONFIG_440GX) \|\| defined(CONFIG_440SP)
3d9569b2	92
6e7fb6ea	93	#define I2C_BOOTROM
3d9569b2	94
6e7fb6ea SR	95	int i2c_bootrom_enabled(void)
	96	{
	97	#if defined(CONFIG_405EP)
	98	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
3d9569b2 SR	99	#endif
3d9569b2 SR	100
6e7fb6ea SR	101	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| defined(CONFIG_440SP)
	102	unsigned long val;
	103
	104	mfsdr(sdr_sdcs, val);
	105	return (val & SDR0_SDCS_SDD);
	106	#endif
	107	}
3d9569b2 SR	108	#endif
	109
	110
c609719b	111	#if defined(CONFIG_440)
3d9569b2	112	static int do_chip_reset(unsigned long sys0, unsigned long sys1);
c609719b WD	113	#endif
c609719b WD	114
c609719b WD	115
	116	int checkcpu (void)
	117	{
3d9569b2	118	#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
c609719b	119	DECLARE_GLOBAL_DATA_PTR;
3d9569b2	120	uint pvr = get_pvr();
c609719b WD	121	ulong clock = gd->cpu_clk;
c609719b WD	122	char buf[32];
c609719b	123
3d9569b2 SR	124	#if !defined(CONFIG_IOP480)
3d9569b2 SR	125	sys_info_t sys_info;
c609719b WD	126
	127	puts ("CPU: ");
	128
	129	get_sys_info(&sys_info);
	130
3d9569b2 SR	131	puts("AMCC PowerPC 4");
	132
	133	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405EP)
	134	puts("05");
b867d705	135	#endif
3d9569b2 SR	136	#if defined(CONFIG_440)
3d9569b2 SR	137	puts("40");
c609719b	138	#endif
3d9569b2	139
c609719b WD	140	switch (pvr) {
c609719b WD	141	case PVR_405GP_RB:
3d9569b2	142	puts("GP Rev. B");
c609719b	143	break;
3d9569b2	144
c609719b	145	case PVR_405GP_RC:
3d9569b2	146	puts("GP Rev. C");
c609719b	147	break;
3d9569b2	148
c609719b	149	case PVR_405GP_RD:
3d9569b2	150	puts("GP Rev. D");
c609719b	151	break;
3d9569b2	152
42dfe7a1	153	#ifdef CONFIG_405GP
3d9569b2 SR	154	case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
3d9569b2 SR	155	puts("GP Rev. E");
c609719b WD	156	break;
c609719b WD	157	#endif
3d9569b2	158
c609719b	159	case PVR_405CR_RA:
3d9569b2	160	puts("CR Rev. A");
c609719b	161	break;
3d9569b2	162
c609719b	163	case PVR_405CR_RB:
3d9569b2	164	puts("CR Rev. B");
c609719b	165	break;
c609719b	166
3d9569b2 SR	167	#ifdef CONFIG_405CR
	168	case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
	169	puts("CR Rev. C");
	170	break;
c609719b WD	171	#endif
c609719b WD	172
3d9569b2 SR	173	case PVR_405GPR_RB:
	174	puts("GPr Rev. B");
	175	break;
c609719b	176
3d9569b2 SR	177	case PVR_405EP_RB:
	178	puts("EP Rev. B");
	179	break;
c609719b WD	180
c609719b WD	181	#if defined(CONFIG_440)
8bde7f77	182	case PVR_440GP_RB:
c157d8e2	183	puts("GP Rev. B");
4d816774 WD	184	/* See errata 1.12: CHIP_4 */
	185	if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) \|\|
	186	(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
	187	puts ( "\n\t CPC0_SYSx DCRs corrupted. "
	188	"Resetting chip ...\n");
	189	udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
	190	do_chip_reset ( mfdcr(cpc0_strp0),
	191	mfdcr(cpc0_strp1) );
	192	}
c609719b	193	break;
3d9569b2	194
8bde7f77	195	case PVR_440GP_RC:
c157d8e2	196	puts("GP Rev. C");
ba56f625	197	break;
3d9569b2	198
ba56f625	199	case PVR_440GX_RA:
c157d8e2	200	puts("GX Rev. A");
ba56f625	201	break;
3d9569b2	202
ba56f625	203	case PVR_440GX_RB:
c157d8e2	204	puts("GX Rev. B");
c609719b	205	break;
3d9569b2	206
0a7c5391	207	case PVR_440GX_RC:
c157d8e2	208	puts("GX Rev. C");
0a7c5391	209	break;
3d9569b2	210
57275b69 SR	211	case PVR_440GX_RF:
	212	puts("GX Rev. F");
	213	break;
3d9569b2	214
c157d8e2 SR	215	case PVR_440EP_RA:
	216	puts("EP Rev. A");
	217	break;
3d9569b2	218
9a8d82fd SR	219	#ifdef CONFIG_440EP
9a8d82fd SR	220	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
c157d8e2 SR	221	puts("EP Rev. B");
c157d8e2 SR	222	break;
9a8d82fd	223	#endif /* CONFIG_440EP */
3d9569b2	224
9a8d82fd SR	225	#ifdef CONFIG_440GR
	226	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
	227	puts("GR Rev. A");
	228	break;
	229	#endif /* CONFIG_440GR */
3d9569b2 SR	230	#endif /* CONFIG_440 */
3d9569b2 SR	231
6e7fb6ea SR	232	case PVR_440SP_RA:
	233	puts("SP Rev. A");
	234	break;
	235
	236	case PVR_440SP_RB:
	237	puts("SP Rev. B");
	238	break;
	239
8bde7f77	240	default:
17f50f22	241	printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b WD	242	break;
c609719b WD	243	}
3d9569b2 SR	244
	245	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
	246	sys_info.freqPLB / 1000000,
	247	sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
	248	FREQ_EBC / 1000000);
	249
6e7fb6ea SR	250	#if defined(I2C_BOOTROM)
6e7fb6ea SR	251	printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
3d9569b2 SR	252	#endif
3d9569b2 SR	253
6e7fb6ea SR	254	#if defined(CONFIG_PCI)
6e7fb6ea SR	255	printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2 SR	256	#endif
3d9569b2 SR	257
6e7fb6ea SR	258	#if defined(PCI_ASYNC)
6e7fb6ea SR	259	if (pci_async_enabled()) {
3d9569b2 SR	260	printf (", PCI async ext clock used");
	261	} else {
	262	printf (", PCI sync clock at %lu MHz",
	263	sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	264	}
c609719b	265	#endif
3d9569b2	266
6e7fb6ea	267	#if defined(CONFIG_PCI)
3d9569b2 SR	268	putc('\n');
	269	#endif
	270
	271	#if defined(CONFIG_405EP)
	272	printf (" 16 kB I-Cache 16 kB D-Cache");
	273	#elif defined(CONFIG_440)
	274	printf (" 32 kB I-Cache 32 kB D-Cache");
	275	#else
	276	printf (" 16 kB I-Cache %d kB D-Cache",
	277	((pvr \| 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
	278	#endif
	279	#endif /* !defined(CONFIG_IOP480) */
	280
	281	#if defined(CONFIG_IOP480)
	282	printf ("PLX IOP480 (PVR=%08x)", pvr);
	283	printf (" at %s MHz:", strmhz(buf, clock));
	284	printf (" %u kB I-Cache", 4);
	285	printf (" %u kB D-Cache", 2);
	286	#endif
	287
	288	#endif /* !defined(CONFIG_405) */
	289
	290	putc ('\n');
c609719b WD	291
	292	return 0;
	293	}
	294
	295
	296	/* ------------------------------------------------------------------------- */
	297
8bde7f77	298	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
c609719b	299	{
c157d8e2 SR	300	#if defined(CONFIG_YOSEMITE) \|\| defined(CONFIG_YELLOWSTONE)
	301	/give reset to BCSR/
	302	(unsigned char)(CFG_BCSR_BASE \| 0x06) = 0x09;
	303
	304	#else
	305
8bde7f77 WD	306	/*
	307	* Initiate system reset in debug control register DBCR
	308	*/
c609719b WD	309	__asm__ __volatile__("lis 3, 0x3000" ::: "r3");
	310	#if defined(CONFIG_440)
	311	__asm__ __volatile__("mtspr 0x134, 3");
	312	#else
	313	__asm__ __volatile__("mtspr 0x3f2, 3");
	314	#endif
c157d8e2 SR	315
c157d8e2 SR	316	#endif/* defined(CONFIG_YOSEMITE) \|\| defined(CONFIG_YELLOWSTONE)*/
c609719b WD	317	return 1;
	318	}
	319
	320	#if defined(CONFIG_440)
3d9569b2	321	static int do_chip_reset (unsigned long sys0, unsigned long sys1)
c609719b	322	{
4d816774 WD	323	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
	324	* reset.
	325	*/
	326	mtdcr (cntrl0, mfdcr (cntrl0) \| 0x80000000); /* Set SWE */
	327	mtdcr (cpc0_sys0, sys0);
	328	mtdcr (cpc0_sys1, sys1);
	329	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
	330	mtspr (dbcr0, 0x20000000); /* Reset the chip */
	331
	332	return 1;
c609719b WD	333	}
	334	#endif
	335
	336
	337	/*
	338	* Get timebase clock frequency
	339	*/
	340	unsigned long get_tbclk (void)
	341	{
3d9569b2	342	#if !defined(CONFIG_IOP480)
c609719b WD	343	sys_info_t sys_info;
	344
	345	get_sys_info(&sys_info);
	346	return (sys_info.freqProcessor);
c609719b	347	#else
3d9569b2	348	return (66000000);
c609719b WD	349	#endif
	350
	351	}
	352
	353
	354	#if defined(CONFIG_WATCHDOG)
	355	void
	356	watchdog_reset(void)
	357	{
	358	int re_enable = disable_interrupts();
	359	reset_4xx_watchdog();
	360	if (re_enable) enable_interrupts();
	361	}
	362
	363	void
	364	reset_4xx_watchdog(void)
	365	{
	366	/*
	367	* Clear TSR(WIS) bit
	368	*/
	369	mtspr(tsr, 0x40000000);
	370	}
	371	#endif /* CONFIG_WATCHDOG */