[people/ms/u-boot.git] / cpu / ppc4xx / speed.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <ppc4xx.h>
#include <asm/processor.h>

/* ------------------------------------------------------------------------- */

#define ONE_BILLION        1000000000


#if defined(CONFIG_405GP) || defined(CONFIG_405CR)

void get_sys_info (PPC405_SYS_INFO * sysInfo)
{
	unsigned long pllmr;
	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	uint pvr = get_pvr();
	unsigned long psr;
	unsigned long m;

	/*
	 * Read PLL Mode register
	 */
	pllmr = mfdcr (pllmd);

	/*
	 * Read Pin Strapping register
	 */
	psr = mfdcr (strap);

	/*
	 * Determine FWD_DIV.
	 */
	sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);

	/*
	 * Determine FBK_DIV.
	 */
	sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
	if (sysInfo->pllFbkDiv == 0) {
		sysInfo->pllFbkDiv = 16;
	}

	/*
	 * Determine PLB_DIV.
	 */
	sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;

	/*
	 * Determine PCI_DIV.
	 */
	sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;

	/*
	 * Determine EXTBUS_DIV.
	 */
	sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;

	/*
	 * Determine OPB_DIV.
	 */
	sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;

	/*
	 * Check if PPC405GPr used (mask minor revision field)
	 */
	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
		/*
		 * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
		 */
		sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);

		/*
		 * Determine factor m depending on PLL feedback clock source
		 */
		if (!(psr & PSR_PCI_ASYNC_EN)) {
			if (psr & PSR_NEW_MODE_EN) {
				/*
				 * sync pci clock used as feedback (new mode)
				 */
				m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
			} else {
				/*
				 * sync pci clock used as feedback (legacy mode)
				 */
				m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
			}
		} else if (psr & PSR_NEW_MODE_EN) {
			if (psr & PSR_PERCLK_SYNC_MODE_EN) {
				/*
				 * PerClk used as feedback (new mode)
				 */
				m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
			} else {
				/*
				 * CPU clock used as feedback (new mode)
				 */
				m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
			}
		} else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
			/*
			 * PerClk used as feedback (legacy mode)
			 */
			m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
		} else {
			/*
			 * PLB clock used as feedback (legacy mode)
			 */
			m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
		}

		sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
		sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv;
		sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) /
			(sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
	} else {
		/*
		 * Check pllFwdDiv to see if running in bypass mode where the CPU speed
		 * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
		 * to make sure it is within the proper range.
		 *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
		 * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
		 */
		if (sysInfo->pllFwdDiv == 1) {
			sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
			sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
		} else {
			sysInfo->freqVCOMhz = ( 1000000 *
						sysInfo->pllFwdDiv *
						sysInfo->pllFbkDiv *
						sysInfo->pllPlbDiv
				) / sysClkPeriodPs;
			if (sysInfo->freqVCOMhz >= VCO_MIN
			    && sysInfo->freqVCOMhz <= VCO_MAX) {
				sysInfo->freqPLB = (ONE_BILLION /
						    ((sysClkPeriodPs * 10) /
						     sysInfo->pllFbkDiv)) * 10000;
				sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
			} else {
				printf ("\nInvalid VCO frequency calculated :  %ld MHz \a\n",
					sysInfo->freqVCOMhz);
				printf ("It must be between %d-%d MHz \a\n",
					VCO_MIN, VCO_MAX);
				printf ("PLL Mode reg           :  %8.8lx\a\n",
					pllmr);
				hang ();
			}
		}
	}
}


/********************************************
 * get_OPB_freq
 * return OPB bus freq in Hz
 *********************************************/
ulong get_OPB_freq (void)
{
	ulong val = 0;

	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllOpbDiv;

	return val;
}


/********************************************
 * get_PCI_freq
 * return PCI bus freq in Hz
 *********************************************/
ulong get_PCI_freq (void)
{
	ulong val;
	PPC405_SYS_INFO sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB / sys_info.pllPciDiv;
	return val;
}


#elif defined(CONFIG_440)
void get_sys_info (sys_info_t * sysInfo)
{
	unsigned long strp0;
	unsigned long temp;
	unsigned long m;

	/* Extract configured divisors */
	strp0 = mfdcr( cpc0_strp0 );
	sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
	sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
	sysInfo->pllFbkDiv = temp ? temp : 16;
	sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
	sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);

	/* Calculate 'M' based on feedback source */
	if( strp0 & PLLSYS0_EXTSL_MASK )
		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
	else
		m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;

	/* Now calculate the individual clocks */
	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
    if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
        sysInfo->freqPLB >>= 1;
	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;

}

ulong get_OPB_freq (void)
{

	sys_info_t sys_info;
	get_sys_info (&sys_info);
	return sys_info.freqOPB;
}

#elif defined(CONFIG_405)

void get_sys_info (sys_info_t * sysInfo) {

	sysInfo->freqVCOMhz=3125000;
	sysInfo->freqProcessor=12*1000*1000;
	sysInfo->freqPLB=50*1000*1000;
	sysInfo->freqPCI=66*1000*1000;

}

#endif

int get_clocks (void)
{
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405)
	DECLARE_GLOBAL_DATA_PTR;

	sys_info_t sys_info;

	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor;
	gd->bus_clk = sys_info.freqPLB;

#endif	/* defined(CONFIG_405GP) || defined(CONFIG_405CR) */

#ifdef CONFIG_IOP480
	DECLARE_GLOBAL_DATA_PTR;

	gd->cpu_clk = 66000000;
	gd->bus_clk = 66000000;
#endif
	return (0);
}


/********************************************
 * get_bus_freq
 * return PLB bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	ulong val;

#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440)
	sys_info_t sys_info;

	get_sys_info (&sys_info);
	val = sys_info.freqPLB;

#elif defined(CONFIG_IOP480)

	val = 66;

#else
# error get_bus_freq() not implemented
#endif

	return val;
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <ppc_asm.tmpl>
	26	#include <ppc4xx.h>
	27	#include <asm/processor.h>
	28
	29	/* ------------------------------------------------------------------------- */
	30
	31	#define ONE_BILLION 1000000000
	32
	33
	34	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR)
	35
	36	void get_sys_info (PPC405_SYS_INFO * sysInfo)
	37	{
	38	unsigned long pllmr;
	39	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
	40	uint pvr = get_pvr();
	41	unsigned long psr;
	42	unsigned long m;
	43
	44	/*
	45	* Read PLL Mode register
	46	*/
	47	pllmr = mfdcr (pllmd);
	48
	49	/*
	50	* Read Pin Strapping register
	51	*/
	52	psr = mfdcr (strap);
	53
	54	/*
	55	* Determine FWD_DIV.
	56	*/
	57	sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
	58
	59	/*
	60	* Determine FBK_DIV.
	61	*/
	62	sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
	63	if (sysInfo->pllFbkDiv == 0) {
	64	sysInfo->pllFbkDiv = 16;
65	}
66
67	/*
68	* Determine PLB_DIV.
69	*/
70	sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
71
72	/*
73	* Determine PCI_DIV.
74	*/
75	sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
76
77	/*
78	* Determine EXTBUS_DIV.
79	*/
80	sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
81
82	/*
83	* Determine OPB_DIV.
84	*/
85	sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
86
87	/*
88	* Check if PPC405GPr used (mask minor revision field)
89	*/
baa3d528	90	if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
c609719b WD	91	/*
	92	* Determine FWD_DIV B (only PPC405GPr with new mode strapping).
	93	*/
	94	sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
	95
	96	/*
	97	* Determine factor m depending on PLL feedback clock source
	98	*/
	99	if (!(psr & PSR_PCI_ASYNC_EN)) {
	100	if (psr & PSR_NEW_MODE_EN) {
	101	/*
	102	* sync pci clock used as feedback (new mode)
	103	*/
	104	m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
	105	} else {
	106	/*
	107	* sync pci clock used as feedback (legacy mode)
	108	*/
	109	m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
	110	}
	111	} else if (psr & PSR_NEW_MODE_EN) {
	112	if (psr & PSR_PERCLK_SYNC_MODE_EN) {
	113	/*
	114	* PerClk used as feedback (new mode)
	115	*/
	116	m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
	117	} else {
	118	/*
	119	* CPU clock used as feedback (new mode)
	120	*/
	121	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
	122	}
	123	} else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
	124	/*
	125	* PerClk used as feedback (legacy mode)
	126	*/
	127	m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
	128	} else {
	129	/*
	130	* PLB clock used as feedback (legacy mode)
	131	*/
	132	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
	133	}
	134
	135	sysInfo->freqVCOMhz = (1000000 * m) / sysClkPeriodPs;
	136	sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000) / sysInfo->pllFwdDiv;
	137	sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000) /
	138	(sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
	139	} else {
	140	/*
	141	* Check pllFwdDiv to see if running in bypass mode where the CPU speed
	142	* is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
	143	* to make sure it is within the proper range.
	144	* spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
	145	* Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
	146	*/
	147	if (sysInfo->pllFwdDiv == 1) {
	148	sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
	149	sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
	150	} else {
	151	sysInfo->freqVCOMhz = ( 1000000 *
	152	sysInfo->pllFwdDiv *
	153	sysInfo->pllFbkDiv *
	154	sysInfo->pllPlbDiv
155	) / sysClkPeriodPs;
156	if (sysInfo->freqVCOMhz >= VCO_MIN
157	&& sysInfo->freqVCOMhz <= VCO_MAX) {
158	sysInfo->freqPLB = (ONE_BILLION /
159	((sysClkPeriodPs * 10) /
160	sysInfo->pllFbkDiv)) * 10000;
161	sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
162	} else {
163	printf ("\nInvalid VCO frequency calculated : %ld MHz \a\n",
164	sysInfo->freqVCOMhz);
165	printf ("It must be between %d-%d MHz \a\n",
166	VCO_MIN, VCO_MAX);
167	printf ("PLL Mode reg : %8.8lx\a\n",
168	pllmr);
169	hang ();
170	}
171	}
172	}
173	}
174
175
176	/********************************************
177	* get_OPB_freq
178	* return OPB bus freq in Hz
179	*********************************************/
180	ulong get_OPB_freq (void)
181	{
182	ulong val = 0;
183
184	PPC405_SYS_INFO sys_info;
185
186	get_sys_info (&sys_info);
187	val = sys_info.freqPLB / sys_info.pllOpbDiv;
188
189	return val;
190	}
191
192
193	/********************************************
194	* get_PCI_freq
195	* return PCI bus freq in Hz
196	*********************************************/
197	ulong get_PCI_freq (void)
198	{
199	ulong val;
200	PPC405_SYS_INFO sys_info;
201
202	get_sys_info (&sys_info);
203	val = sys_info.freqPLB / sys_info.pllPciDiv;
204	return val;
205	}
206
207
208	#elif defined(CONFIG_440)
209	void get_sys_info (sys_info_t * sysInfo)
210	{
211	unsigned long strp0;
212	unsigned long temp;
213	unsigned long m;
214
215	/* Extract configured divisors */
216	strp0 = mfdcr( cpc0_strp0 );
217	sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
218	sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
219	temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
220	sysInfo->pllFbkDiv = temp ? temp : 16;
221	sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
222	sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
223
224	/* Calculate 'M' based on feedback source */
225	if( strp0 & PLLSYS0_EXTSL_MASK )
226	m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
227	else
228	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
229
230	/* Now calculate the individual clocks */
231	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
232	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
233	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
234	if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
235	sysInfo->freqPLB >>= 1;
236	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
237	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
238
239	}
240
241	ulong get_OPB_freq (void)
242	{
243
244	sys_info_t sys_info;
245	get_sys_info (&sys_info);
246	return sys_info.freqOPB;
247	}
248
249	#elif defined(CONFIG_405)
250
251	void get_sys_info (sys_info_t * sysInfo) {
252
253	sysInfo->freqVCOMhz=3125000;
254	sysInfo->freqProcessor=1210001000;
255	sysInfo->freqPLB=5010001000;
256	sysInfo->freqPCI=6610001000;
257
258	}
259
260	#endif
261
262	int get_clocks (void)
263	{
264	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_440) \|\| defined(CONFIG_405)
265	DECLARE_GLOBAL_DATA_PTR;
266
267	sys_info_t sys_info;
268
269	get_sys_info (&sys_info);
270	gd->cpu_clk = sys_info.freqProcessor;
271	gd->bus_clk = sys_info.freqPLB;
272
273	#endif /* defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) */
274
275	#ifdef CONFIG_IOP480
276	DECLARE_GLOBAL_DATA_PTR;
277
278	gd->cpu_clk = 66000000;
279	gd->bus_clk = 66000000;
280	#endif
281	return (0);
282	}
283
284
285	/********************************************
286	* get_bus_freq
287	* return PLB bus freq in Hz
288	*********************************************/
289	ulong get_bus_freq (ulong dummy)
290	{
291	ulong val;
292
293	#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_405) \|\| defined(CONFIG_440)
294	sys_info_t sys_info;
295
296	get_sys_info (&sys_info);
297	val = sys_info.freqPLB;
298
299	#elif defined(CONFIG_IOP480)
300
301	val = 66;
302
303	#else
304	# error get_bus_freq() not implemented
305	#endif
306
307	return val;
308	}