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11a72d9f WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Alex Zuepke <azu@sysgo.de> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
30 | * CPU specific code | |
31 | */ | |
32 | ||
33 | #include <common.h> | |
34 | #include <command.h> | |
71f95118 | 35 | #include <asm/arch/pxa-regs.h> |
11a72d9f | 36 | |
d87080b7 WD |
37 | #ifdef CONFIG_USE_IRQ |
38 | DECLARE_GLOBAL_DATA_PTR; | |
39 | #endif | |
40 | ||
11a72d9f WD |
41 | int cpu_init (void) |
42 | { | |
43 | /* | |
a8c7c708 | 44 | * setup up stacks if necessary |
11a72d9f | 45 | */ |
11a72d9f | 46 | #ifdef CONFIG_USE_IRQ |
6d0f6bcf | 47 | IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; |
a8c7c708 | 48 | FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; |
11a72d9f | 49 | #endif |
a8c7c708 | 50 | return 0; |
11a72d9f WD |
51 | } |
52 | ||
53 | int cleanup_before_linux (void) | |
54 | { | |
55 | /* | |
56 | * this function is called just before we call linux | |
57 | * it prepares the processor for linux | |
58 | * | |
59 | * just disable everything that can disturb booting linux | |
60 | */ | |
61 | ||
62 | unsigned long i; | |
63 | ||
64 | disable_interrupts (); | |
65 | ||
66 | /* turn off I-cache */ | |
67 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); | |
68 | i &= ~0x1000; | |
69 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); | |
70 | ||
71 | /* flush I-cache */ | |
72 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); | |
73 | ||
74 | return (0); | |
75 | } | |
76 | ||
77 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
78 | { | |
5f535fe1 | 79 | printf ("resetting ...\n"); |
11a72d9f WD |
80 | |
81 | udelay (50000); /* wait 50 ms */ | |
82 | disable_interrupts (); | |
83 | reset_cpu (0); | |
84 | ||
85 | /*NOTREACHED*/ | |
86 | return (0); | |
87 | } | |
88 | ||
89 | /* taken from blob */ | |
90 | void icache_enable (void) | |
91 | { | |
92 | register u32 i; | |
93 | ||
94 | /* read control register */ | |
95 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); | |
96 | ||
97 | /* set i-cache */ | |
98 | i |= 0x1000; | |
99 | ||
100 | /* write back to control register */ | |
101 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); | |
102 | } | |
103 | ||
104 | void icache_disable (void) | |
105 | { | |
106 | register u32 i; | |
107 | ||
108 | /* read control register */ | |
109 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); | |
110 | ||
111 | /* clear i-cache */ | |
112 | i &= ~0x1000; | |
113 | ||
114 | /* write back to control register */ | |
115 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); | |
116 | ||
117 | /* flush i-cache */ | |
118 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); | |
119 | } | |
120 | ||
121 | int icache_status (void) | |
122 | { | |
123 | register u32 i; | |
124 | ||
125 | /* read control register */ | |
126 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); | |
127 | ||
128 | /* return bit */ | |
129 | return (i & 0x1000); | |
130 | } | |
131 | ||
132 | /* we will never enable dcache, because we have to setup MMU first */ | |
133 | void dcache_enable (void) | |
134 | { | |
135 | return; | |
136 | } | |
137 | ||
138 | void dcache_disable (void) | |
139 | { | |
140 | return; | |
141 | } | |
142 | ||
143 | int dcache_status (void) | |
144 | { | |
145 | return 0; /* always off */ | |
146 | } | |
71f95118 | 147 | |