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[thirdparty/qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
1d93f0f0 24#include "qemu-barrier.h"
7d13299d 25
fbf9eeb3
FB		 26#if !defined(CONFIG_SOFTMMU)
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
84778508 37#ifdef __linux__
fbf9eeb3
FB		 38#include <sys/ucontext.h>
39#endif
84778508 40#endif
fbf9eeb3 41
dfe5fff3 42#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 43// Work around ugly bugs in glibc that mangle global register contents
44#undef env
45#define env cpu_single_env
46#endif
47
36bdbe54
FB		 48int tb_invalidated_flag;
49
f0667e66 50//#define CONFIG_DEBUG_EXEC
9de5e440 51//#define DEBUG_SIGNAL
7d13299d 52
6a4955a8
AL		 53int qemu_cpu_has_work(CPUState *env)
54{
55 return cpu_has_work(env);
56}
57
e4533c7a
FB		 58void cpu_loop_exit(void)
59{
1c3569fe 60 env->current_tb = NULL;
e4533c7a
FB		 61 longjmp(env->jmp_env, 1);
62}
bfed01fc 63
fbf9eeb3
FB		 64/* exit the current TB from a signal handler. The host registers are
65 restored in a state compatible with the CPU emulator
66 */
5fafdf24 67void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 68{
69#if !defined(CONFIG_SOFTMMU)
84778508 70#ifdef __linux__
fbf9eeb3 71 struct ucontext *uc = puc;
84778508
BS		 72#elif defined(__OpenBSD__)
73 struct sigcontext *uc = puc;
74#endif
fbf9eeb3
FB		 75#endif
76
77 env = env1;
78
79 /* XXX: restore cpu registers saved in host registers */
80
81#if !defined(CONFIG_SOFTMMU)
82 if (puc) {
83 /* XXX: use siglongjmp ? */
84778508 84#ifdef __linux__
60e99246
AJ		 85#ifdef __ia64
86 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
87#else
fbf9eeb3 88 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
60e99246 89#endif
84778508
BS		 90#elif defined(__OpenBSD__)
91 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
92#endif
fbf9eeb3
FB		 93 }
94#endif
9a3ea654 95 env->exception_index = -1;
fbf9eeb3
FB		 96 longjmp(env->jmp_env, 1);
97}
98
2e70f6ef
PB		 99/* Execute the code without caching the generated code. An interpreter
100 could be used if available. */
101static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
102{
103 unsigned long next_tb;
104 TranslationBlock *tb;
105
106 /* Should never happen.
107 We only end up here when an existing TB is too long. */
108 if (max_cycles > CF_COUNT_MASK)
109 max_cycles = CF_COUNT_MASK;
110
111 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
112 max_cycles);
113 env->current_tb = tb;
114 /* execute the generated code */
115 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
1c3569fe 116 env->current_tb = NULL;
2e70f6ef
PB		 117
118 if ((next_tb & 3) == 2) {
119 /* Restore PC. This may happen if async event occurs before
120 the TB starts executing. */
622ed360 121 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 122 }
123 tb_phys_invalidate(tb, -1);
124 tb_free(tb);
125}
126
8a40a180
FB		 127static TranslationBlock *tb_find_slow(target_ulong pc,
128 target_ulong cs_base,
c068688b 129 uint64_t flags)
8a40a180
FB		 130{
131 TranslationBlock *tb, **ptb1;
8a40a180 132 unsigned int h;
41c1b1c9
PB		 133 tb_page_addr_t phys_pc, phys_page1, phys_page2;
134 target_ulong virt_page2;
3b46e624 135
8a40a180 136 tb_invalidated_flag = 0;
3b46e624 137
8a40a180 138 /* find translated block using physical mappings */
41c1b1c9 139 phys_pc = get_page_addr_code(env, pc);
8a40a180
FB		 140 phys_page1 = phys_pc & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 h = tb_phys_hash_func(phys_pc);
143 ptb1 = &tb_phys_hash[h];
144 for(;;) {
145 tb = *ptb1;
146 if (!tb)
147 goto not_found;
5fafdf24 148 if (tb->pc == pc &&
8a40a180 149 tb->page_addr[0] == phys_page1 &&
5fafdf24 150 tb->cs_base == cs_base &&
8a40a180
FB		 151 tb->flags == flags) {
152 /* check next page if needed */
153 if (tb->page_addr[1] != -1) {
5fafdf24 154 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 155 TARGET_PAGE_SIZE;
41c1b1c9 156 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 157 if (tb->page_addr[1] == phys_page2)
158 goto found;
159 } else {
160 goto found;
161 }
162 }
163 ptb1 = &tb->phys_hash_next;
164 }
165 not_found:
2e70f6ef
PB		 166 /* if no translated code available, then translate it now */
167 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 168
8a40a180 169 found:
2c90fe2b
KB		 170 /* Move the last found TB to the head of the list */
171 if (likely(*ptb1)) {
172 *ptb1 = tb->phys_hash_next;
173 tb->phys_hash_next = tb_phys_hash[h];
174 tb_phys_hash[h] = tb;
175 }
8a40a180
FB		 176 /* we add the TB in the virtual pc hash table */
177 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 178 return tb;
179}
180
181static inline TranslationBlock *tb_find_fast(void)
182{
183 TranslationBlock *tb;
184 target_ulong cs_base, pc;
6b917547 185 int flags;
8a40a180
FB		 186
187 /* we record a subset of the CPU state. It will
188 always be the same before a given translated block
189 is executed. */
6b917547 190 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 191 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 192 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
193 tb->flags != flags)) {
8a40a180
FB		 194 tb = tb_find_slow(pc, cs_base, flags);
195 }
196 return tb;
197}
198
7d13299d
FB		 199/* main execution loop */
200
1a28cac3
MT		 201volatile sig_atomic_t exit_request;
202
e4533c7a 203int cpu_exec(CPUState *env1)
7d13299d 204{
1d9000e8 205 volatile host_reg_t saved_env_reg;
8a40a180 206 int ret, interrupt_request;
8a40a180 207 TranslationBlock *tb;
c27004ec 208 uint8_t *tc_ptr;
d5975363 209 unsigned long next_tb;
8c6939c0 210
bfed01fc
TS		 211 if (cpu_halted(env1) == EXCP_HALTED)
212 return EXCP_HALTED;
5a1e3cfc 213
5fafdf24 214 cpu_single_env = env1;
6a00d601 215
24ebf5f3
PB		 216 /* the access to env below is actually saving the global register's
217 value, so that files not including target-xyz/exec.h are free to
218 use it. */
219 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
220 saved_env_reg = (host_reg_t) env;
1d93f0f0 221 barrier();
c27004ec 222 env = env1;
e4533c7a 223
c629a4bc 224 if (unlikely(exit_request)) {
1a28cac3 225 env->exit_request = 1;
1a28cac3
MT		 226 }
227
ecb644f4 228#if defined(TARGET_I386)
6792a57b
JK		 229 /* put eflags in CPU temporary format */
230 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
231 DF = 1 - (2 * ((env->eflags >> 10) & 1));
232 CC_OP = CC_OP_EFLAGS;
233 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 234#elif defined(TARGET_SPARC)
e6e5906b
PB		 235#elif defined(TARGET_M68K)
236 env->cc_op = CC_OP_FLAGS;
237 env->cc_dest = env->sr & 0xf;
238 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 239#elif defined(TARGET_ALPHA)
240#elif defined(TARGET_ARM)
241#elif defined(TARGET_PPC)
81ea0e13 242#elif defined(TARGET_LM32)
b779e29e 243#elif defined(TARGET_MICROBLAZE)
6af0bf9c 244#elif defined(TARGET_MIPS)
fdf9b3e8 245#elif defined(TARGET_SH4)
f1ccf904 246#elif defined(TARGET_CRIS)
10ec5117 247#elif defined(TARGET_S390X)
fdf9b3e8 248 /* XXXXX */
e4533c7a
FB		 249#else
250#error unsupported target CPU
251#endif
3fb2ded1 252 env->exception_index = -1;
9d27abd9 253
7d13299d 254 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 255 for(;;) {
256 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 257#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2 258#undef env
6792a57b 259 env = cpu_single_env;
9ddff3d2
BS		 260#define env cpu_single_env
261#endif
3fb2ded1
FB		 262 /* if an exception is pending, we execute it here */
263 if (env->exception_index >= 0) {
264 if (env->exception_index >= EXCP_INTERRUPT) {
265 /* exit request from the cpu execution loop */
266 ret = env->exception_index;
267 break;
72d239ed
AJ		 268 } else {
269#if defined(CONFIG_USER_ONLY)
3fb2ded1 270 /* if user mode only, we simulate a fake exception
9f083493 271 which will be handled outside the cpu execution
3fb2ded1 272 loop */
83479e77 273#if defined(TARGET_I386)
5fafdf24
TS		 274 do_interrupt_user(env->exception_index,
275 env->exception_is_int,
276 env->error_code,
3fb2ded1 277 env->exception_next_eip);
eba01623
FB		 278 /* successfully delivered */
279 env->old_exception = -1;
83479e77 280#endif
3fb2ded1
FB		 281 ret = env->exception_index;
282 break;
72d239ed 283#else
83479e77 284#if defined(TARGET_I386)
3fb2ded1
FB		 285 /* simulate a real cpu exception. On i386, it can
286 trigger new exceptions, but we do not handle
287 double or triple faults yet. */
5fafdf24
TS		 288 do_interrupt(env->exception_index,
289 env->exception_is_int,
290 env->error_code,
d05e66d2 291 env->exception_next_eip, 0);
678dde13
TS		 292 /* successfully delivered */
293 env->old_exception = -1;
ce09776b
FB		 294#elif defined(TARGET_PPC)
295 do_interrupt(env);
81ea0e13
MW		 296#elif defined(TARGET_LM32)
297 do_interrupt(env);
b779e29e
EI		 298#elif defined(TARGET_MICROBLAZE)
299 do_interrupt(env);
6af0bf9c
FB		 300#elif defined(TARGET_MIPS)
301 do_interrupt(env);
e95c8d51 302#elif defined(TARGET_SPARC)
f2bc7e7f 303 do_interrupt(env);
b5ff1b31
FB		 304#elif defined(TARGET_ARM)
305 do_interrupt(env);
fdf9b3e8
FB		 306#elif defined(TARGET_SH4)
307 do_interrupt(env);
eddf68a6
JM		 308#elif defined(TARGET_ALPHA)
309 do_interrupt(env);
f1ccf904
TS		 310#elif defined(TARGET_CRIS)
311 do_interrupt(env);
0633879f
PB		 312#elif defined(TARGET_M68K)
313 do_interrupt(0);
72d239ed 314#endif
301d2908 315 env->exception_index = -1;
83479e77 316#endif
3fb2ded1 317 }
5fafdf24 318 }
9df217a3 319
b5fc09ae 320 next_tb = 0; /* force lookup of first TB */
3fb2ded1 321 for(;;) {
68a79315 322 interrupt_request = env->interrupt_request;
e1638bd8 323 if (unlikely(interrupt_request)) {
324 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
325 /* Mask out external interrupts for this step. */
326 interrupt_request &= ~(CPU_INTERRUPT_HARD |
327 CPU_INTERRUPT_FIQ |
328 CPU_INTERRUPT_SMI |
329 CPU_INTERRUPT_NMI);
330 }
6658ffb8
PB		 331 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
332 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
333 env->exception_index = EXCP_DEBUG;
334 cpu_loop_exit();
335 }
a90b7318 336#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 337 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
81ea0e13 338 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32)
a90b7318
AZ		 339 if (interrupt_request & CPU_INTERRUPT_HALT) {
340 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
341 env->halted = 1;
342 env->exception_index = EXCP_HLT;
343 cpu_loop_exit();
344 }
345#endif
68a79315 346#if defined(TARGET_I386)
b09ea7d5
GN		 347 if (interrupt_request & CPU_INTERRUPT_INIT) {
348 svm_check_intercept(SVM_EXIT_INIT);
349 do_cpu_init(env);
350 env->exception_index = EXCP_HALTED;
351 cpu_loop_exit();
352 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
353 do_cpu_sipi(env);
354 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 355 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
356 !(env->hflags & HF_SMM_MASK)) {
357 svm_check_intercept(SVM_EXIT_SMI);
358 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
359 do_smm_enter();
360 next_tb = 0;
361 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
362 !(env->hflags2 & HF2_NMI_MASK)) {
363 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
364 env->hflags2 |= HF2_NMI_MASK;
365 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
366 next_tb = 0;
79c4f6b0
HY		 367 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
368 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
369 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
370 next_tb = 0;
db620f46
FB		 371 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
372 (((env->hflags2 & HF2_VINTR_MASK) &&
373 (env->hflags2 & HF2_HIF_MASK)) ||
374 (!(env->hflags2 & HF2_VINTR_MASK) &&
375 (env->eflags & IF_MASK &&
376 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
377 int intno;
378 svm_check_intercept(SVM_EXIT_INTR);
379 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
380 intno = cpu_get_pic_interrupt(env);
93fcfe39 381 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 382#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 383#undef env
384 env = cpu_single_env;
385#define env cpu_single_env
386#endif
db620f46
FB		 387 do_interrupt(intno, 0, 0, 0, 1);
388 /* ensure that no TB jump will be modified as
389 the program flow was changed */
390 next_tb = 0;
0573fbfc 391#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 392 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
393 (env->eflags & IF_MASK) &&
394 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
395 int intno;
396 /* FIXME: this should respect TPR */
397 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 398 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 399 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 400 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 401 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 402 next_tb = 0;
907a5b26 403#endif
db620f46 404 }
68a79315 405 }
ce09776b 406#elif defined(TARGET_PPC)
9fddaa0c
FB		 407#if 0
408 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 409 cpu_reset(env);
9fddaa0c
FB		 410 }
411#endif
47103572 412 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 413 ppc_hw_interrupt(env);
414 if (env->pending_interrupts == 0)
415 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 416 next_tb = 0;
ce09776b 417 }
81ea0e13
MW		 418#elif defined(TARGET_LM32)
419 if ((interrupt_request & CPU_INTERRUPT_HARD)
420 && (env->ie & IE_IE)) {
421 env->exception_index = EXCP_IRQ;
422 do_interrupt(env);
423 next_tb = 0;
424 }
b779e29e
EI		 425#elif defined(TARGET_MICROBLAZE)
426 if ((interrupt_request & CPU_INTERRUPT_HARD)
427 && (env->sregs[SR_MSR] & MSR_IE)
428 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
429 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
430 env->exception_index = EXCP_IRQ;
431 do_interrupt(env);
432 next_tb = 0;
433 }
6af0bf9c
FB		 434#elif defined(TARGET_MIPS)
435 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 436 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 437 /* Raise it */
438 env->exception_index = EXCP_EXT_INTERRUPT;
439 env->error_code = 0;
440 do_interrupt(env);
b5fc09ae 441 next_tb = 0;
6af0bf9c 442 }
e95c8d51 443#elif defined(TARGET_SPARC)
d532b26c
IK		 444 if (interrupt_request & CPU_INTERRUPT_HARD) {
445 if (cpu_interrupts_enabled(env) &&
446 env->interrupt_index > 0) {
447 int pil = env->interrupt_index & 0xf;
448 int type = env->interrupt_index & 0xf0;
449
450 if (((type == TT_EXTINT) &&
451 cpu_pil_allowed(env, pil)) ||
452 type != TT_EXTINT) {
453 env->exception_index = env->interrupt_index;
454 do_interrupt(env);
455 next_tb = 0;
456 }
457 }
e95c8d51
FB		 458 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
459 //do_interrupt(0, 0, 0, 0, 0);
460 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 461 }
b5ff1b31
FB		 462#elif defined(TARGET_ARM)
463 if (interrupt_request & CPU_INTERRUPT_FIQ
464 && !(env->uncached_cpsr & CPSR_F)) {
465 env->exception_index = EXCP_FIQ;
466 do_interrupt(env);
b5fc09ae 467 next_tb = 0;
b5ff1b31 468 }
9ee6e8bb
PB		 469 /* ARMv7-M interrupt return works by loading a magic value
470 into the PC. On real hardware the load causes the
471 return to occur. The qemu implementation performs the
472 jump normally, then does the exception return when the
473 CPU tries to execute code at the magic address.
474 This will cause the magic PC value to be pushed to
475 the stack if an interrupt occured at the wrong time.
476 We avoid this by disabling interrupts when
477 pc contains a magic address. */
b5ff1b31 478 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 479 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
480 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 481 env->exception_index = EXCP_IRQ;
482 do_interrupt(env);
b5fc09ae 483 next_tb = 0;
b5ff1b31 484 }
fdf9b3e8 485#elif defined(TARGET_SH4)
e96e2044
TS		 486 if (interrupt_request & CPU_INTERRUPT_HARD) {
487 do_interrupt(env);
b5fc09ae 488 next_tb = 0;
e96e2044 489 }
eddf68a6
JM		 490#elif defined(TARGET_ALPHA)
491 if (interrupt_request & CPU_INTERRUPT_HARD) {
492 do_interrupt(env);
b5fc09ae 493 next_tb = 0;
eddf68a6 494 }
f1ccf904 495#elif defined(TARGET_CRIS)
1b1a38b0 496 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 497 && (env->pregs[PR_CCS] & I_FLAG)
498 && !env->locked_irq) {
1b1a38b0
EI		 499 env->exception_index = EXCP_IRQ;
500 do_interrupt(env);
501 next_tb = 0;
502 }
503 if (interrupt_request & CPU_INTERRUPT_NMI
504 && (env->pregs[PR_CCS] & M_FLAG)) {
505 env->exception_index = EXCP_NMI;
f1ccf904 506 do_interrupt(env);
b5fc09ae 507 next_tb = 0;
f1ccf904 508 }
0633879f
PB		 509#elif defined(TARGET_M68K)
510 if (interrupt_request & CPU_INTERRUPT_HARD
511 && ((env->sr & SR_I) >> SR_I_SHIFT)
512 < env->pending_level) {
513 /* Real hardware gets the interrupt vector via an
514 IACK cycle at this point. Current emulated
515 hardware doesn't rely on this, so we
516 provide/save the vector when the interrupt is
517 first signalled. */
518 env->exception_index = env->pending_vector;
519 do_interrupt(1);
b5fc09ae 520 next_tb = 0;
0633879f 521 }
68a79315 522#endif
9d05095e
FB		 523 /* Don't use the cached interupt_request value,
524 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 525 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 526 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
527 /* ensure that no TB jump will be modified as
528 the program flow was changed */
b5fc09ae 529 next_tb = 0;
bf3e8bf1 530 }
be214e6c
AJ		 531 }
532 if (unlikely(env->exit_request)) {
533 env->exit_request = 0;
534 env->exception_index = EXCP_INTERRUPT;
535 cpu_loop_exit();
3fb2ded1 536 }
a73b1fd9 537#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 538 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 539 /* restore flags in standard format */
ecb644f4 540#if defined(TARGET_I386)
a7812ae4 541 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 542 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 543 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 544#elif defined(TARGET_M68K)
545 cpu_m68k_flush_flags(env, env->cc_op);
546 env->cc_op = CC_OP_FLAGS;
547 env->sr = (env->sr & 0xffe0)
548 | env->cc_dest | (env->cc_x << 4);
93fcfe39 549 log_cpu_state(env, 0);
e4533c7a 550#else
a73b1fd9 551 log_cpu_state(env, 0);
e4533c7a 552#endif
3fb2ded1 553 }
a73b1fd9 554#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 555 spin_lock(&tb_lock);
8a40a180 556 tb = tb_find_fast();
d5975363
PB		 557 /* Note: we do it here to avoid a gcc bug on Mac OS X when
558 doing it in tb_find_slow */
559 if (tb_invalidated_flag) {
560 /* as some TB could have been invalidated because
561 of memory exceptions while generating the code, we
562 must recompute the hash index here */
563 next_tb = 0;
2e70f6ef 564 tb_invalidated_flag = 0;
d5975363 565 }
f0667e66 566#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 567 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
568 (long)tb->tc_ptr, tb->pc,
569 lookup_symbol(tb->pc));
9d27abd9 570#endif
8a40a180
FB		 571 /* see if we can patch the calling TB. When the TB
572 spans two pages, we cannot safely do a direct
573 jump. */
040f2fb2 574 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 575 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 576 }
d5975363 577 spin_unlock(&tb_lock);
55e8b85e 578
579 /* cpu_interrupt might be called while translating the
580 TB, but before it is linked into a potentially
581 infinite loop and becomes env->current_tb. Avoid
582 starting execution if there is a pending interrupt. */
b0052d15
JK		 583 env->current_tb = tb;
584 barrier();
585 if (likely(!env->exit_request)) {
2e70f6ef 586 tc_ptr = tb->tc_ptr;
3fb2ded1 587 /* execute the generated code */
dfe5fff3 588#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 589#undef env
2e70f6ef 590 env = cpu_single_env;
572a9d4a
BS		 591#define env cpu_single_env
592#endif
2e70f6ef 593 next_tb = tcg_qemu_tb_exec(tc_ptr);
2e70f6ef 594 if ((next_tb & 3) == 2) {
bf20dc07 595 /* Instruction counter expired. */
2e70f6ef
PB		 596 int insns_left;
597 tb = (TranslationBlock *)(long)(next_tb & ~3);
598 /* Restore PC. */
622ed360 599 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 600 insns_left = env->icount_decr.u32;
601 if (env->icount_extra && insns_left >= 0) {
602 /* Refill decrementer and continue execution. */
603 env->icount_extra += insns_left;
604 if (env->icount_extra > 0xffff) {
605 insns_left = 0xffff;
606 } else {
607 insns_left = env->icount_extra;
608 }
609 env->icount_extra -= insns_left;
610 env->icount_decr.u16.low = insns_left;
611 } else {
612 if (insns_left > 0) {
613 /* Execute remaining instructions. */
614 cpu_exec_nocache(insns_left, tb);
615 }
616 env->exception_index = EXCP_INTERRUPT;
617 next_tb = 0;
618 cpu_loop_exit();
619 }
620 }
621 }
b0052d15 622 env->current_tb = NULL;
4cbf74b6
FB		 623 /* reset soft MMU for next block (it can currently
624 only be set by a memory fault) */
50a518e3 625 } /* for(;;) */
7d13299d 626 }
3fb2ded1
FB		 627 } /* for(;;) */
628
7d13299d 629
e4533c7a 630#if defined(TARGET_I386)
9de5e440 631 /* restore flags in standard format */
a7812ae4 632 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 633#elif defined(TARGET_ARM)
b7bcbe95 634 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 635#elif defined(TARGET_SPARC)
67867308 636#elif defined(TARGET_PPC)
81ea0e13 637#elif defined(TARGET_LM32)
e6e5906b
PB		 638#elif defined(TARGET_M68K)
639 cpu_m68k_flush_flags(env, env->cc_op);
640 env->cc_op = CC_OP_FLAGS;
641 env->sr = (env->sr & 0xffe0)
642 | env->cc_dest | (env->cc_x << 4);
b779e29e 643#elif defined(TARGET_MICROBLAZE)
6af0bf9c 644#elif defined(TARGET_MIPS)
fdf9b3e8 645#elif defined(TARGET_SH4)
eddf68a6 646#elif defined(TARGET_ALPHA)
f1ccf904 647#elif defined(TARGET_CRIS)
10ec5117 648#elif defined(TARGET_S390X)
fdf9b3e8 649 /* XXXXX */
e4533c7a
FB		 650#else
651#error unsupported target CPU
652#endif
1057eaa7
PB		 653
654 /* restore global registers */
1d93f0f0 655 barrier();
24ebf5f3 656 env = (void *) saved_env_reg;
1057eaa7 657
6a00d601 658 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 659 cpu_single_env = NULL;
7d13299d
FB		 660 return ret;
661}
6dbad63e 662
fbf9eeb3
FB		 663/* must only be called from the generated code as an exception can be
664 generated */
665void tb_invalidate_page_range(target_ulong start, target_ulong end)
666{
dc5d0b3d
FB		 667 /* XXX: cannot enable it yet because it yields to MMU exception
668 where NIP != read address on PowerPC */
669#if 0
fbf9eeb3
FB		 670 target_ulong phys_addr;
671 phys_addr = get_phys_addr_code(env, start);
672 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 673#endif
fbf9eeb3
FB		 674}
675
1a18c71b 676#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 677
6dbad63e
FB		 678void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
679{
680 CPUX86State *saved_env;
681
682 saved_env = env;
683 env = s;
a412ac57 684 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 685 selector &= 0xffff;
5fafdf24 686 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 687 (selector << 4), 0xffff, 0);
a513fe19 688 } else {
5d97559d 689 helper_load_seg(seg_reg, selector);
a513fe19 690 }
6dbad63e
FB		 691 env = saved_env;
692}
9de5e440 693
6f12a2a6 694void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 695{
696 CPUX86State *saved_env;
697
698 saved_env = env;
699 env = s;
3b46e624 700
6f12a2a6 701 helper_fsave(ptr, data32);
d0a1ffc9
FB		 702
703 env = saved_env;
704}
705
6f12a2a6 706void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 707{
708 CPUX86State *saved_env;
709
710 saved_env = env;
711 env = s;
3b46e624 712
6f12a2a6 713 helper_frstor(ptr, data32);
d0a1ffc9
FB		 714
715 env = saved_env;
716}
717
e4533c7a
FB		 718#endif /* TARGET_I386 */
719
67b915a5
FB		 720#if !defined(CONFIG_SOFTMMU)
721
3fb2ded1 722#if defined(TARGET_I386)
0b5c1ce8
NF		 723#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
724#else
725#define EXCEPTION_ACTION cpu_loop_exit()
726#endif
3fb2ded1 727
b56dad1c 728/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 729 the effective address of the memory exception. 'is_write' is 1 if a
730 write caused the exception and otherwise 0'. 'old_set' is the
731 signal set which should be restored */
2b413144 732static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 733 int is_write, sigset_t *old_set,
bf3e8bf1 734 void *puc)
9de5e440 735{
a513fe19
FB		 736 TranslationBlock *tb;
737 int ret;
68a79315 738
83479e77
FB		 739 if (cpu_single_env)
740 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 741#if defined(DEBUG_SIGNAL)
5fafdf24 742 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 743 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 744#endif
25eb4484 745 /* XXX: locking issue */
53a5960a 746 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 747 return 1;
748 }
fbf9eeb3 749
3fb2ded1 750 /* see if it is an MMU fault */
0b5c1ce8 751 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 752 if (ret < 0)
753 return 0; /* not an MMU fault */
754 if (ret == 0)
755 return 1; /* the MMU fault was handled without causing real CPU fault */
756 /* now we have a real cpu fault */
757 tb = tb_find_pc(pc);
758 if (tb) {
759 /* the PC is inside the translated code. It means that we have
760 a virtual CPU fault */
761 cpu_restore_state(tb, env, pc, puc);
762 }
68016c62 763
68016c62
FB		 764 /* we restore the process signal mask as the sigreturn should
765 do it (XXX: use sigsetjmp) */
766 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 767 EXCEPTION_ACTION;
e6e5906b 768
e6e5906b 769 /* never comes here */
67867308
FB		 770 return 1;
771}
6af0bf9c 772
2b413144
FB		 773#if defined(__i386__)
774
d8ecc0b9
FB		 775#if defined(__APPLE__)
776# include <sys/ucontext.h>
777
778# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
779# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
780# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 781# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 782#elif defined (__NetBSD__)
783# include <ucontext.h>
784
785# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
786# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
787# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
788# define MASK_sig(context) ((context)->uc_sigmask)
789#elif defined (__FreeBSD__) || defined(__DragonFly__)
790# include <ucontext.h>
791
792# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
793# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
794# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
795# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 796#elif defined(__OpenBSD__)
797# define EIP_sig(context) ((context)->sc_eip)
798# define TRAP_sig(context) ((context)->sc_trapno)
799# define ERROR_sig(context) ((context)->sc_err)
800# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 801#else
802# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
803# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
804# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 805# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 806#endif
807
5fafdf24 808int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 809 void *puc)
9de5e440 810{
5a7b542b 811 siginfo_t *info = pinfo;
78cfb07f
JL		 812#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
813 ucontext_t *uc = puc;
814#elif defined(__OpenBSD__)
d39bb24a
BS		 815 struct sigcontext *uc = puc;
816#else
9de5e440 817 struct ucontext *uc = puc;
d39bb24a 818#endif
9de5e440 819 unsigned long pc;
bf3e8bf1 820 int trapno;
97eb5b14 821
d691f669
FB		 822#ifndef REG_EIP
823/* for glibc 2.1 */
fd6ce8f6
FB		 824#define REG_EIP EIP
825#define REG_ERR ERR
826#define REG_TRAPNO TRAPNO
d691f669 827#endif
d8ecc0b9
FB		 828 pc = EIP_sig(uc);
829 trapno = TRAP_sig(uc);
ec6338ba
FB		 830 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
831 trapno == 0xe ?
832 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 833 &MASK_sig(uc), puc);
2b413144
FB		 834}
835
bc51c5c9
FB		 836#elif defined(__x86_64__)
837
b3efe5c8 838#ifdef __NetBSD__
d397abbd
BS		 839#define PC_sig(context) _UC_MACHINE_PC(context)
840#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
841#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
842#define MASK_sig(context) ((context)->uc_sigmask)
843#elif defined(__OpenBSD__)
844#define PC_sig(context) ((context)->sc_rip)
845#define TRAP_sig(context) ((context)->sc_trapno)
846#define ERROR_sig(context) ((context)->sc_err)
847#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 848#elif defined (__FreeBSD__) || defined(__DragonFly__)
849#include <ucontext.h>
850
851#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
852#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
853#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
854#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 855#else
d397abbd
BS		 856#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
857#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
858#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
859#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 860#endif
861
5a7b542b 862int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 863 void *puc)
864{
5a7b542b 865 siginfo_t *info = pinfo;
bc51c5c9 866 unsigned long pc;
78cfb07f 867#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 868 ucontext_t *uc = puc;
d397abbd
BS		 869#elif defined(__OpenBSD__)
870 struct sigcontext *uc = puc;
b3efe5c8
BS		 871#else
872 struct ucontext *uc = puc;
873#endif
bc51c5c9 874
d397abbd 875 pc = PC_sig(uc);
5fafdf24 876 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 877 TRAP_sig(uc) == 0xe ?
878 (ERROR_sig(uc) >> 1) & 1 : 0,
879 &MASK_sig(uc), puc);
bc51c5c9
FB		 880}
881
e58ffeb3 882#elif defined(_ARCH_PPC)
2b413144 883
83fb7adf
FB		 884/***********************************************************************
885 * signal context platform-specific definitions
886 * From Wine
887 */
888#ifdef linux
889/* All Registers access - only for local access */
890# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
891/* Gpr Registers access */
892# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
893# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
894# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
895# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
896# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
897# define LR_sig(context) REG_sig(link, context) /* Link register */
898# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
899/* Float Registers access */
900# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
901# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
902/* Exception Registers access */
903# define DAR_sig(context) REG_sig(dar, context)
904# define DSISR_sig(context) REG_sig(dsisr, context)
905# define TRAP_sig(context) REG_sig(trap, context)
906#endif /* linux */
907
58d9b1e0
JL		 908#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
909#include <ucontext.h>
910# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
911# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
912# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
913# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
914# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
915# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
916/* Exception Registers access */
917# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
918# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
919# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
920#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
921
83fb7adf
FB		 922#ifdef __APPLE__
923# include <sys/ucontext.h>
924typedef struct ucontext SIGCONTEXT;
925/* All Registers access - only for local access */
926# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
927# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
928# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
929# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
930/* Gpr Registers access */
931# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
932# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
933# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
934# define CTR_sig(context) REG_sig(ctr, context)
935# define XER_sig(context) REG_sig(xer, context) /* Link register */
936# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
937# define CR_sig(context) REG_sig(cr, context) /* Condition register */
938/* Float Registers access */
939# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
940# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
941/* Exception Registers access */
942# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
943# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
944# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
945#endif /* __APPLE__ */
946
5fafdf24 947int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 948 void *puc)
2b413144 949{
5a7b542b 950 siginfo_t *info = pinfo;
58d9b1e0
JL		 951#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
952 ucontext_t *uc = puc;
953#else
25eb4484 954 struct ucontext *uc = puc;
58d9b1e0 955#endif
25eb4484 956 unsigned long pc;
25eb4484
FB		 957 int is_write;
958
83fb7adf 959 pc = IAR_sig(uc);
25eb4484
FB		 960 is_write = 0;
961#if 0
962 /* ppc 4xx case */
83fb7adf 963 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 964 is_write = 1;
965#else
83fb7adf 966 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 967 is_write = 1;
968#endif
5fafdf24 969 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 970 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 971}
972
2f87c607
FB		 973#elif defined(__alpha__)
974
5fafdf24 975int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 976 void *puc)
977{
5a7b542b 978 siginfo_t *info = pinfo;
2f87c607
FB		 979 struct ucontext *uc = puc;
980 uint32_t *pc = uc->uc_mcontext.sc_pc;
981 uint32_t insn = *pc;
982 int is_write = 0;
983
8c6939c0 984 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 985 switch (insn >> 26) {
986 case 0x0d: // stw
987 case 0x0e: // stb
988 case 0x0f: // stq_u
989 case 0x24: // stf
990 case 0x25: // stg
991 case 0x26: // sts
992 case 0x27: // stt
993 case 0x2c: // stl
994 case 0x2d: // stq
995 case 0x2e: // stl_c
996 case 0x2f: // stq_c
997 is_write = 1;
998 }
999
5fafdf24 1000 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1001 is_write, &uc->uc_sigmask, puc);
2f87c607 1002}
8c6939c0
FB		 1003#elif defined(__sparc__)
1004
5fafdf24 1005int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1006 void *puc)
8c6939c0 1007{
5a7b542b 1008 siginfo_t *info = pinfo;
8c6939c0
FB		 1009 int is_write;
1010 uint32_t insn;
dfe5fff3 1011#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1012 uint32_t *regs = (uint32_t *)(info + 1);
1013 void *sigmask = (regs + 20);
8c6939c0 1014 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1015 unsigned long pc = regs[1];
1016#else
84778508 1017#ifdef __linux__
c9e1e2b0
BS		 1018 struct sigcontext *sc = puc;
1019 unsigned long pc = sc->sigc_regs.tpc;
1020 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1021#elif defined(__OpenBSD__)
1022 struct sigcontext *uc = puc;
1023 unsigned long pc = uc->sc_pc;
1024 void *sigmask = (void *)(long)uc->sc_mask;
1025#endif
c9e1e2b0
BS		 1026#endif
1027
8c6939c0
FB		 1028 /* XXX: need kernel patch to get write flag faster */
1029 is_write = 0;
1030 insn = *(uint32_t *)pc;
1031 if ((insn >> 30) == 3) {
1032 switch((insn >> 19) & 0x3f) {
1033 case 0x05: // stb
d877fa5a 1034 case 0x15: // stba
8c6939c0 1035 case 0x06: // sth
d877fa5a 1036 case 0x16: // stha
8c6939c0 1037 case 0x04: // st
d877fa5a 1038 case 0x14: // sta
8c6939c0 1039 case 0x07: // std
d877fa5a
BS		 1040 case 0x17: // stda
1041 case 0x0e: // stx
1042 case 0x1e: // stxa
8c6939c0 1043 case 0x24: // stf
d877fa5a 1044 case 0x34: // stfa
8c6939c0 1045 case 0x27: // stdf
d877fa5a
BS		 1046 case 0x37: // stdfa
1047 case 0x26: // stqf
1048 case 0x36: // stqfa
8c6939c0 1049 case 0x25: // stfsr
d877fa5a
BS		 1050 case 0x3c: // casa
1051 case 0x3e: // casxa
8c6939c0
FB		 1052 is_write = 1;
1053 break;
1054 }
1055 }
5fafdf24 1056 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1057 is_write, sigmask, NULL);
8c6939c0
FB		 1058}
1059
1060#elif defined(__arm__)
1061
5fafdf24 1062int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1063 void *puc)
8c6939c0 1064{
5a7b542b 1065 siginfo_t *info = pinfo;
8c6939c0
FB		 1066 struct ucontext *uc = puc;
1067 unsigned long pc;
1068 int is_write;
3b46e624 1069
48bbf11b 1070#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1071 pc = uc->uc_mcontext.gregs[R15];
1072#else
4eee57f5 1073 pc = uc->uc_mcontext.arm_pc;
5c49b363 1074#endif
8c6939c0
FB		 1075 /* XXX: compute is_write */
1076 is_write = 0;
5fafdf24 1077 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1078 is_write,
f3a9676a 1079 &uc->uc_sigmask, puc);
8c6939c0
FB		 1080}
1081
38e584a0
FB		 1082#elif defined(__mc68000)
1083
5fafdf24 1084int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1085 void *puc)
1086{
5a7b542b 1087 siginfo_t *info = pinfo;
38e584a0
FB		 1088 struct ucontext *uc = puc;
1089 unsigned long pc;
1090 int is_write;
3b46e624 1091
38e584a0
FB		 1092 pc = uc->uc_mcontext.gregs[16];
1093 /* XXX: compute is_write */
1094 is_write = 0;
5fafdf24 1095 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1096 is_write,
bf3e8bf1 1097 &uc->uc_sigmask, puc);
38e584a0
FB		 1098}
1099
b8076a74
FB		 1100#elif defined(__ia64)
1101
1102#ifndef __ISR_VALID
1103 /* This ought to be in <bits/siginfo.h>... */
1104# define __ISR_VALID 1
b8076a74
FB		 1105#endif
1106
5a7b542b 1107int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1108{
5a7b542b 1109 siginfo_t *info = pinfo;
b8076a74
FB		 1110 struct ucontext *uc = puc;
1111 unsigned long ip;
1112 int is_write = 0;
1113
1114 ip = uc->uc_mcontext.sc_ip;
1115 switch (host_signum) {
1116 case SIGILL:
1117 case SIGFPE:
1118 case SIGSEGV:
1119 case SIGBUS:
1120 case SIGTRAP:
fd4a43e4 1121 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1122 /* ISR.W (write-access) is bit 33: */
1123 is_write = (info->si_isr >> 33) & 1;
1124 break;
1125
1126 default:
1127 break;
1128 }
1129 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1130 is_write,
60e99246 1131 (sigset_t *)&uc->uc_sigmask, puc);
b8076a74
FB		 1132}
1133
90cb9493
FB		 1134#elif defined(__s390__)
1135
5fafdf24 1136int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1137 void *puc)
1138{
5a7b542b 1139 siginfo_t *info = pinfo;
90cb9493
FB		 1140 struct ucontext *uc = puc;
1141 unsigned long pc;
6a1621b9
RH		 1142 uint16_t *pinsn;
1143 int is_write = 0;
3b46e624 1144
90cb9493 1145 pc = uc->uc_mcontext.psw.addr;
6a1621b9
RH		 1146
1147 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1148 of the normal 2 arguments. The 3rd argument contains the "int_code"
1149 from the hardware which does in fact contain the is_write value.
1150 The rt signal handler, as far as I can tell, does not give this value
1151 at all. Not that we could get to it from here even if it were. */
1152 /* ??? This is not even close to complete, since it ignores all
1153 of the read-modify-write instructions. */
1154 pinsn = (uint16_t *)pc;
1155 switch (pinsn[0] >> 8) {
1156 case 0x50: /* ST */
1157 case 0x42: /* STC */
1158 case 0x40: /* STH */
1159 is_write = 1;
1160 break;
1161 case 0xc4: /* RIL format insns */
1162 switch (pinsn[0] & 0xf) {
1163 case 0xf: /* STRL */
1164 case 0xb: /* STGRL */
1165 case 0x7: /* STHRL */
1166 is_write = 1;
1167 }
1168 break;
1169 case 0xe3: /* RXY format insns */
1170 switch (pinsn[2] & 0xff) {
1171 case 0x50: /* STY */
1172 case 0x24: /* STG */
1173 case 0x72: /* STCY */
1174 case 0x70: /* STHY */
1175 case 0x8e: /* STPQ */
1176 case 0x3f: /* STRVH */
1177 case 0x3e: /* STRV */
1178 case 0x2f: /* STRVG */
1179 is_write = 1;
1180 }
1181 break;
1182 }
5fafdf24 1183 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1184 is_write, &uc->uc_sigmask, puc);
1185}
1186
1187#elif defined(__mips__)
1188
5fafdf24 1189int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1190 void *puc)
1191{
9617efe8 1192 siginfo_t *info = pinfo;
c4b89d18
TS		 1193 struct ucontext *uc = puc;
1194 greg_t pc = uc->uc_mcontext.pc;
1195 int is_write;
3b46e624 1196
c4b89d18
TS		 1197 /* XXX: compute is_write */
1198 is_write = 0;
5fafdf24 1199 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1200 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1201}
1202
f54b3f92
AJ		 1203#elif defined(__hppa__)
1204
1205int cpu_signal_handler(int host_signum, void *pinfo,
1206 void *puc)
1207{
1208 struct siginfo *info = pinfo;
1209 struct ucontext *uc = puc;
f57040be
RH		 1210 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1211 uint32_t insn = *(uint32_t *)pc;
1212 int is_write = 0;
1213
1214 /* XXX: need kernel patch to get write flag faster. */
1215 switch (insn >> 26) {
1216 case 0x1a: /* STW */
1217 case 0x19: /* STH */
1218 case 0x18: /* STB */
1219 case 0x1b: /* STWM */
1220 is_write = 1;
1221 break;
1222
1223 case 0x09: /* CSTWX, FSTWX, FSTWS */
1224 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1225 /* Distinguish from coprocessor load ... */
1226 is_write = (insn >> 9) & 1;
1227 break;
1228
1229 case 0x03:
1230 switch ((insn >> 6) & 15) {
1231 case 0xa: /* STWS */
1232 case 0x9: /* STHS */
1233 case 0x8: /* STBS */
1234 case 0xe: /* STWAS */
1235 case 0xc: /* STBYS */
1236 is_write = 1;
1237 }
1238 break;
1239 }
f54b3f92 1240
f54b3f92 1241 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
f57040be 1242 is_write, &uc->uc_sigmask, puc);
f54b3f92
AJ		 1243}
1244
9de5e440 1245#else
2b413144 1246
3fb2ded1 1247#error host CPU specific signal handler needed
2b413144 1248
9de5e440 1249#endif
67b915a5
FB		 1250
1251#endif /* !defined(CONFIG_SOFTMMU) */
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