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cpu-exec: simplify align_clocks
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7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
6db8b538 21#include "trace.h"
76cad711 22#include "disas/disas.h"
7cb69cae 23#include "tcg.h"
1de7afc9 24#include "qemu/atomic.h"
9c17d615 25#include "sysemu/qtest.h"
c2aa5f81
ST
26#include "qemu/timer.h"
27
28/* -icount align implementation. */
29
30typedef struct SyncClocks {
31 int64_t diff_clk;
32 int64_t last_cpu_icount;
7f7bc144 33 int64_t realtime_clock;
c2aa5f81
ST
34} SyncClocks;
35
36#if !defined(CONFIG_USER_ONLY)
37/* Allow the guest to have a max 3ms advance.
38 * The difference between the 2 clocks could therefore
39 * oscillate around 0.
40 */
41#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
42#define THRESHOLD_REDUCE 1.5
43#define MAX_DELAY_PRINT_RATE 2000000000LL
44#define MAX_NB_PRINTS 100
c2aa5f81
ST
45
46static void align_clocks(SyncClocks *sc, const CPUState *cpu)
47{
48 int64_t cpu_icount;
49
50 if (!icount_align_option) {
51 return;
52 }
53
54 cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
55 sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
56 sc->last_cpu_icount = cpu_icount;
57
58 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
59#ifndef _WIN32
60 struct timespec sleep_delay, rem_delay;
61 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
62 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
63 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 64 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
65 } else {
66 sc->diff_clk = 0;
67 }
68#else
69 Sleep(sc->diff_clk / SCALE_MS);
70 sc->diff_clk = 0;
71#endif
72 }
73}
74
7f7bc144
ST
75static void print_delay(const SyncClocks *sc)
76{
77 static float threshold_delay;
78 static int64_t last_realtime_clock;
79 static int nb_prints;
80
81 if (icount_align_option &&
82 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
83 nb_prints < MAX_NB_PRINTS) {
84 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
85 (-sc->diff_clk / (float)1000000000LL <
86 (threshold_delay - THRESHOLD_REDUCE))) {
87 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
88 printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
89 threshold_delay - 1,
90 threshold_delay);
91 nb_prints++;
92 last_realtime_clock = sc->realtime_clock;
93 }
94 }
95}
96
c2aa5f81
ST
97static void init_delay_params(SyncClocks *sc,
98 const CPUState *cpu)
99{
100 if (!icount_align_option) {
101 return;
102 }
7f7bc144 103 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
c2aa5f81 104 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
7f7bc144 105 sc->realtime_clock +
c2aa5f81
ST
106 cpu_get_clock_offset();
107 sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
27498bef
ST
108 if (sc->diff_clk < max_delay) {
109 max_delay = sc->diff_clk;
110 }
111 if (sc->diff_clk > max_advance) {
112 max_advance = sc->diff_clk;
113 }
7f7bc144
ST
114
115 /* Print every 2s max if the guest is late. We limit the number
116 of printed messages to NB_PRINT_MAX(currently 100) */
117 print_delay(sc);
c2aa5f81
ST
118}
119#else
120static void align_clocks(SyncClocks *sc, const CPUState *cpu)
121{
122}
123
124static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
125{
126}
127#endif /* CONFIG USER ONLY */
7d13299d 128
5638d180 129void cpu_loop_exit(CPUState *cpu)
e4533c7a 130{
d77953b9 131 cpu->current_tb = NULL;
6f03bef0 132 siglongjmp(cpu->jmp_env, 1);
e4533c7a 133}
bfed01fc 134
fbf9eeb3
FB
135/* exit the current TB from a signal handler. The host registers are
136 restored in a state compatible with the CPU emulator
137 */
9eff14f3 138#if defined(CONFIG_SOFTMMU)
0ea8cb88 139void cpu_resume_from_signal(CPUState *cpu, void *puc)
9eff14f3 140{
9eff14f3
BS
141 /* XXX: restore cpu registers saved in host registers */
142
27103424 143 cpu->exception_index = -1;
6f03bef0 144 siglongjmp(cpu->jmp_env, 1);
9eff14f3 145}
9eff14f3 146#endif
fbf9eeb3 147
77211379
PM
148/* Execute a TB, and fix up the CPU state afterwards if necessary */
149static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
150{
151 CPUArchState *env = cpu->env_ptr;
03afa5f8
RH
152 uintptr_t next_tb;
153
154#if defined(DEBUG_DISAS)
155 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
156#if defined(TARGET_I386)
157 log_cpu_state(cpu, CPU_DUMP_CCOP);
158#elif defined(TARGET_M68K)
159 /* ??? Should not modify env state for dumping. */
160 cpu_m68k_flush_flags(env, env->cc_op);
161 env->cc_op = CC_OP_FLAGS;
162 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
163 log_cpu_state(cpu, 0);
164#else
165 log_cpu_state(cpu, 0);
166#endif
167 }
168#endif /* DEBUG_DISAS */
169
626cf8f4 170 cpu->can_do_io = 0;
03afa5f8 171 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
626cf8f4 172 cpu->can_do_io = 1;
6db8b538
AB
173 trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
174 next_tb & TB_EXIT_MASK);
175
77211379
PM
176 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
177 /* We didn't start executing this TB (eg because the instruction
178 * counter hit zero); we must restore the guest PC to the address
179 * of the start of the TB.
180 */
bdf7ae5b 181 CPUClass *cc = CPU_GET_CLASS(cpu);
77211379 182 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
bdf7ae5b
AF
183 if (cc->synchronize_from_tb) {
184 cc->synchronize_from_tb(cpu, tb);
185 } else {
186 assert(cc->set_pc);
187 cc->set_pc(cpu, tb->pc);
188 }
77211379 189 }
378df4b2
PM
190 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
191 /* We were asked to stop executing TBs (probably a pending
192 * interrupt. We've now stopped, so clear the flag.
193 */
194 cpu->tcg_exit_req = 0;
195 }
77211379
PM
196 return next_tb;
197}
198
2e70f6ef
PB
199/* Execute the code without caching the generated code. An interpreter
200 could be used if available. */
9349b4f9 201static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
cea5f9a2 202 TranslationBlock *orig_tb)
2e70f6ef 203{
d77953b9 204 CPUState *cpu = ENV_GET_CPU(env);
2e70f6ef 205 TranslationBlock *tb;
b4ac20b4
PD
206 target_ulong pc = orig_tb->pc;
207 target_ulong cs_base = orig_tb->cs_base;
208 uint64_t flags = orig_tb->flags;
2e70f6ef
PB
209
210 /* Should never happen.
211 We only end up here when an existing TB is too long. */
212 if (max_cycles > CF_COUNT_MASK)
213 max_cycles = CF_COUNT_MASK;
214
b4ac20b4
PD
215 /* tb_gen_code can flush our orig_tb, invalidate it now */
216 tb_phys_invalidate(orig_tb, -1);
217 tb = tb_gen_code(cpu, pc, cs_base, flags,
d8a499f1 218 max_cycles | CF_NOCACHE);
d77953b9 219 cpu->current_tb = tb;
2e70f6ef 220 /* execute the generated code */
6db8b538 221 trace_exec_tb_nocache(tb, tb->pc);
77211379 222 cpu_tb_exec(cpu, tb->tc_ptr);
d77953b9 223 cpu->current_tb = NULL;
2e70f6ef
PB
224 tb_phys_invalidate(tb, -1);
225 tb_free(tb);
226}
227
9349b4f9 228static TranslationBlock *tb_find_slow(CPUArchState *env,
cea5f9a2 229 target_ulong pc,
8a40a180 230 target_ulong cs_base,
c068688b 231 uint64_t flags)
8a40a180 232{
8cd70437 233 CPUState *cpu = ENV_GET_CPU(env);
8a40a180 234 TranslationBlock *tb, **ptb1;
8a40a180 235 unsigned int h;
337fc758 236 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 237 target_ulong virt_page2;
3b46e624 238
5e5f07e0 239 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
3b46e624 240
8a40a180 241 /* find translated block using physical mappings */
41c1b1c9 242 phys_pc = get_page_addr_code(env, pc);
8a40a180 243 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180 244 h = tb_phys_hash_func(phys_pc);
5e5f07e0 245 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
8a40a180
FB
246 for(;;) {
247 tb = *ptb1;
248 if (!tb)
249 goto not_found;
5fafdf24 250 if (tb->pc == pc &&
8a40a180 251 tb->page_addr[0] == phys_page1 &&
5fafdf24 252 tb->cs_base == cs_base &&
8a40a180
FB
253 tb->flags == flags) {
254 /* check next page if needed */
255 if (tb->page_addr[1] != -1) {
337fc758
BS
256 tb_page_addr_t phys_page2;
257
5fafdf24 258 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 259 TARGET_PAGE_SIZE;
41c1b1c9 260 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB
261 if (tb->page_addr[1] == phys_page2)
262 goto found;
263 } else {
264 goto found;
265 }
266 }
267 ptb1 = &tb->phys_hash_next;
268 }
269 not_found:
2e70f6ef 270 /* if no translated code available, then translate it now */
648f034c 271 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
3b46e624 272
8a40a180 273 found:
2c90fe2b
KB
274 /* Move the last found TB to the head of the list */
275 if (likely(*ptb1)) {
276 *ptb1 = tb->phys_hash_next;
5e5f07e0
EV
277 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
278 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
2c90fe2b 279 }
8a40a180 280 /* we add the TB in the virtual pc hash table */
8cd70437 281 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB
282 return tb;
283}
284
9349b4f9 285static inline TranslationBlock *tb_find_fast(CPUArchState *env)
8a40a180 286{
8cd70437 287 CPUState *cpu = ENV_GET_CPU(env);
8a40a180
FB
288 TranslationBlock *tb;
289 target_ulong cs_base, pc;
6b917547 290 int flags;
8a40a180
FB
291
292 /* we record a subset of the CPU state. It will
293 always be the same before a given translated block
294 is executed. */
6b917547 295 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
8cd70437 296 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS
297 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
298 tb->flags != flags)) {
cea5f9a2 299 tb = tb_find_slow(env, pc, cs_base, flags);
8a40a180
FB
300 }
301 return tb;
302}
303
9349b4f9 304static void cpu_handle_debug_exception(CPUArchState *env)
1009d2ed 305{
ff4700b0 306 CPUState *cpu = ENV_GET_CPU(env);
86025ee4 307 CPUClass *cc = CPU_GET_CLASS(cpu);
1009d2ed
JK
308 CPUWatchpoint *wp;
309
ff4700b0
AF
310 if (!cpu->watchpoint_hit) {
311 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
312 wp->flags &= ~BP_WATCHPOINT_HIT;
313 }
314 }
86025ee4
PM
315
316 cc->debug_excp_handler(cpu);
1009d2ed
JK
317}
318
7d13299d
FB
319/* main execution loop */
320
1a28cac3
MT
321volatile sig_atomic_t exit_request;
322
9349b4f9 323int cpu_exec(CPUArchState *env)
7d13299d 324{
c356a1bc 325 CPUState *cpu = ENV_GET_CPU(env);
97a8ea5a 326 CPUClass *cc = CPU_GET_CLASS(cpu);
693fa551
AF
327#ifdef TARGET_I386
328 X86CPU *x86_cpu = X86_CPU(cpu);
97a8ea5a 329#endif
8a40a180 330 int ret, interrupt_request;
8a40a180 331 TranslationBlock *tb;
c27004ec 332 uint8_t *tc_ptr;
3e9bd63a 333 uintptr_t next_tb;
c2aa5f81
ST
334 SyncClocks sc;
335
bae2c270
PM
336 /* This must be volatile so it is not trashed by longjmp() */
337 volatile bool have_tb_lock = false;
8c6939c0 338
259186a7 339 if (cpu->halted) {
3993c6bd 340 if (!cpu_has_work(cpu)) {
eda48c34
PB
341 return EXCP_HALTED;
342 }
343
259186a7 344 cpu->halted = 0;
eda48c34 345 }
5a1e3cfc 346
4917cf44 347 current_cpu = cpu;
e4533c7a 348
4917cf44 349 /* As long as current_cpu is null, up to the assignment just above,
ec9bd89f
OH
350 * requests by other threads to exit the execution loop are expected to
351 * be issued using the exit_request global. We must make sure that our
4917cf44 352 * evaluation of the global value is performed past the current_cpu
ec9bd89f
OH
353 * value transition point, which requires a memory barrier as well as
354 * an instruction scheduling constraint on modern architectures. */
355 smp_mb();
356
c629a4bc 357 if (unlikely(exit_request)) {
fcd7d003 358 cpu->exit_request = 1;
1a28cac3
MT
359 }
360
cffe7b32 361 cc->cpu_exec_enter(cpu);
9d27abd9 362
c2aa5f81
ST
363 /* Calculate difference between guest clock and host clock.
364 * This delay includes the delay of the last cycle, so
365 * what we have to do is sleep until it is 0. As for the
366 * advance/delay we gain here, we try to fix it next time.
367 */
368 init_delay_params(&sc, cpu);
369
7d13299d 370 /* prepare setjmp context for exception handling */
3fb2ded1 371 for(;;) {
6f03bef0 372 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
3fb2ded1 373 /* if an exception is pending, we execute it here */
27103424
AF
374 if (cpu->exception_index >= 0) {
375 if (cpu->exception_index >= EXCP_INTERRUPT) {
3fb2ded1 376 /* exit request from the cpu execution loop */
27103424 377 ret = cpu->exception_index;
1009d2ed
JK
378 if (ret == EXCP_DEBUG) {
379 cpu_handle_debug_exception(env);
380 }
e511b4d7 381 cpu->exception_index = -1;
3fb2ded1 382 break;
72d239ed
AJ
383 } else {
384#if defined(CONFIG_USER_ONLY)
3fb2ded1 385 /* if user mode only, we simulate a fake exception
9f083493 386 which will be handled outside the cpu execution
3fb2ded1 387 loop */
83479e77 388#if defined(TARGET_I386)
97a8ea5a 389 cc->do_interrupt(cpu);
83479e77 390#endif
27103424 391 ret = cpu->exception_index;
e511b4d7 392 cpu->exception_index = -1;
3fb2ded1 393 break;
72d239ed 394#else
97a8ea5a 395 cc->do_interrupt(cpu);
27103424 396 cpu->exception_index = -1;
83479e77 397#endif
3fb2ded1 398 }
5fafdf24 399 }
9df217a3 400
b5fc09ae 401 next_tb = 0; /* force lookup of first TB */
3fb2ded1 402 for(;;) {
259186a7 403 interrupt_request = cpu->interrupt_request;
e1638bd8 404 if (unlikely(interrupt_request)) {
ed2803da 405 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
e1638bd8 406 /* Mask out external interrupts for this step. */
3125f763 407 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 408 }
6658ffb8 409 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
259186a7 410 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
27103424 411 cpu->exception_index = EXCP_DEBUG;
5638d180 412 cpu_loop_exit(cpu);
6658ffb8 413 }
a90b7318 414 if (interrupt_request & CPU_INTERRUPT_HALT) {
259186a7
AF
415 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
416 cpu->halted = 1;
27103424 417 cpu->exception_index = EXCP_HLT;
5638d180 418 cpu_loop_exit(cpu);
a90b7318 419 }
4a92a558
PB
420#if defined(TARGET_I386)
421 if (interrupt_request & CPU_INTERRUPT_INIT) {
422 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);
423 do_cpu_init(x86_cpu);
424 cpu->exception_index = EXCP_HALTED;
425 cpu_loop_exit(cpu);
426 }
427#else
428 if (interrupt_request & CPU_INTERRUPT_RESET) {
429 cpu_reset(cpu);
430 }
68a79315 431#endif
9585db68
RH
432 /* The target hook has 3 exit conditions:
433 False when the interrupt isn't processed,
434 True when it is, and we should restart on a new TB,
435 and via longjmp via cpu_loop_exit. */
436 if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
437 next_tb = 0;
438 }
439 /* Don't use the cached interrupt_request value,
440 do_interrupt may have updated the EXITTB flag. */
259186a7
AF
441 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
442 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bf3e8bf1
FB
443 /* ensure that no TB jump will be modified as
444 the program flow was changed */
b5fc09ae 445 next_tb = 0;
bf3e8bf1 446 }
be214e6c 447 }
fcd7d003
AF
448 if (unlikely(cpu->exit_request)) {
449 cpu->exit_request = 0;
27103424 450 cpu->exception_index = EXCP_INTERRUPT;
5638d180 451 cpu_loop_exit(cpu);
3fb2ded1 452 }
5e5f07e0 453 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
bae2c270 454 have_tb_lock = true;
cea5f9a2 455 tb = tb_find_fast(env);
d5975363
PB
456 /* Note: we do it here to avoid a gcc bug on Mac OS X when
457 doing it in tb_find_slow */
5e5f07e0 458 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
d5975363
PB
459 /* as some TB could have been invalidated because
460 of memory exceptions while generating the code, we
461 must recompute the hash index here */
462 next_tb = 0;
5e5f07e0 463 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
d5975363 464 }
c30d1aea
PM
465 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
466 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
467 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
468 }
8a40a180
FB
469 /* see if we can patch the calling TB. When the TB
470 spans two pages, we cannot safely do a direct
471 jump. */
040f2fb2 472 if (next_tb != 0 && tb->page_addr[1] == -1) {
0980011b
PM
473 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
474 next_tb & TB_EXIT_MASK, tb);
3fb2ded1 475 }
bae2c270 476 have_tb_lock = false;
5e5f07e0 477 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
55e8b85e 478
479 /* cpu_interrupt might be called while translating the
480 TB, but before it is linked into a potentially
481 infinite loop and becomes env->current_tb. Avoid
482 starting execution if there is a pending interrupt. */
d77953b9 483 cpu->current_tb = tb;
b0052d15 484 barrier();
fcd7d003 485 if (likely(!cpu->exit_request)) {
6db8b538 486 trace_exec_tb(tb, tb->pc);
2e70f6ef 487 tc_ptr = tb->tc_ptr;
e965fc38 488 /* execute the generated code */
77211379 489 next_tb = cpu_tb_exec(cpu, tc_ptr);
378df4b2
PM
490 switch (next_tb & TB_EXIT_MASK) {
491 case TB_EXIT_REQUESTED:
492 /* Something asked us to stop executing
493 * chained TBs; just continue round the main
494 * loop. Whatever requested the exit will also
495 * have set something else (eg exit_request or
496 * interrupt_request) which we will handle
497 * next time around the loop.
498 */
499 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
500 next_tb = 0;
501 break;
502 case TB_EXIT_ICOUNT_EXPIRED:
503 {
bf20dc07 504 /* Instruction counter expired. */
2e70f6ef 505 int insns_left;
0980011b 506 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
28ecfd7a 507 insns_left = cpu->icount_decr.u32;
efee7340 508 if (cpu->icount_extra && insns_left >= 0) {
2e70f6ef 509 /* Refill decrementer and continue execution. */
efee7340
AF
510 cpu->icount_extra += insns_left;
511 if (cpu->icount_extra > 0xffff) {
2e70f6ef
PB
512 insns_left = 0xffff;
513 } else {
efee7340 514 insns_left = cpu->icount_extra;
2e70f6ef 515 }
efee7340 516 cpu->icount_extra -= insns_left;
28ecfd7a 517 cpu->icount_decr.u16.low = insns_left;
2e70f6ef
PB
518 } else {
519 if (insns_left > 0) {
520 /* Execute remaining instructions. */
cea5f9a2 521 cpu_exec_nocache(env, insns_left, tb);
c2aa5f81 522 align_clocks(&sc, cpu);
2e70f6ef 523 }
27103424 524 cpu->exception_index = EXCP_INTERRUPT;
2e70f6ef 525 next_tb = 0;
5638d180 526 cpu_loop_exit(cpu);
2e70f6ef 527 }
378df4b2
PM
528 break;
529 }
530 default:
531 break;
2e70f6ef
PB
532 }
533 }
d77953b9 534 cpu->current_tb = NULL;
c2aa5f81
ST
535 /* Try to align the host and virtual clocks
536 if the guest is in advance */
537 align_clocks(&sc, cpu);
4cbf74b6
FB
538 /* reset soft MMU for next block (it can currently
539 only be set by a memory fault) */
50a518e3 540 } /* for(;;) */
0d101938
JK
541 } else {
542 /* Reload env after longjmp - the compiler may have smashed all
543 * local variables as longjmp is marked 'noreturn'. */
4917cf44
AF
544 cpu = current_cpu;
545 env = cpu->env_ptr;
6c78f29a 546 cc = CPU_GET_CLASS(cpu);
626cf8f4 547 cpu->can_do_io = 1;
693fa551
AF
548#ifdef TARGET_I386
549 x86_cpu = X86_CPU(cpu);
6c78f29a 550#endif
bae2c270
PM
551 if (have_tb_lock) {
552 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
553 have_tb_lock = false;
554 }
7d13299d 555 }
3fb2ded1
FB
556 } /* for(;;) */
557
cffe7b32 558 cc->cpu_exec_exit(cpu);
1057eaa7 559
4917cf44
AF
560 /* fail safe : never use current_cpu outside cpu_exec() */
561 current_cpu = NULL;
7d13299d
FB
562 return ret;
563}