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unicore32: necessary modifications for other files to support unicore32
[thirdparty/qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
1d93f0f0 24#include "qemu-barrier.h"
7d13299d 25
fbf9eeb3
FB		 26#if !defined(CONFIG_SOFTMMU)
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
84778508 37#ifdef __linux__
fbf9eeb3
FB		 38#include <sys/ucontext.h>
39#endif
84778508 40#endif
fbf9eeb3 41
dfe5fff3 42#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 43// Work around ugly bugs in glibc that mangle global register contents
44#undef env
45#define env cpu_single_env
46#endif
47
36bdbe54
FB		 48int tb_invalidated_flag;
49
f0667e66 50//#define CONFIG_DEBUG_EXEC
9de5e440 51//#define DEBUG_SIGNAL
7d13299d 52
6a4955a8
AL		 53int qemu_cpu_has_work(CPUState *env)
54{
55 return cpu_has_work(env);
56}
57
e4533c7a
FB		 58void cpu_loop_exit(void)
59{
1c3569fe 60 env->current_tb = NULL;
e4533c7a
FB		 61 longjmp(env->jmp_env, 1);
62}
bfed01fc 63
fbf9eeb3
FB		 64/* exit the current TB from a signal handler. The host registers are
65 restored in a state compatible with the CPU emulator
66 */
5fafdf24 67void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 68{
69#if !defined(CONFIG_SOFTMMU)
84778508 70#ifdef __linux__
fbf9eeb3 71 struct ucontext *uc = puc;
84778508
BS		 72#elif defined(__OpenBSD__)
73 struct sigcontext *uc = puc;
74#endif
fbf9eeb3
FB		 75#endif
76
77 env = env1;
78
79 /* XXX: restore cpu registers saved in host registers */
80
81#if !defined(CONFIG_SOFTMMU)
82 if (puc) {
83 /* XXX: use siglongjmp ? */
84778508 84#ifdef __linux__
60e99246
AJ		 85#ifdef __ia64
86 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
87#else
fbf9eeb3 88 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
60e99246 89#endif
84778508
BS		 90#elif defined(__OpenBSD__)
91 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
92#endif
fbf9eeb3
FB		 93 }
94#endif
9a3ea654 95 env->exception_index = -1;
fbf9eeb3
FB		 96 longjmp(env->jmp_env, 1);
97}
98
2e70f6ef
PB		 99/* Execute the code without caching the generated code. An interpreter
100 could be used if available. */
101static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
102{
103 unsigned long next_tb;
104 TranslationBlock *tb;
105
106 /* Should never happen.
107 We only end up here when an existing TB is too long. */
108 if (max_cycles > CF_COUNT_MASK)
109 max_cycles = CF_COUNT_MASK;
110
111 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
112 max_cycles);
113 env->current_tb = tb;
114 /* execute the generated code */
115 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
1c3569fe 116 env->current_tb = NULL;
2e70f6ef
PB		 117
118 if ((next_tb & 3) == 2) {
119 /* Restore PC. This may happen if async event occurs before
120 the TB starts executing. */
622ed360 121 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 122 }
123 tb_phys_invalidate(tb, -1);
124 tb_free(tb);
125}
126
8a40a180
FB		 127static TranslationBlock *tb_find_slow(target_ulong pc,
128 target_ulong cs_base,
c068688b 129 uint64_t flags)
8a40a180
FB		 130{
131 TranslationBlock *tb, **ptb1;
8a40a180 132 unsigned int h;
41c1b1c9
PB		 133 tb_page_addr_t phys_pc, phys_page1, phys_page2;
134 target_ulong virt_page2;
3b46e624 135
8a40a180 136 tb_invalidated_flag = 0;
3b46e624 137
8a40a180 138 /* find translated block using physical mappings */
41c1b1c9 139 phys_pc = get_page_addr_code(env, pc);
8a40a180
FB		 140 phys_page1 = phys_pc & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 h = tb_phys_hash_func(phys_pc);
143 ptb1 = &tb_phys_hash[h];
144 for(;;) {
145 tb = *ptb1;
146 if (!tb)
147 goto not_found;
5fafdf24 148 if (tb->pc == pc &&
8a40a180 149 tb->page_addr[0] == phys_page1 &&
5fafdf24 150 tb->cs_base == cs_base &&
8a40a180
FB		 151 tb->flags == flags) {
152 /* check next page if needed */
153 if (tb->page_addr[1] != -1) {
5fafdf24 154 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 155 TARGET_PAGE_SIZE;
41c1b1c9 156 phys_page2 = get_page_addr_code(env, virt_page2);
8a40a180
FB		 157 if (tb->page_addr[1] == phys_page2)
158 goto found;
159 } else {
160 goto found;
161 }
162 }
163 ptb1 = &tb->phys_hash_next;
164 }
165 not_found:
2e70f6ef
PB		 166 /* if no translated code available, then translate it now */
167 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 168
8a40a180 169 found:
2c90fe2b
KB		 170 /* Move the last found TB to the head of the list */
171 if (likely(*ptb1)) {
172 *ptb1 = tb->phys_hash_next;
173 tb->phys_hash_next = tb_phys_hash[h];
174 tb_phys_hash[h] = tb;
175 }
8a40a180
FB		 176 /* we add the TB in the virtual pc hash table */
177 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 178 return tb;
179}
180
181static inline TranslationBlock *tb_find_fast(void)
182{
183 TranslationBlock *tb;
184 target_ulong cs_base, pc;
6b917547 185 int flags;
8a40a180
FB		 186
187 /* we record a subset of the CPU state. It will
188 always be the same before a given translated block
189 is executed. */
6b917547 190 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 191 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 192 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
193 tb->flags != flags)) {
8a40a180
FB		 194 tb = tb_find_slow(pc, cs_base, flags);
195 }
196 return tb;
197}
198
1009d2ed
JK		 199static CPUDebugExcpHandler *debug_excp_handler;
200
201CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
202{
203 CPUDebugExcpHandler *old_handler = debug_excp_handler;
204
205 debug_excp_handler = handler;
206 return old_handler;
207}
208
209static void cpu_handle_debug_exception(CPUState *env)
210{
211 CPUWatchpoint *wp;
212
213 if (!env->watchpoint_hit) {
214 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
215 wp->flags &= ~BP_WATCHPOINT_HIT;
216 }
217 }
218 if (debug_excp_handler) {
219 debug_excp_handler(env);
220 }
221}
222
7d13299d
FB		 223/* main execution loop */
224
1a28cac3
MT		 225volatile sig_atomic_t exit_request;
226
e4533c7a 227int cpu_exec(CPUState *env1)
7d13299d 228{
1d9000e8 229 volatile host_reg_t saved_env_reg;
8a40a180 230 int ret, interrupt_request;
8a40a180 231 TranslationBlock *tb;
c27004ec 232 uint8_t *tc_ptr;
d5975363 233 unsigned long next_tb;
8c6939c0 234
eda48c34
PB		 235 if (env1->halted) {
236 if (!cpu_has_work(env1)) {
237 return EXCP_HALTED;
238 }
239
240 env1->halted = 0;
241 }
5a1e3cfc 242
5fafdf24 243 cpu_single_env = env1;
6a00d601 244
24ebf5f3
PB		 245 /* the access to env below is actually saving the global register's
246 value, so that files not including target-xyz/exec.h are free to
247 use it. */
248 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
249 saved_env_reg = (host_reg_t) env;
1d93f0f0 250 barrier();
c27004ec 251 env = env1;
e4533c7a 252
c629a4bc 253 if (unlikely(exit_request)) {
1a28cac3 254 env->exit_request = 1;
1a28cac3
MT		 255 }
256
ecb644f4 257#if defined(TARGET_I386)
6792a57b
JK		 258 /* put eflags in CPU temporary format */
259 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
260 DF = 1 - (2 * ((env->eflags >> 10) & 1));
261 CC_OP = CC_OP_EFLAGS;
262 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 263#elif defined(TARGET_SPARC)
e6e5906b
PB		 264#elif defined(TARGET_M68K)
265 env->cc_op = CC_OP_FLAGS;
266 env->cc_dest = env->sr & 0xf;
267 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 268#elif defined(TARGET_ALPHA)
269#elif defined(TARGET_ARM)
d2fbca94 270#elif defined(TARGET_UNICORE32)
ecb644f4 271#elif defined(TARGET_PPC)
81ea0e13 272#elif defined(TARGET_LM32)
b779e29e 273#elif defined(TARGET_MICROBLAZE)
6af0bf9c 274#elif defined(TARGET_MIPS)
fdf9b3e8 275#elif defined(TARGET_SH4)
f1ccf904 276#elif defined(TARGET_CRIS)
10ec5117 277#elif defined(TARGET_S390X)
fdf9b3e8 278 /* XXXXX */
e4533c7a
FB		 279#else
280#error unsupported target CPU
281#endif
3fb2ded1 282 env->exception_index = -1;
9d27abd9 283
7d13299d 284 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 285 for(;;) {
286 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 287#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2 288#undef env
6792a57b 289 env = cpu_single_env;
9ddff3d2
BS		 290#define env cpu_single_env
291#endif
3fb2ded1
FB		 292 /* if an exception is pending, we execute it here */
293 if (env->exception_index >= 0) {
294 if (env->exception_index >= EXCP_INTERRUPT) {
295 /* exit request from the cpu execution loop */
296 ret = env->exception_index;
1009d2ed
JK		 297 if (ret == EXCP_DEBUG) {
298 cpu_handle_debug_exception(env);
299 }
3fb2ded1 300 break;
72d239ed
AJ		 301 } else {
302#if defined(CONFIG_USER_ONLY)
3fb2ded1 303 /* if user mode only, we simulate a fake exception
9f083493 304 which will be handled outside the cpu execution
3fb2ded1 305 loop */
83479e77 306#if defined(TARGET_I386)
5fafdf24
TS		 307 do_interrupt_user(env->exception_index,
308 env->exception_is_int,
309 env->error_code,
3fb2ded1 310 env->exception_next_eip);
eba01623
FB		 311 /* successfully delivered */
312 env->old_exception = -1;
83479e77 313#endif
3fb2ded1
FB		 314 ret = env->exception_index;
315 break;
72d239ed 316#else
83479e77 317#if defined(TARGET_I386)
3fb2ded1
FB		 318 /* simulate a real cpu exception. On i386, it can
319 trigger new exceptions, but we do not handle
320 double or triple faults yet. */
5fafdf24
TS		 321 do_interrupt(env->exception_index,
322 env->exception_is_int,
323 env->error_code,
d05e66d2 324 env->exception_next_eip, 0);
678dde13
TS		 325 /* successfully delivered */
326 env->old_exception = -1;
ce09776b
FB		 327#elif defined(TARGET_PPC)
328 do_interrupt(env);
81ea0e13
MW		 329#elif defined(TARGET_LM32)
330 do_interrupt(env);
b779e29e
EI		 331#elif defined(TARGET_MICROBLAZE)
332 do_interrupt(env);
6af0bf9c
FB		 333#elif defined(TARGET_MIPS)
334 do_interrupt(env);
e95c8d51 335#elif defined(TARGET_SPARC)
f2bc7e7f 336 do_interrupt(env);
b5ff1b31
FB		 337#elif defined(TARGET_ARM)
338 do_interrupt(env);
d2fbca94
GX		 339#elif defined(TARGET_UNICORE32)
340 do_interrupt(env);
fdf9b3e8
FB		 341#elif defined(TARGET_SH4)
342 do_interrupt(env);
eddf68a6
JM		 343#elif defined(TARGET_ALPHA)
344 do_interrupt(env);
f1ccf904
TS		 345#elif defined(TARGET_CRIS)
346 do_interrupt(env);
0633879f
PB		 347#elif defined(TARGET_M68K)
348 do_interrupt(0);
72d239ed 349#endif
301d2908 350 env->exception_index = -1;
83479e77 351#endif
3fb2ded1 352 }
5fafdf24 353 }
9df217a3 354
b5fc09ae 355 next_tb = 0; /* force lookup of first TB */
3fb2ded1 356 for(;;) {
68a79315 357 interrupt_request = env->interrupt_request;
e1638bd8 358 if (unlikely(interrupt_request)) {
359 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
360 /* Mask out external interrupts for this step. */
361 interrupt_request &= ~(CPU_INTERRUPT_HARD |
362 CPU_INTERRUPT_FIQ |
363 CPU_INTERRUPT_SMI |
364 CPU_INTERRUPT_NMI);
365 }
6658ffb8
PB		 366 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
367 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
368 env->exception_index = EXCP_DEBUG;
369 cpu_loop_exit();
370 }
a90b7318 371#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e 372 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
d2fbca94 373 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
a90b7318
AZ		 374 if (interrupt_request & CPU_INTERRUPT_HALT) {
375 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
376 env->halted = 1;
377 env->exception_index = EXCP_HLT;
378 cpu_loop_exit();
379 }
380#endif
68a79315 381#if defined(TARGET_I386)
b09ea7d5
GN		 382 if (interrupt_request & CPU_INTERRUPT_INIT) {
383 svm_check_intercept(SVM_EXIT_INIT);
384 do_cpu_init(env);
385 env->exception_index = EXCP_HALTED;
386 cpu_loop_exit();
387 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
388 do_cpu_sipi(env);
389 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 390 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
391 !(env->hflags & HF_SMM_MASK)) {
392 svm_check_intercept(SVM_EXIT_SMI);
393 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
394 do_smm_enter();
395 next_tb = 0;
396 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
397 !(env->hflags2 & HF2_NMI_MASK)) {
398 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
399 env->hflags2 |= HF2_NMI_MASK;
400 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
401 next_tb = 0;
79c4f6b0
HY		 402 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
403 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
404 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
405 next_tb = 0;
db620f46
FB		 406 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
407 (((env->hflags2 & HF2_VINTR_MASK) &&
408 (env->hflags2 & HF2_HIF_MASK)) ||
409 (!(env->hflags2 & HF2_VINTR_MASK) &&
410 (env->eflags & IF_MASK &&
411 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
412 int intno;
413 svm_check_intercept(SVM_EXIT_INTR);
414 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
415 intno = cpu_get_pic_interrupt(env);
93fcfe39 416 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 417#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 418#undef env
419 env = cpu_single_env;
420#define env cpu_single_env
421#endif
db620f46
FB		 422 do_interrupt(intno, 0, 0, 0, 1);
423 /* ensure that no TB jump will be modified as
424 the program flow was changed */
425 next_tb = 0;
0573fbfc 426#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 427 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
428 (env->eflags & IF_MASK) &&
429 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
430 int intno;
431 /* FIXME: this should respect TPR */
432 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 433 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 434 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 435 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 436 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 437 next_tb = 0;
907a5b26 438#endif
db620f46 439 }
68a79315 440 }
ce09776b 441#elif defined(TARGET_PPC)
9fddaa0c
FB		 442#if 0
443 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 444 cpu_reset(env);
9fddaa0c
FB		 445 }
446#endif
47103572 447 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 448 ppc_hw_interrupt(env);
449 if (env->pending_interrupts == 0)
450 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 451 next_tb = 0;
ce09776b 452 }
81ea0e13
MW		 453#elif defined(TARGET_LM32)
454 if ((interrupt_request & CPU_INTERRUPT_HARD)
455 && (env->ie & IE_IE)) {
456 env->exception_index = EXCP_IRQ;
457 do_interrupt(env);
458 next_tb = 0;
459 }
b779e29e
EI		 460#elif defined(TARGET_MICROBLAZE)
461 if ((interrupt_request & CPU_INTERRUPT_HARD)
462 && (env->sregs[SR_MSR] & MSR_IE)
463 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
464 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
465 env->exception_index = EXCP_IRQ;
466 do_interrupt(env);
467 next_tb = 0;
468 }
6af0bf9c
FB		 469#elif defined(TARGET_MIPS)
470 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
4cdc1cd1 471 cpu_mips_hw_interrupts_pending(env)) {
6af0bf9c
FB		 472 /* Raise it */
473 env->exception_index = EXCP_EXT_INTERRUPT;
474 env->error_code = 0;
475 do_interrupt(env);
b5fc09ae 476 next_tb = 0;
6af0bf9c 477 }
e95c8d51 478#elif defined(TARGET_SPARC)
d532b26c
IK		 479 if (interrupt_request & CPU_INTERRUPT_HARD) {
480 if (cpu_interrupts_enabled(env) &&
481 env->interrupt_index > 0) {
482 int pil = env->interrupt_index & 0xf;
483 int type = env->interrupt_index & 0xf0;
484
485 if (((type == TT_EXTINT) &&
486 cpu_pil_allowed(env, pil)) ||
487 type != TT_EXTINT) {
488 env->exception_index = env->interrupt_index;
489 do_interrupt(env);
490 next_tb = 0;
491 }
492 }
e95c8d51
FB		 493 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
494 //do_interrupt(0, 0, 0, 0, 0);
495 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 496 }
b5ff1b31
FB		 497#elif defined(TARGET_ARM)
498 if (interrupt_request & CPU_INTERRUPT_FIQ
499 && !(env->uncached_cpsr & CPSR_F)) {
500 env->exception_index = EXCP_FIQ;
501 do_interrupt(env);
b5fc09ae 502 next_tb = 0;
b5ff1b31 503 }
9ee6e8bb
PB		 504 /* ARMv7-M interrupt return works by loading a magic value
505 into the PC. On real hardware the load causes the
506 return to occur. The qemu implementation performs the
507 jump normally, then does the exception return when the
508 CPU tries to execute code at the magic address.
509 This will cause the magic PC value to be pushed to
510 the stack if an interrupt occured at the wrong time.
511 We avoid this by disabling interrupts when
512 pc contains a magic address. */
b5ff1b31 513 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 514 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
515 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 516 env->exception_index = EXCP_IRQ;
517 do_interrupt(env);
b5fc09ae 518 next_tb = 0;
b5ff1b31 519 }
d2fbca94
GX		 520#elif defined(TARGET_UNICORE32)
521 if (interrupt_request & CPU_INTERRUPT_HARD
522 && !(env->uncached_asr & ASR_I)) {
523 do_interrupt(env);
524 next_tb = 0;
525 }
fdf9b3e8 526#elif defined(TARGET_SH4)
e96e2044
TS		 527 if (interrupt_request & CPU_INTERRUPT_HARD) {
528 do_interrupt(env);
b5fc09ae 529 next_tb = 0;
e96e2044 530 }
eddf68a6
JM		 531#elif defined(TARGET_ALPHA)
532 if (interrupt_request & CPU_INTERRUPT_HARD) {
533 do_interrupt(env);
b5fc09ae 534 next_tb = 0;
eddf68a6 535 }
f1ccf904 536#elif defined(TARGET_CRIS)
1b1a38b0 537 if (interrupt_request & CPU_INTERRUPT_HARD
fb9fb692
EI		 538 && (env->pregs[PR_CCS] & I_FLAG)
539 && !env->locked_irq) {
1b1a38b0
EI		 540 env->exception_index = EXCP_IRQ;
541 do_interrupt(env);
542 next_tb = 0;
543 }
544 if (interrupt_request & CPU_INTERRUPT_NMI
545 && (env->pregs[PR_CCS] & M_FLAG)) {
546 env->exception_index = EXCP_NMI;
f1ccf904 547 do_interrupt(env);
b5fc09ae 548 next_tb = 0;
f1ccf904 549 }
0633879f
PB		 550#elif defined(TARGET_M68K)
551 if (interrupt_request & CPU_INTERRUPT_HARD
552 && ((env->sr & SR_I) >> SR_I_SHIFT)
553 < env->pending_level) {
554 /* Real hardware gets the interrupt vector via an
555 IACK cycle at this point. Current emulated
556 hardware doesn't rely on this, so we
557 provide/save the vector when the interrupt is
558 first signalled. */
559 env->exception_index = env->pending_vector;
560 do_interrupt(1);
b5fc09ae 561 next_tb = 0;
0633879f 562 }
68a79315 563#endif
9d05095e
FB		 564 /* Don't use the cached interupt_request value,
565 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 566 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 567 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
568 /* ensure that no TB jump will be modified as
569 the program flow was changed */
b5fc09ae 570 next_tb = 0;
bf3e8bf1 571 }
be214e6c
AJ		 572 }
573 if (unlikely(env->exit_request)) {
574 env->exit_request = 0;
575 env->exception_index = EXCP_INTERRUPT;
576 cpu_loop_exit();
3fb2ded1 577 }
a73b1fd9 578#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
8fec2b8c 579 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 580 /* restore flags in standard format */
ecb644f4 581#if defined(TARGET_I386)
a7812ae4 582 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 583 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 584 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e6e5906b
PB		 585#elif defined(TARGET_M68K)
586 cpu_m68k_flush_flags(env, env->cc_op);
587 env->cc_op = CC_OP_FLAGS;
588 env->sr = (env->sr & 0xffe0)
589 | env->cc_dest | (env->cc_x << 4);
93fcfe39 590 log_cpu_state(env, 0);
e4533c7a 591#else
a73b1fd9 592 log_cpu_state(env, 0);
e4533c7a 593#endif
3fb2ded1 594 }
a73b1fd9 595#endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
d5975363 596 spin_lock(&tb_lock);
8a40a180 597 tb = tb_find_fast();
d5975363
PB		 598 /* Note: we do it here to avoid a gcc bug on Mac OS X when
599 doing it in tb_find_slow */
600 if (tb_invalidated_flag) {
601 /* as some TB could have been invalidated because
602 of memory exceptions while generating the code, we
603 must recompute the hash index here */
604 next_tb = 0;
2e70f6ef 605 tb_invalidated_flag = 0;
d5975363 606 }
f0667e66 607#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 608 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
609 (long)tb->tc_ptr, tb->pc,
610 lookup_symbol(tb->pc));
9d27abd9 611#endif
8a40a180
FB		 612 /* see if we can patch the calling TB. When the TB
613 spans two pages, we cannot safely do a direct
614 jump. */
040f2fb2 615 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 616 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 617 }
d5975363 618 spin_unlock(&tb_lock);
55e8b85e 619
620 /* cpu_interrupt might be called while translating the
621 TB, but before it is linked into a potentially
622 infinite loop and becomes env->current_tb. Avoid
623 starting execution if there is a pending interrupt. */
b0052d15
JK		 624 env->current_tb = tb;
625 barrier();
626 if (likely(!env->exit_request)) {
2e70f6ef 627 tc_ptr = tb->tc_ptr;
3fb2ded1 628 /* execute the generated code */
dfe5fff3 629#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 630#undef env
2e70f6ef 631 env = cpu_single_env;
572a9d4a
BS		 632#define env cpu_single_env
633#endif
2e70f6ef 634 next_tb = tcg_qemu_tb_exec(tc_ptr);
2e70f6ef 635 if ((next_tb & 3) == 2) {
bf20dc07 636 /* Instruction counter expired. */
2e70f6ef
PB		 637 int insns_left;
638 tb = (TranslationBlock *)(long)(next_tb & ~3);
639 /* Restore PC. */
622ed360 640 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 641 insns_left = env->icount_decr.u32;
642 if (env->icount_extra && insns_left >= 0) {
643 /* Refill decrementer and continue execution. */
644 env->icount_extra += insns_left;
645 if (env->icount_extra > 0xffff) {
646 insns_left = 0xffff;
647 } else {
648 insns_left = env->icount_extra;
649 }
650 env->icount_extra -= insns_left;
651 env->icount_decr.u16.low = insns_left;
652 } else {
653 if (insns_left > 0) {
654 /* Execute remaining instructions. */
655 cpu_exec_nocache(insns_left, tb);
656 }
657 env->exception_index = EXCP_INTERRUPT;
658 next_tb = 0;
659 cpu_loop_exit();
660 }
661 }
662 }
b0052d15 663 env->current_tb = NULL;
4cbf74b6
FB		 664 /* reset soft MMU for next block (it can currently
665 only be set by a memory fault) */
50a518e3 666 } /* for(;;) */
7d13299d 667 }
3fb2ded1
FB		 668 } /* for(;;) */
669
7d13299d 670
e4533c7a 671#if defined(TARGET_I386)
9de5e440 672 /* restore flags in standard format */
a7812ae4 673 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 674#elif defined(TARGET_ARM)
b7bcbe95 675 /* XXX: Save/restore host fpu exception state?. */
d2fbca94 676#elif defined(TARGET_UNICORE32)
93ac68bc 677#elif defined(TARGET_SPARC)
67867308 678#elif defined(TARGET_PPC)
81ea0e13 679#elif defined(TARGET_LM32)
e6e5906b
PB		 680#elif defined(TARGET_M68K)
681 cpu_m68k_flush_flags(env, env->cc_op);
682 env->cc_op = CC_OP_FLAGS;
683 env->sr = (env->sr & 0xffe0)
684 | env->cc_dest | (env->cc_x << 4);
b779e29e 685#elif defined(TARGET_MICROBLAZE)
6af0bf9c 686#elif defined(TARGET_MIPS)
fdf9b3e8 687#elif defined(TARGET_SH4)
eddf68a6 688#elif defined(TARGET_ALPHA)
f1ccf904 689#elif defined(TARGET_CRIS)
10ec5117 690#elif defined(TARGET_S390X)
fdf9b3e8 691 /* XXXXX */
e4533c7a
FB		 692#else
693#error unsupported target CPU
694#endif
1057eaa7
PB		 695
696 /* restore global registers */
1d93f0f0 697 barrier();
24ebf5f3 698 env = (void *) saved_env_reg;
1057eaa7 699
6a00d601 700 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 701 cpu_single_env = NULL;
7d13299d
FB		 702 return ret;
703}
6dbad63e 704
fbf9eeb3
FB		 705/* must only be called from the generated code as an exception can be
706 generated */
707void tb_invalidate_page_range(target_ulong start, target_ulong end)
708{
dc5d0b3d
FB		 709 /* XXX: cannot enable it yet because it yields to MMU exception
710 where NIP != read address on PowerPC */
711#if 0
fbf9eeb3
FB		 712 target_ulong phys_addr;
713 phys_addr = get_phys_addr_code(env, start);
714 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 715#endif
fbf9eeb3
FB		 716}
717
1a18c71b 718#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 719
6dbad63e
FB		 720void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
721{
722 CPUX86State *saved_env;
723
724 saved_env = env;
725 env = s;
a412ac57 726 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 727 selector &= 0xffff;
5fafdf24 728 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 729 (selector << 4), 0xffff, 0);
a513fe19 730 } else {
5d97559d 731 helper_load_seg(seg_reg, selector);
a513fe19 732 }
6dbad63e
FB		 733 env = saved_env;
734}
9de5e440 735
6f12a2a6 736void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 737{
738 CPUX86State *saved_env;
739
740 saved_env = env;
741 env = s;
3b46e624 742
6f12a2a6 743 helper_fsave(ptr, data32);
d0a1ffc9
FB		 744
745 env = saved_env;
746}
747
6f12a2a6 748void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 749{
750 CPUX86State *saved_env;
751
752 saved_env = env;
753 env = s;
3b46e624 754
6f12a2a6 755 helper_frstor(ptr, data32);
d0a1ffc9
FB		 756
757 env = saved_env;
758}
759
e4533c7a
FB		 760#endif /* TARGET_I386 */
761
67b915a5
FB		 762#if !defined(CONFIG_SOFTMMU)
763
3fb2ded1 764#if defined(TARGET_I386)
0b5c1ce8
NF		 765#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
766#else
767#define EXCEPTION_ACTION cpu_loop_exit()
768#endif
3fb2ded1 769
b56dad1c 770/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 771 the effective address of the memory exception. 'is_write' is 1 if a
772 write caused the exception and otherwise 0'. 'old_set' is the
773 signal set which should be restored */
2b413144 774static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 775 int is_write, sigset_t *old_set,
bf3e8bf1 776 void *puc)
9de5e440 777{
a513fe19
FB		 778 TranslationBlock *tb;
779 int ret;
68a79315 780
83479e77
FB		 781 if (cpu_single_env)
782 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 783#if defined(DEBUG_SIGNAL)
5fafdf24 784 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 785 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 786#endif
25eb4484 787 /* XXX: locking issue */
53a5960a 788 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 789 return 1;
790 }
fbf9eeb3 791
3fb2ded1 792 /* see if it is an MMU fault */
0b5c1ce8 793 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 794 if (ret < 0)
795 return 0; /* not an MMU fault */
796 if (ret == 0)
797 return 1; /* the MMU fault was handled without causing real CPU fault */
798 /* now we have a real cpu fault */
799 tb = tb_find_pc(pc);
800 if (tb) {
801 /* the PC is inside the translated code. It means that we have
802 a virtual CPU fault */
803 cpu_restore_state(tb, env, pc, puc);
804 }
68016c62 805
68016c62
FB		 806 /* we restore the process signal mask as the sigreturn should
807 do it (XXX: use sigsetjmp) */
808 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 809 EXCEPTION_ACTION;
e6e5906b 810
e6e5906b 811 /* never comes here */
67867308
FB		 812 return 1;
813}
6af0bf9c 814
2b413144
FB		 815#if defined(__i386__)
816
d8ecc0b9
FB		 817#if defined(__APPLE__)
818# include <sys/ucontext.h>
819
820# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
821# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
822# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 823# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 824#elif defined (__NetBSD__)
825# include <ucontext.h>
826
827# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
828# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
829# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
830# define MASK_sig(context) ((context)->uc_sigmask)
831#elif defined (__FreeBSD__) || defined(__DragonFly__)
832# include <ucontext.h>
833
834# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
835# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
836# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
837# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 838#elif defined(__OpenBSD__)
839# define EIP_sig(context) ((context)->sc_eip)
840# define TRAP_sig(context) ((context)->sc_trapno)
841# define ERROR_sig(context) ((context)->sc_err)
842# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 843#else
844# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
845# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
846# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 847# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 848#endif
849
5fafdf24 850int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 851 void *puc)
9de5e440 852{
5a7b542b 853 siginfo_t *info = pinfo;
78cfb07f
JL		 854#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
855 ucontext_t *uc = puc;
856#elif defined(__OpenBSD__)
d39bb24a
BS		 857 struct sigcontext *uc = puc;
858#else
9de5e440 859 struct ucontext *uc = puc;
d39bb24a 860#endif
9de5e440 861 unsigned long pc;
bf3e8bf1 862 int trapno;
97eb5b14 863
d691f669
FB		 864#ifndef REG_EIP
865/* for glibc 2.1 */
fd6ce8f6
FB		 866#define REG_EIP EIP
867#define REG_ERR ERR
868#define REG_TRAPNO TRAPNO
d691f669 869#endif
d8ecc0b9
FB		 870 pc = EIP_sig(uc);
871 trapno = TRAP_sig(uc);
ec6338ba
FB		 872 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
873 trapno == 0xe ?
874 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 875 &MASK_sig(uc), puc);
2b413144
FB		 876}
877
bc51c5c9
FB		 878#elif defined(__x86_64__)
879
b3efe5c8 880#ifdef __NetBSD__
d397abbd
BS		 881#define PC_sig(context) _UC_MACHINE_PC(context)
882#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
883#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
884#define MASK_sig(context) ((context)->uc_sigmask)
885#elif defined(__OpenBSD__)
886#define PC_sig(context) ((context)->sc_rip)
887#define TRAP_sig(context) ((context)->sc_trapno)
888#define ERROR_sig(context) ((context)->sc_err)
889#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 890#elif defined (__FreeBSD__) || defined(__DragonFly__)
891#include <ucontext.h>
892
893#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
894#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
895#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
896#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 897#else
d397abbd
BS		 898#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
899#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
900#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
901#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 902#endif
903
5a7b542b 904int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 905 void *puc)
906{
5a7b542b 907 siginfo_t *info = pinfo;
bc51c5c9 908 unsigned long pc;
78cfb07f 909#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 910 ucontext_t *uc = puc;
d397abbd
BS		 911#elif defined(__OpenBSD__)
912 struct sigcontext *uc = puc;
b3efe5c8
BS		 913#else
914 struct ucontext *uc = puc;
915#endif
bc51c5c9 916
d397abbd 917 pc = PC_sig(uc);
5fafdf24 918 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 919 TRAP_sig(uc) == 0xe ?
920 (ERROR_sig(uc) >> 1) & 1 : 0,
921 &MASK_sig(uc), puc);
bc51c5c9
FB		 922}
923
e58ffeb3 924#elif defined(_ARCH_PPC)
2b413144 925
83fb7adf
FB		 926/***********************************************************************
927 * signal context platform-specific definitions
928 * From Wine
929 */
930#ifdef linux
931/* All Registers access - only for local access */
932# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
933/* Gpr Registers access */
934# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
935# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
936# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
937# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
938# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
939# define LR_sig(context) REG_sig(link, context) /* Link register */
940# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
941/* Float Registers access */
942# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
943# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
944/* Exception Registers access */
945# define DAR_sig(context) REG_sig(dar, context)
946# define DSISR_sig(context) REG_sig(dsisr, context)
947# define TRAP_sig(context) REG_sig(trap, context)
948#endif /* linux */
949
58d9b1e0
JL		 950#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
951#include <ucontext.h>
952# define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
953# define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
954# define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
955# define XER_sig(context) ((context)->uc_mcontext.mc_xer)
956# define LR_sig(context) ((context)->uc_mcontext.mc_lr)
957# define CR_sig(context) ((context)->uc_mcontext.mc_cr)
958/* Exception Registers access */
959# define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
960# define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
961# define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
962#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
963
83fb7adf
FB		 964#ifdef __APPLE__
965# include <sys/ucontext.h>
966typedef struct ucontext SIGCONTEXT;
967/* All Registers access - only for local access */
968# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
969# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
970# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
971# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
972/* Gpr Registers access */
973# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
974# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
975# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
976# define CTR_sig(context) REG_sig(ctr, context)
977# define XER_sig(context) REG_sig(xer, context) /* Link register */
978# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
979# define CR_sig(context) REG_sig(cr, context) /* Condition register */
980/* Float Registers access */
981# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
982# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
983/* Exception Registers access */
984# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
985# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
986# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
987#endif /* __APPLE__ */
988
5fafdf24 989int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 990 void *puc)
2b413144 991{
5a7b542b 992 siginfo_t *info = pinfo;
58d9b1e0
JL		 993#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
994 ucontext_t *uc = puc;
995#else
25eb4484 996 struct ucontext *uc = puc;
58d9b1e0 997#endif
25eb4484 998 unsigned long pc;
25eb4484
FB		 999 int is_write;
1000
83fb7adf 1001 pc = IAR_sig(uc);
25eb4484
FB		 1002 is_write = 0;
1003#if 0
1004 /* ppc 4xx case */
83fb7adf 1005 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 1006 is_write = 1;
1007#else
83fb7adf 1008 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 1009 is_write = 1;
1010#endif
5fafdf24 1011 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1012 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 1013}
1014
2f87c607
FB		 1015#elif defined(__alpha__)
1016
5fafdf24 1017int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 1018 void *puc)
1019{
5a7b542b 1020 siginfo_t *info = pinfo;
2f87c607
FB		 1021 struct ucontext *uc = puc;
1022 uint32_t *pc = uc->uc_mcontext.sc_pc;
1023 uint32_t insn = *pc;
1024 int is_write = 0;
1025
8c6939c0 1026 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 1027 switch (insn >> 26) {
1028 case 0x0d: // stw
1029 case 0x0e: // stb
1030 case 0x0f: // stq_u
1031 case 0x24: // stf
1032 case 0x25: // stg
1033 case 0x26: // sts
1034 case 0x27: // stt
1035 case 0x2c: // stl
1036 case 0x2d: // stq
1037 case 0x2e: // stl_c
1038 case 0x2f: // stq_c
1039 is_write = 1;
1040 }
1041
5fafdf24 1042 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1043 is_write, &uc->uc_sigmask, puc);
2f87c607 1044}
8c6939c0
FB		 1045#elif defined(__sparc__)
1046
5fafdf24 1047int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1048 void *puc)
8c6939c0 1049{
5a7b542b 1050 siginfo_t *info = pinfo;
8c6939c0
FB		 1051 int is_write;
1052 uint32_t insn;
dfe5fff3 1053#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1054 uint32_t *regs = (uint32_t *)(info + 1);
1055 void *sigmask = (regs + 20);
8c6939c0 1056 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1057 unsigned long pc = regs[1];
1058#else
84778508 1059#ifdef __linux__
c9e1e2b0
BS		 1060 struct sigcontext *sc = puc;
1061 unsigned long pc = sc->sigc_regs.tpc;
1062 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1063#elif defined(__OpenBSD__)
1064 struct sigcontext *uc = puc;
1065 unsigned long pc = uc->sc_pc;
1066 void *sigmask = (void *)(long)uc->sc_mask;
1067#endif
c9e1e2b0
BS		 1068#endif
1069
8c6939c0
FB		 1070 /* XXX: need kernel patch to get write flag faster */
1071 is_write = 0;
1072 insn = *(uint32_t *)pc;
1073 if ((insn >> 30) == 3) {
1074 switch((insn >> 19) & 0x3f) {
1075 case 0x05: // stb
d877fa5a 1076 case 0x15: // stba
8c6939c0 1077 case 0x06: // sth
d877fa5a 1078 case 0x16: // stha
8c6939c0 1079 case 0x04: // st
d877fa5a 1080 case 0x14: // sta
8c6939c0 1081 case 0x07: // std
d877fa5a
BS		 1082 case 0x17: // stda
1083 case 0x0e: // stx
1084 case 0x1e: // stxa
8c6939c0 1085 case 0x24: // stf
d877fa5a 1086 case 0x34: // stfa
8c6939c0 1087 case 0x27: // stdf
d877fa5a
BS		 1088 case 0x37: // stdfa
1089 case 0x26: // stqf
1090 case 0x36: // stqfa
8c6939c0 1091 case 0x25: // stfsr
d877fa5a
BS		 1092 case 0x3c: // casa
1093 case 0x3e: // casxa
8c6939c0
FB		 1094 is_write = 1;
1095 break;
1096 }
1097 }
5fafdf24 1098 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1099 is_write, sigmask, NULL);
8c6939c0
FB		 1100}
1101
1102#elif defined(__arm__)
1103
5fafdf24 1104int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1105 void *puc)
8c6939c0 1106{
5a7b542b 1107 siginfo_t *info = pinfo;
8c6939c0
FB		 1108 struct ucontext *uc = puc;
1109 unsigned long pc;
1110 int is_write;
3b46e624 1111
48bbf11b 1112#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1113 pc = uc->uc_mcontext.gregs[R15];
1114#else
4eee57f5 1115 pc = uc->uc_mcontext.arm_pc;
5c49b363 1116#endif
8c6939c0
FB		 1117 /* XXX: compute is_write */
1118 is_write = 0;
5fafdf24 1119 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1120 is_write,
f3a9676a 1121 &uc->uc_sigmask, puc);
8c6939c0
FB		 1122}
1123
38e584a0
FB		 1124#elif defined(__mc68000)
1125
5fafdf24 1126int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1127 void *puc)
1128{
5a7b542b 1129 siginfo_t *info = pinfo;
38e584a0
FB		 1130 struct ucontext *uc = puc;
1131 unsigned long pc;
1132 int is_write;
3b46e624 1133
38e584a0
FB		 1134 pc = uc->uc_mcontext.gregs[16];
1135 /* XXX: compute is_write */
1136 is_write = 0;
5fafdf24 1137 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1138 is_write,
bf3e8bf1 1139 &uc->uc_sigmask, puc);
38e584a0
FB		 1140}
1141
b8076a74
FB		 1142#elif defined(__ia64)
1143
1144#ifndef __ISR_VALID
1145 /* This ought to be in <bits/siginfo.h>... */
1146# define __ISR_VALID 1
b8076a74
FB		 1147#endif
1148
5a7b542b 1149int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1150{
5a7b542b 1151 siginfo_t *info = pinfo;
b8076a74
FB		 1152 struct ucontext *uc = puc;
1153 unsigned long ip;
1154 int is_write = 0;
1155
1156 ip = uc->uc_mcontext.sc_ip;
1157 switch (host_signum) {
1158 case SIGILL:
1159 case SIGFPE:
1160 case SIGSEGV:
1161 case SIGBUS:
1162 case SIGTRAP:
fd4a43e4 1163 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1164 /* ISR.W (write-access) is bit 33: */
1165 is_write = (info->si_isr >> 33) & 1;
1166 break;
1167
1168 default:
1169 break;
1170 }
1171 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1172 is_write,
60e99246 1173 (sigset_t *)&uc->uc_sigmask, puc);
b8076a74
FB		 1174}
1175
90cb9493
FB		 1176#elif defined(__s390__)
1177
5fafdf24 1178int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1179 void *puc)
1180{
5a7b542b 1181 siginfo_t *info = pinfo;
90cb9493
FB		 1182 struct ucontext *uc = puc;
1183 unsigned long pc;
6a1621b9
RH		 1184 uint16_t *pinsn;
1185 int is_write = 0;
3b46e624 1186
90cb9493 1187 pc = uc->uc_mcontext.psw.addr;
6a1621b9
RH		 1188
1189 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1190 of the normal 2 arguments. The 3rd argument contains the "int_code"
1191 from the hardware which does in fact contain the is_write value.
1192 The rt signal handler, as far as I can tell, does not give this value
1193 at all. Not that we could get to it from here even if it were. */
1194 /* ??? This is not even close to complete, since it ignores all
1195 of the read-modify-write instructions. */
1196 pinsn = (uint16_t *)pc;
1197 switch (pinsn[0] >> 8) {
1198 case 0x50: /* ST */
1199 case 0x42: /* STC */
1200 case 0x40: /* STH */
1201 is_write = 1;
1202 break;
1203 case 0xc4: /* RIL format insns */
1204 switch (pinsn[0] & 0xf) {
1205 case 0xf: /* STRL */
1206 case 0xb: /* STGRL */
1207 case 0x7: /* STHRL */
1208 is_write = 1;
1209 }
1210 break;
1211 case 0xe3: /* RXY format insns */
1212 switch (pinsn[2] & 0xff) {
1213 case 0x50: /* STY */
1214 case 0x24: /* STG */
1215 case 0x72: /* STCY */
1216 case 0x70: /* STHY */
1217 case 0x8e: /* STPQ */
1218 case 0x3f: /* STRVH */
1219 case 0x3e: /* STRV */
1220 case 0x2f: /* STRVG */
1221 is_write = 1;
1222 }
1223 break;
1224 }
5fafdf24 1225 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1226 is_write, &uc->uc_sigmask, puc);
1227}
1228
1229#elif defined(__mips__)
1230
5fafdf24 1231int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1232 void *puc)
1233{
9617efe8 1234 siginfo_t *info = pinfo;
c4b89d18
TS		 1235 struct ucontext *uc = puc;
1236 greg_t pc = uc->uc_mcontext.pc;
1237 int is_write;
3b46e624 1238
c4b89d18
TS		 1239 /* XXX: compute is_write */
1240 is_write = 0;
5fafdf24 1241 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1242 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1243}
1244
f54b3f92
AJ		 1245#elif defined(__hppa__)
1246
1247int cpu_signal_handler(int host_signum, void *pinfo,
1248 void *puc)
1249{
1250 struct siginfo *info = pinfo;
1251 struct ucontext *uc = puc;
f57040be
RH		 1252 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
1253 uint32_t insn = *(uint32_t *)pc;
1254 int is_write = 0;
1255
1256 /* XXX: need kernel patch to get write flag faster. */
1257 switch (insn >> 26) {
1258 case 0x1a: /* STW */
1259 case 0x19: /* STH */
1260 case 0x18: /* STB */
1261 case 0x1b: /* STWM */
1262 is_write = 1;
1263 break;
1264
1265 case 0x09: /* CSTWX, FSTWX, FSTWS */
1266 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1267 /* Distinguish from coprocessor load ... */
1268 is_write = (insn >> 9) & 1;
1269 break;
1270
1271 case 0x03:
1272 switch ((insn >> 6) & 15) {
1273 case 0xa: /* STWS */
1274 case 0x9: /* STHS */
1275 case 0x8: /* STBS */
1276 case 0xe: /* STWAS */
1277 case 0xc: /* STBYS */
1278 is_write = 1;
1279 }
1280 break;
1281 }
f54b3f92 1282
f54b3f92 1283 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
f57040be 1284 is_write, &uc->uc_sigmask, puc);
f54b3f92
AJ		 1285}
1286
9de5e440 1287#else
2b413144 1288
3fb2ded1 1289#error host CPU specific signal handler needed
2b413144 1290
9de5e440 1291#endif
67b915a5
FB		 1292
1293#endif /* !defined(CONFIG_SOFTMMU) */
Mirror of https://git.qemu.org/git/qemu.git