]>
Commit | Line | Data |
---|---|---|
afc1ce82 ML |
1 | NDS32 is a new high-performance 32-bit RISC microprocessor core. |
2 | ||
3 | http://www.andestech.com/ | |
4 | ||
5 | AndeStar ISA | |
6 | ============ | |
7 | AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to | |
8 | achieve optimal system performance, code density, and power efficiency. | |
9 | ||
10 | It contains the following features: | |
11 | - Intermixable 32-bit and 16-bit instruction sets without the need for | |
12 | mode switch. | |
13 | - 16-bit instructions as a frequently used subset of 32-bit instructions. | |
14 | - RISC-style register-based instruction set. | |
15 | - 32 32-bit General Purpose Registers (GPR). | |
16 | - Upto 1024 User Special Registers (USR) for existing and extension | |
17 | instructions. | |
18 | - Rich load/store instructions for... | |
19 | - Single memory access with base address update. | |
20 | - Multiple aligned and unaligned memory accesses for memory copy and stack | |
21 | operations. | |
22 | - Data prefetch to improve data cache performance. | |
23 | - Non-bus locking synchronization instructions. | |
24 | - PC relative jump and PC read instructions for efficient position independent | |
25 | code. | |
26 | - Multiply-add and multiple-sub with 64-bit accumulator. | |
27 | - Instruction for efficient power management. | |
28 | - Bi-endian support. | |
29 | - Three instruction extension space for application acceleration: | |
30 | - Performance extension. | |
31 | - Andes future extensions (for floating-point, multimedia, etc.) | |
32 | - Customer extensions. | |
33 | ||
34 | AndesCore CPU | |
35 | ============= | |
36 | Andes Technology has 4 families of CPU cores: N12, N10, N9, N8. | |
37 | ||
38 | For details about N12 CPU family, please check doc/README.N1213. | |
39 | ||
40 | The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and | |
41 | other associated software are actively supported by Andes Technology Corporation. |