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fe8c2806 WD |
1 | # Porting U-Boot onto RPXlite board |
2 | # Written by Yoo. Jonghoon | |
3 | # E-Mail : yooth@ipone.co.kr | |
4 | # IP ONE Inc. | |
5 | ||
6 | # Since 2001. 1. 29 | |
7 | ||
8 | # Shell : bash | |
9 | # Cross-compile tools : Montavista Hardhat | |
10 | # Debugging tools : Windriver VisionProbe (PowerPC BDM) | |
11 | # ppcboot ver. : ppcboot-0.8.1 | |
12 | ||
13 | ############################################################### | |
14 | # 1. Hardware setting | |
15 | ############################################################### | |
16 | ||
17 | 1.1. Board, BDM settings | |
18 | Install board, BDM, connect each other | |
19 | ||
20 | 1.2. Save Register value | |
21 | Boot with board-on monitor program and save the | |
22 | register values with BDM. | |
23 | ||
24 | 1.3. Configure flash programmer | |
25 | Check flash memory area in the memory map. | |
26 | 0xFFC00000 - 0xFFFFFFFF | |
27 | ||
28 | Boot monitor program is at | |
29 | 0xFFF00000 | |
30 | ||
31 | You can program on-board flash memory with VisionClick | |
32 | flash programmer. Set the target flash device as: | |
33 | ||
34 | 29DL800B | |
35 | ||
36 | (?) The flash memory device in the board *is* 29LV800B, | |
37 | but I cannot program it with '29LV800B' option. | |
38 | (in VisionClick flash programming tools) | |
39 | I don't know why... | |
40 | ||
41 | 1.4. Save boot monitor program *IMPORTANT* | |
42 | Upload boot monitor program from board to file. | |
43 | boot monitor program starts at 0xFFF00000 | |
44 | ||
45 | 1.5. Test flash memory programming | |
46 | Try to erase boot program in the flash memory, | |
47 | and re-write them. | |
48 | *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE | |
49 | BEFORE ERASING FLASH | |
50 | ||
51 | ############################################################### | |
52 | # 2. U-Boot setting | |
53 | ############################################################### | |
54 | ||
55 | 2.1. Download U-Boot tarball at | |
56 | ftp://ftp.denx.de | |
57 | (The latest version is ppcboot-0.8.1.tar.bz2) | |
58 | ||
59 | To extract the archive use the following syntax : | |
60 | > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - | |
61 | ||
62 | 2.2. Add the following lines in '.profile' | |
63 | export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin | |
64 | ||
65 | 2.3. Make board specific config, for example: | |
66 | > cd ppcboot-0.8.1 | |
67 | > make TQM860L_config | |
68 | ||
69 | Now we can build ppcboot bin files. | |
70 | After make all, you must see these files in your | |
71 | ppcboot root directory. | |
72 | ||
73 | ppcboot | |
74 | ppcboot.bin | |
75 | ppcboot.srec | |
76 | ppcboot.map | |
77 | ||
78 | 2.4. Make your own board directory into the | |
79 | ppcboot-0.8.1/board | |
80 | and make your board-specific files here. | |
81 | ||
82 | For exmanple, tqm8xx files are composed of | |
83 | .depend : Nothing | |
84 | Makefile : To make config file | |
85 | config.mk : Sets base address | |
86 | flash.c : Flash memory control files | |
87 | ppcboot.lds : linker(ld) script? (I don't know this yet) | |
88 | tqm8xx.c : DRAM control and board check routines | |
89 | ||
90 | And, add your board config lines in the | |
91 | ppcboot-0.8.1/Makefile | |
92 | ||
93 | Finally, add config_(your board).h file in the | |
94 | ppcboot-0.8.1/include/ | |
95 | ||
96 | I've made board/rpxlite directory, and just copied | |
97 | tqm8xx settings for now. | |
98 | ||
99 | Rebuild ppcboot for rpxlite board: | |
100 | > make rpxlite_config | |
101 | > make | |
102 | ||
103 | ############################################################### | |
104 | # 3. U-Boot porting | |
105 | ############################################################### | |
106 | ||
107 | 3.1. My RPXlite files are based on tqm8xx board files. | |
108 | > cd board | |
109 | > cp -r tqm8xx RPXLITE | |
110 | > cd RPXLITE | |
111 | > mv tqm8xx.c RPXLITE.c | |
112 | > cd ../../include | |
113 | > cp config_tqm8xx.h config_RPXLITE.h | |
114 | ||
115 | 3.2. Modified files are: | |
116 | board/RPXLITE/RPXLITE.c /* DRAM-related routines */ | |
117 | board/RPXLITE/flash.c /* flash-related routines */ | |
118 | board/RPXLITE/config.mk /* set text base address */ | |
a47a12be | 119 | arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ |
fe8c2806 WD |
120 | include/config_RPXLITE.h /* board specific registers */ |
121 | ||
122 | See 'reg_config.txt' for register values in detail. | |
123 | ||
124 | ############################################################### | |
125 | # 4. Running Linux | |
126 | ############################################################### | |
127 | ||
128 | ||
fe8c2806 WD |
129 | ############################################################### |
130 | # Misc Information | |
131 | ############################################################### | |
132 | ||
133 | mem_config.txt: | |
134 | =============== | |
135 | ||
136 | Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device | |
137 | manufacturer id : 01 (AMD) | |
138 | device id : 5B (AM29LV800B) | |
139 | size : 4Mbyte | |
140 | sector # : 19 | |
141 | ||
142 | Sector information : | |
143 | ||
144 | number start addr. size | |
145 | 00 FFC0_0000 64 | |
146 | 01 FFC1_0000 32 | |
147 | 02 FFC1_8000 32 | |
148 | 03 FFC2_0000 128 | |
149 | 04 FFC4_0000 256 | |
150 | 05 FFC8_0000 256 | |
151 | 06 FFCC_0000 256 | |
152 | 07 FFD0_0000 256 | |
153 | 08 FFD4_0000 256 | |
154 | 09 FFD8_0000 256 | |
155 | 10 FFDC_0000 256 | |
156 | 11 FFE0_0000 256 | |
157 | 12 FFE4_0000 256 | |
158 | 13 FFE8_0000 256 | |
159 | 14 FFEC_0000 256 | |
160 | 15 FFF0_0000 256 | |
161 | 16 FFF4_0000 256 | |
162 | 17 FFF8_0000 256 | |
163 | 18 FFFC_0000 256 | |
164 | ||
165 | ||
166 | reg_config.txt: | |
167 | =============== | |
168 | ||
169 | ||
170 | /*------------------------------------------------------------------- */ | |
171 | /*------------------------------------------------------------------- */ | |
172 | /* SIU (System Interface Unit) */ | |
173 | /* */ | |
174 | /*------------------------------------------------------------------- */ | |
175 | /*------------------------------------------------------------------- */ | |
176 | ||
177 | ||
178 | /*### IMMR */ | |
179 | /*### Internal Memory Map Register */ | |
180 | /*### Chap. 11.4.1 */ | |
181 | ||
182 | ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ | |
183 | PARTNUM = 0x21 | |
184 | MASKNUM = 0x00 | |
185 | ||
186 | => 0xFA20 2100 | |
187 | ||
188 | --------------------------------------------------------------------- | |
189 | ||
190 | /*### SIUMCR */ | |
191 | /*### SIU Module Configuration Register */ | |
192 | /*### Chap. 11.4.2 */ | |
193 | /*### Offset : 0x0000 0000 */ | |
194 | ||
195 | EARB = 0 | |
196 | EARP = 0 | |
197 | DSHW = 0 | |
198 | DBGC = 0 | |
199 | DBPC = 0 | |
200 | FRC = 0 | |
201 | DLK = 0 | |
202 | OPAR = 0 | |
203 | PNCS = 0 | |
204 | DPC = 0 | |
205 | MPRE = 0 | |
206 | MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ | |
207 | AEME = 0 | |
208 | SEME = 0 | |
209 | BSC = 0 | |
210 | GB5E = 0 | |
211 | B2DD = 0 | |
212 | B3DD = 0 | |
213 | ||
214 | => 0x0000 0800 | |
215 | ||
216 | --------------------------------------------------------------------- | |
217 | ||
218 | /*### SYPCR */ | |
219 | /*### System Protection Control Register */ | |
220 | /*### Chap. 11.4.3 */ | |
221 | /*### Offset : 0x0000 0004 */ | |
222 | ||
223 | SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ | |
224 | BMT = 0x06 /* BUS monitoring timing */ | |
225 | BME = 1 /* BUS monitor enable */ | |
226 | SWF = 1 | |
227 | SWE = 0 /* SW watchdog disable */ | |
228 | SWRI = 0 | |
229 | SWP = 1 | |
230 | ||
231 | => 0xFFFF 0689 | |
232 | ||
233 | --------------------------------------------------------------------- | |
234 | ||
235 | /*### TESR */ | |
236 | /*### Transfer Error Status Register */ | |
237 | /*### Chap. 11.4.4 */ | |
238 | /*### Offset : 0x0000 0020 */ | |
239 | ||
240 | IEXT = 0 | |
241 | ITMT = 0 | |
242 | IPB = 0000 | |
243 | DEXT = 0 | |
244 | DTMT = 0 | |
245 | DPB = 0000 | |
246 | ||
247 | => 0x0000 0000 | |
248 | ||
249 | --------------------------------------------------------------------- | |
250 | ||
251 | /*### SIPEND */ | |
252 | /*### SIU Interrupt Pending Register */ | |
253 | /*### Chap. 11.5.4.1 */ | |
254 | /*### Offset : 0x0000 0010 */ | |
255 | ||
256 | IRQ0~IRQ7 = 0 | |
257 | LVL0~LVL7 = 0 | |
258 | ||
259 | => 0x0000 0000 | |
260 | ||
261 | --------------------------------------------------------------------- | |
262 | ||
263 | /*### SIMASK */ | |
264 | /*### SIU Interrupt Mask Register */ | |
265 | /*### Chap. 11.5.4.2 */ | |
266 | /*### Offset : 0x0000 0014 */ | |
267 | ||
268 | IRM0~IRM7 = 0 /* Mask all interrupts */ | |
269 | LVL0~LVL7 = 0 | |
270 | ||
271 | => 0x0000 0000 | |
272 | ||
273 | --------------------------------------------------------------------- | |
274 | ||
275 | /*### SIEL */ | |
276 | /*### SIU Interrupt Edge/Level Register */ | |
277 | /*### Chap. 11.5.4.3 */ | |
278 | /*### Offset : 0x0000 0018 */ | |
279 | ||
280 | ED0~ED7 = 0 /* Low level triggered */ | |
281 | WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ | |
282 | ||
283 | => 0x0000 0000 | |
284 | ||
285 | --------------------------------------------------------------------- | |
286 | ||
287 | /*### SIVEC */ | |
288 | /*### SIU Interrupt Vector Register */ | |
289 | /*### Chap. 11.5.4.4 */ | |
290 | /*### Offset : 0x0000 001C */ | |
291 | ||
292 | INTC = 3C /* The lowest interrupt is pending..(?) */ | |
293 | ||
294 | => 0x3C00 0000 | |
295 | ||
296 | --------------------------------------------------------------------- | |
297 | ||
298 | /*### SWSR */ | |
299 | /*### Software Service Register */ | |
300 | /*### Chap. 11.7.1 */ | |
301 | /*### Offset : 0x0000 001E */ | |
302 | ||
303 | SEQ = 0 | |
304 | ||
305 | => 0x0000 | |
306 | ||
307 | --------------------------------------------------------------------- | |
308 | ||
309 | /*### SDCR */ | |
310 | /*### SDMA Configuration Register */ | |
311 | /*### Chap. 20.2.1 */ | |
312 | /*### Offset : 0x0000 0032 */ | |
313 | ||
314 | FRZ = 0 | |
315 | RAID = 01 /* Priority level 5 (BR5) (normal operation) */ | |
316 | ||
317 | => 0x0000 0001 | |
318 | ||
319 | ||
320 | /*------------------------------------------------------------------- */ | |
321 | /*------------------------------------------------------------------- */ | |
322 | /* UPMA (User Programmable Machine A) */ | |
323 | /* */ | |
324 | /*------------------------------------------------------------------- */ | |
325 | /*------------------------------------------------------------------- */ | |
326 | ||
327 | /*### Chap. 16.6.4.1 */ | |
328 | /*### Offset = 0x0000 017c */ | |
329 | ||
330 | T0 = CFFF CC24 /* Single Read */ | |
331 | T1 = 0FFF CC04 | |
332 | T2 = 0CAF CC04 | |
333 | T3 = 03AF CC08 | |
334 | T4 = 3FBF CC27 /* last */ | |
335 | T5 = FFFF CC25 | |
336 | T6 = FFFF CC25 | |
337 | T7 = FFFF CC25 | |
338 | T8 = CFFF CC24 /* Burst Read */ | |
339 | T9 = 0FFF CC04 | |
340 | T10 = 0CAF CC84 | |
341 | T11 = 03AF CC88 | |
342 | T12 = 3FBF CC27 /* last */ | |
343 | T13 = FFFF CC25 | |
344 | T14 = FFFF CC25 | |
345 | T15 = FFFF CC25 | |
346 | T16 = FFFF CC25 | |
347 | T17 = FFFF CC25 | |
348 | T18 = FFFF CC25 | |
349 | T19 = FFFF CC25 | |
350 | T20 = FFFF CC25 | |
351 | T21 = FFFF CC25 | |
352 | T22 = FFFF CC25 | |
353 | T23 = FFFF CC25 | |
354 | T24 = CFFF CC24 /* Single Write */ | |
355 | T25 = 0FFF CC04 | |
356 | T26 = 0CFF CC04 | |
357 | T27 = 03FF CC00 | |
358 | T28 = 3FFF CC27 /* last */ | |
359 | T29 = FFFF CC25 | |
360 | T30 = FFFF CC25 | |
361 | T31 = FFFF CC25 | |
362 | T32 = CFFF CC24 /* Burst Write */ | |
363 | T33 = 0FFF CC04 | |
364 | T34 = 0CFF CC80 | |
365 | T35 = 03FF CC8C | |
366 | T36 = 0CFF CC00 | |
367 | T37 = 33FF CC27 /* last */ | |
368 | T38 = FFFF CC25 | |
369 | T39 = FFFF CC25 | |
370 | T40 = FFFF CC25 | |
371 | T41 = FFFF CC25 | |
372 | T42 = FFFF CC25 | |
373 | T43 = FFFF CC25 | |
374 | T44 = FFFF CC25 | |
375 | T45 = FFFF CC25 | |
376 | T46 = FFFF CC25 | |
377 | T47 = FFFF CC25 | |
378 | T48 = C0FF CC24 /* Refresh */ | |
379 | T49 = 03FF CC24 | |
380 | T50 = 0FFF CC24 | |
381 | T51 = 0FFF CC24 | |
382 | T52 = 3FFF CC27 /* last */ | |
383 | T53 = FFFF CC25 | |
384 | T54 = FFFF CC25 | |
385 | T55 = FFFF CC25 | |
386 | T56 = FFFF CC25 | |
387 | T57 = FFFF CC25 | |
388 | T58 = FFFF CC25 | |
389 | T59 = FFFF CC25 | |
390 | T60 = FFFF CC25 /* Exception */ | |
391 | T61 = FFFF CC25 | |
392 | T62 = FFFF CC25 | |
393 | T63 = FFFF CC25 | |
394 | ||
395 | ||
396 | /*------------------------------------------------------------------- */ | |
397 | /*------------------------------------------------------------------- */ | |
398 | /* UPMB */ | |
399 | /* */ | |
400 | /*------------------------------------------------------------------- */ | |
401 | /*------------------------------------------------------------------- */ | |
402 | --------------------------------------------------------------------- | |
403 | ||
404 | /*### Chap. 16.6.4.1 */ | |
405 | ||
406 | ||
407 | /*------------------------------------------------------------------- */ | |
408 | /*------------------------------------------------------------------- */ | |
409 | /* MEMC */ | |
410 | /* */ | |
411 | /*------------------------------------------------------------------- */ | |
412 | /*------------------------------------------------------------------- */ | |
413 | --------------------------------------------------------------------- | |
414 | ||
415 | /*### BR0 & OR0 */ | |
416 | /*### Base Registers & Option Registers */ | |
417 | /*### Chap. 16.4.1 & 16.4.2 */ | |
418 | /*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ | |
419 | /*### Flash memory */ | |
420 | ||
421 | BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ | |
422 | AT = 000 | |
423 | PS = 00 | |
424 | PARE = 0 | |
425 | WP = 0 | |
426 | MS = 0 /* GPCM */ | |
427 | V = 1 /* Valid */ | |
428 | ||
429 | => 0xFE00 0001 | |
430 | ||
431 | AM = 1111 1110 0000 0000 0 /* 32MBytes */ | |
432 | ATM = 000 | |
433 | CSNT/SAM = 0 | |
434 | ACS/G5LA,G5LS = 00 | |
435 | BIH = 1 /* Burst inhibited */ | |
436 | SCY = 0100 /* cycle length = 4 */ | |
437 | SETA = 0 | |
438 | TRLX = 0 | |
439 | EHTR = 0 | |
440 | ||
441 | => 0xFE00 0140 | |
442 | ||
443 | /*### BR1 & OR1 */ | |
444 | /*### Base Registers & Option Registers */ | |
445 | /*### Chap. 16.4.1 & 16.4.2 */ | |
446 | /*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ | |
447 | /*### SDRAM */ | |
448 | ||
449 | BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ | |
450 | AT = 000 | |
451 | PS = 00 | |
452 | PARE = 0 | |
453 | WP = 0 | |
53677ef1 | 454 | MS = 1 /* UPMA */ |
fe8c2806 WD |
455 | V = 1 /* Valid */ |
456 | ||
457 | => 0x0000 0081 | |
458 | ||
459 | AM = 1111 1110 0000 0000 /* 32MBytes */ | |
460 | ATM = 000 | |
461 | CSNT/SAM = 1 | |
462 | ACS/G5LA,G5LS = 11 | |
463 | BIH = 0 | |
464 | SCY = 0000 /* cycle length = 0 */ | |
465 | SETA = 0 | |
466 | TRLX = 0 | |
467 | EHTR = 0 | |
468 | ||
469 | => 0xFE00 0E00 | |
470 | ||
471 | /*### BR2 & OR2 */ | |
472 | /*### Base Registers & Option Registers */ | |
473 | /*### Chap. 16.4.1 & 16.4.2 */ | |
474 | /*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ | |
475 | ||
476 | BR2 & OR2 = 0x0000 0000 /* Not used */ | |
477 | ||
478 | /*### BR3 & OR3 */ | |
479 | /*### Base Registers & Option Registers */ | |
480 | /*### Chap. 16.4.1 & 16.4.2 */ | |
481 | /*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ | |
482 | /*### BCSR */ | |
483 | ||
484 | BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ | |
485 | AT = 000 | |
486 | PS = 00 | |
487 | PARE = 0 | |
488 | WP = 0 | |
53677ef1 | 489 | MS = 0 /* GPCM */ |
fe8c2806 WD |
490 | V = 1 /* Valid */ |
491 | ||
492 | => 0xFA40 0001 | |
493 | ||
494 | AM = 1111 1111 0111 1111 1 /* (?) */ | |
495 | ATM = 000 | |
496 | CSNT/SAM = 1 | |
497 | ACS/G5LA,G5LS = 00 | |
498 | BIH = 1 /* Burst inhibited */ | |
499 | SCY = 0001 /* cycle length = 1 */ | |
500 | SETA = 0 | |
501 | TRLX = 0 | |
502 | ||
503 | => 0xFF7F 8910 | |
504 | ||
505 | /*### BR4 & OR4 */ | |
506 | /*### Base Registers & Option Registers */ | |
507 | /*### Chap. 16.4.1 & 16.4.2 */ | |
508 | /*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ | |
509 | /*### NVRAM & SRAM */ | |
510 | ||
511 | BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ | |
512 | AT = 000 | |
513 | PS = 01 | |
514 | PARE = 0 | |
515 | WP = 0 | |
53677ef1 | 516 | MS = 0 /* GPCM */ |
fe8c2806 WD |
517 | V = 1 /* Valid */ |
518 | ||
519 | => 0xFA00 0401 | |
520 | ||
521 | AM = 1111 1111 1111 1000 0 /* 8MByte */ | |
522 | ATM = 000 | |
523 | CSNT/SAM = 1 | |
524 | ACS/G5LA,G5LS = 00 | |
525 | BIH = 1 /* Burst inhibited */ | |
526 | SCY = 0111 /* cycle length = 7 */ | |
527 | SETA = 0 | |
528 | TRLX = 0 | |
529 | ||
530 | => 0xFFF8 0970 | |
531 | ||
532 | /*### BR5 & OR5 */ | |
533 | /*### Base Registers & Option Registers */ | |
534 | /*### Chap. 16.4.1 & 16.4.2 */ | |
535 | /*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ | |
536 | ||
537 | BR5 & OR5 = 0x0000 0000 /* Not used */ | |
538 | ||
539 | /*### BR6 & OR6 */ | |
540 | /*### Base Registers & Option Registers */ | |
541 | /*### Chap. 16.4.1 & 16.4.2 */ | |
542 | /*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ | |
543 | ||
544 | BR6 & OR6 = 0x0000 0000 /* Not used */ | |
545 | ||
546 | /*### BR7 & OR7 */ | |
547 | /*### Base Registers & Option Registers */ | |
548 | /*### Chap. 16.4.1 & 16.4.2 */ | |
549 | /*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ | |
550 | ||
551 | BR7 & OR7 = 0x0000 0000 /* Not used */ | |
552 | ||
553 | /*### MAR */ | |
554 | /*### Memory Address Register */ | |
555 | /*### Chap. 16.4.7 */ | |
556 | /*### Offset : 0x0000 0164 */ | |
557 | ||
558 | MA = External memory address | |
559 | ||
560 | /*### MCR */ | |
561 | /*### Memory Command Register */ | |
562 | /*### Chap. 16.4.5 */ | |
563 | /*### Offset : 0x0000 0168 */ | |
564 | ||
565 | OP = xx /* Command op code */ | |
566 | UM = 1 /* Select UPMA */ | |
567 | MB = 001 /* Select CS1 */ | |
568 | MCLF = xxxx /* Loop times */ | |
569 | MAD = xx xxxx /* Memory array index */ | |
570 | ||
571 | /*### MAMR */ | |
572 | /*### Machine A Mode Register */ | |
573 | /*### Chap. 16.4.4 */ | |
574 | /*### Offset : 0x0000 0170 */ | |
575 | ||
576 | PTA = 0101 1000 | |
577 | PTAE = 1 /* Periodic timer A enabled */ | |
578 | AMA = 010 | |
579 | DSA = 00 | |
580 | G0CLA = 000 | |
581 | GPLA4DIS = 1 | |
582 | RLFA = 0100 | |
583 | WLFA = 0011 | |
584 | TLFA = 0000 | |
585 | ||
586 | => 0x58A0 1430 | |
587 | ||
588 | /*### MBMR */ | |
589 | /*### Machine B Mode Register */ | |
590 | /*### Chap. 16.4.4 */ | |
591 | /*### Offset : 0x0000 0174 */ | |
592 | ||
593 | PTA = 0100 1110 | |
594 | PTAE = 0 /* Periodic timer B disabled */ | |
595 | AMA = 000 | |
596 | DSA = 00 | |
597 | G0CLA = 000 | |
598 | GPLA4DIS = 1 | |
599 | RLFA = 0000 | |
600 | WLFA = 0000 | |
601 | TLFA = 0000 | |
602 | ||
603 | => 0x4E00 1000 | |
604 | ||
605 | /*### MSTAT */ | |
606 | /*### Memory Status Register */ | |
607 | /*### Chap. 16.4.3 */ | |
608 | /*### Offset : 0x0000 0178 */ | |
609 | ||
610 | PER0~PER7 = Parity error | |
611 | WPER = Write protection error | |
612 | ||
613 | => 0x0000 | |
614 | ||
615 | /*### MPTPR */ | |
616 | /*### Memory Periodic Timer Prescaler Register */ | |
617 | /*### Chap. 16.4.8 */ | |
618 | /*### Offset : 0x0000 017A */ | |
619 | ||
620 | PTP = 0000 1000 /* Divide by 8 */ | |
621 | ||
622 | => 0x0800 | |
623 | ||
624 | /*### MDR */ | |
625 | /*### Memory Data Register */ | |
626 | /*### Chap. 16.4.6 */ | |
627 | /*### Offset : 0x0000 017C */ | |
628 | ||
629 | MD = Memory data contains the RAM array word | |
630 | ||
631 | ||
632 | /*------------------------------------------------------------------- */ | |
633 | /*------------------------------------------------------------------- */ | |
634 | /* TIMERS */ | |
635 | /* */ | |
636 | /*------------------------------------------------------------------- */ | |
637 | /*------------------------------------------------------------------- */ | |
638 | --------------------------------------------------------------------- | |
639 | ||
640 | /*### TBREFx */ | |
641 | /*### Timebase Reference Registers */ | |
642 | /*### Chap. 11.9.2 */ | |
643 | /*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ | |
644 | /*### (Locked) */ | |
645 | ||
646 | TBREFF0 = 0xFFFF FFFF | |
647 | TBREFF1 = 0xFFFF FFFF | |
648 | ||
649 | --------------------------------------------------------------------- | |
650 | ||
651 | /*### TBSCR */ | |
652 | /*### Timebase Status and Control Registers */ | |
653 | /*### Chap. 11.9.3 */ | |
654 | /*### Offset : 0x0000 0200 */ | |
655 | /*### (Locked) */ | |
656 | ||
657 | TBIRQ = 00000000 | |
658 | REF0 = 0 | |
659 | REF1 = 0 | |
660 | REFE0 = 0 /* Reference interrupt disable */ | |
661 | REFE1 = 0 | |
662 | TBF = 1 | |
663 | TBE = 1 /* Timebase enable */ | |
664 | ||
665 | => 0x0003 | |
666 | ||
667 | --------------------------------------------------------------------- | |
668 | ||
669 | /*### RTCSC */ | |
670 | /*### Real-Time Clock Status and Control Registers */ | |
671 | /*### Chap. 11.10.1 */ | |
672 | /*### Offset : 0x0000 0220 */ | |
673 | /*### (Locked) */ | |
674 | ||
675 | RTCIRQ = 00000000 | |
676 | SEC = 1 | |
677 | ALR = 0 | |
678 | 38K = 0 /* PITRTCLK is driven by 32.768KHz */ | |
679 | SIE = 0 | |
680 | ALE = 0 | |
681 | RTF = 0 | |
682 | RTE = 1 /* Real-Time clock enabled */ | |
683 | ||
684 | => 0x0081 | |
685 | ||
686 | --------------------------------------------------------------------- | |
687 | ||
688 | /*### RTC */ | |
689 | /*### Real-Time Clock Registers */ | |
690 | /*### Chap. 11.10.2 */ | |
691 | /*### Offset : 0x0000 0224 */ | |
692 | /*### (Locked) */ | |
693 | ||
694 | RTC = Real time clock measured in second | |
695 | ||
696 | --------------------------------------------------------------------- | |
697 | ||
698 | /*### RTCAL */ | |
699 | /*### Real-Time Clock Alarm Registers */ | |
700 | /*### Chap. 11.10.3 */ | |
701 | /*### Offset : 0x0000 022C */ | |
702 | /*### (Locked) */ | |
703 | ||
704 | ALARM = 0xFFFF FFFF | |
705 | ||
706 | --------------------------------------------------------------------- | |
707 | ||
708 | /*### RTSEC */ | |
709 | /*### Real-Time Clock Alarm Second Registers */ | |
710 | /*### Chap. 11.10.4 */ | |
711 | /*### Offset : 0x0000 0228 */ | |
712 | /*### (Locked) */ | |
713 | ||
714 | COUNTER = Counter bits(fraction of a second) | |
715 | ||
716 | --------------------------------------------------------------------- | |
717 | ||
718 | /*### PISCR */ | |
719 | /*### Periodic Interrupt Status and Control Register */ | |
720 | /*### Chap. 11.11.1 */ | |
721 | /*### Offset : 0x0000 0240 */ | |
722 | /*### (Locked) */ | |
723 | ||
724 | PIRQ = 0 | |
725 | PS = 0 /* Write 1 to clear */ | |
726 | PIE = 0 | |
727 | PITF = 1 | |
728 | PTE = 0 /* PIT disabled */ | |
729 | ||
730 | --------------------------------------------------------------------- | |
731 | ||
732 | /*### PITC */ | |
733 | /*### PIT Count Register */ | |
734 | /*### Chap. 11.11.2 */ | |
735 | /*### Offset : 0x0000 0244 */ | |
736 | /*### (Locked) */ | |
737 | ||
738 | PITC = PIT count | |
739 | ||
740 | --------------------------------------------------------------------- | |
741 | ||
742 | /*### PITR */ | |
743 | /*### PIT Register */ | |
744 | /*### Chap. 11.11.3 */ | |
745 | /*### Offset : 0x0000 0248 */ | |
746 | /*### (Locked) */ | |
747 | ||
748 | PIT = PIT count /* Read only */ | |
749 | ||
750 | ||
fe8c2806 WD |
751 | /*------------------------------------------------------------------- */ |
752 | /*------------------------------------------------------------------- */ | |
753 | /* CLOCKS */ | |
754 | /* */ | |
755 | /*------------------------------------------------------------------- */ | |
756 | /*------------------------------------------------------------------- */ | |
757 | --------------------------------------------------------------------- | |
758 | ||
759 | ||
760 | --------------------------------------------------------------------- | |
761 | ||
762 | /*### SCCR */ | |
763 | /*### System Clock and Reset Control Register */ | |
764 | /*### Chap. 15.6.1 */ | |
765 | /*### Offset : 0x0000 0280 */ | |
766 | /*### (Locked) */ | |
767 | ||
768 | COM = 11 /* Clock output disabled */ | |
769 | TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ | |
770 | RTDIV = 0 /* The clock is divided by 4 */ | |
771 | RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ | |
772 | CRQEN = 0 | |
773 | PRQEN = 0 | |
774 | EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ | |
775 | DFSYNC = 00 /* Divided by 1 (normal operation) */ | |
776 | DFBRG = 00 /* Divided by 1 (normal operation) */ | |
777 | DFNL = 000 | |
778 | DFNH = 000 | |
779 | ||
780 | => 0x6200 0000 | |
781 | ||
782 | --------------------------------------------------------------------- | |
783 | ||
784 | /*### PLPRCR */ | |
785 | /*### PLL, Low-Power, and Reset Control Register */ | |
786 | /*### Chap. 15.6.2 */ | |
787 | /*### Offset : 0x0000 0284 */ | |
788 | /*### (Locked) */ | |
789 | ||
790 | MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ | |
791 | SPLSS = 0 | |
792 | TEXPS = 0 | |
793 | TMIST = 0 | |
794 | CSRC = 0 /* The general system clock is generated by the DFNH field */ | |
795 | LPM = 00 /* Normal high/normal low mode */ | |
796 | CSR = 0 | |
797 | LOLRE = 0 | |
798 | FIOPD = 0 | |
799 | ||
800 | => 0x0050 0000 | |
801 | ||
802 | --------------------------------------------------------------------- | |
803 | ||
804 | /*### RSR */ | |
805 | /*### Reset Status Register */ | |
806 | /*### Chap. 12.2 */ | |
807 | /*### Offset : 0x0000 0288 */ | |
808 | /*### (Locked) */ | |
809 | ||
810 | EHRS = External hard reset | |
811 | ESRS = External soft reset | |
812 | LLRS = Loss-of-lock reset | |
813 | SWRS = Software watchdog reset | |
814 | CSRS = Check stop reset | |
815 | DBHRS = Debug port hard reset | |
816 | DBSRS = Debug port soft reset | |
817 | JTRS = JTAG reset | |
818 | ||
819 | ||
fe8c2806 WD |
820 | /*------------------------------------------------------------------- */ |
821 | /*------------------------------------------------------------------- */ | |
822 | /* DMA */ | |
823 | /* */ | |
824 | /*------------------------------------------------------------------- */ | |
825 | /*------------------------------------------------------------------- */ | |
826 | --------------------------------------------------------------------- | |
827 | ||
828 | /*### SDSR */ | |
829 | /*### SDMA Status Register */ | |
830 | /*### Chap. 20.2.2 */ | |
831 | /*### Offset : 0x0000 0908 */ | |
832 | ||
833 | SBER = 0 /* SDMA channel bus error */ | |
834 | DSP2 = 0 /* DSP chain2 (Tx) interrupt */ | |
835 | DSP1 = 0 /* DSP chain1 (Rx) interrupt */ | |
836 | ||
837 | => 0x00 | |
838 | ||
839 | /*### SDMR */ | |
840 | /*### SDMA Mask Register */ | |
841 | /*### Chap. 20.2.3 */ | |
842 | /*### Offset : 0x0000 090C */ | |
843 | ||
844 | SBER = 0 | |
845 | DSP2 = 0 | |
846 | DSP1 = 0 /* All interrupts are masked */ | |
847 | ||
848 | => 0x00 | |
849 | ||
850 | /*### SDAR */ | |
851 | /*### SDMA Address Register */ | |
852 | /*### Chap. 20.2.4 */ | |
853 | /*### Offset : 0x0000 0904 */ | |
854 | ||
855 | AR = 0xxxxx xxxx /* current system address */ | |
856 | ||
857 | => 0xFA20 23AC | |
858 | ||
859 | /*### IDSRx */ | |
860 | /*### IDMA Status Register */ | |
861 | /*### Chap. 20.3.3.2 */ | |
862 | /*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ | |
863 | ||
864 | AD = 0 | |
865 | DONE = 0 | |
866 | OB = 0 | |
867 | ||
868 | => 0x00 | |
869 | ||
870 | /*### IDMRx */ | |
871 | /*### IDMA Mask Register */ | |
872 | /*### Chap. 20.3.3.3 */ | |
873 | /*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ | |
874 | ||
875 | AD = 0 | |
876 | DONE = 0 | |
877 | OB = 0 |