[people/ms/u-boot.git] / doc / README.arm-caches

Disabling I-cache:
- Set CONFIG_SYS_ICACHE_OFF

Disabling D-cache:
- Set CONFIG_SYS_DCACHE_OFF

Enabling I-cache:
- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable().

Enabling D-cache:
- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable().

Enabling Caches at System Startup:
- Implement enable_caches() for your platform and enable the I-cache and
  D-cache from this function. This function is called immediately
  after relocation.

Guidelines for Working with D-cache:

Memory to Peripheral DMA:
- Flush the buffer after the MPU writes the data and before the DMA is
  initiated.

Peripheral to Memory DMA:
- Invalidate the buffer before starting the DMA. In case there are any dirty
  lines from the DMA buffer in the cache, subsequent cache-line replacements
  may corrupt the buffer in memory while the DMA is still going on. Cache-line
  replacement can happen if the CPU tries to bring some other memory locations
  into the cache while the DMA is going on.
- Invalidate the buffer after the DMA is complete and before the MPU reads
  it. This may be needed in addition to the invalidation before the DMA
  mentioned above, because in some processors memory contents can spontaneously
  come to the cache due to speculative memory access by the CPU. If this
  happens with the DMA buffer while DMA is going on we have a coherency problem.

Buffer Requirements:
- Any buffer that is invalidated(that is, typically the peripheral to
  memory DMA buffer) should be aligned to cache-line boundary both at
  at the beginning and at the end of the buffer.
- If the buffer is not cache-line aligned invalidation will be restricted
  to the aligned part. That is, one cache-line at the respective boundary
  may be left out while doing invalidation.
- A suitable buffer can be alloced on the stack using the
  ALLOC_CACHE_ALIGN_BUFFER macro.

Cleanup Before Linux:
- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
  disable MMU and caches.
- The following sequence is advisable while disabling d-cache:
  1. dcache_disable() - flushes and disables d-cache
  2. invalidate_dcache_all() - invalid any entry that came to the cache
	in the short period after the cache was flushed but before the
	cache got disabled.
Commit	Line	Data
cba4b180 A	1	Disabling I-cache:
	2	- Set CONFIG_SYS_ICACHE_OFF
	3
	4	Disabling D-cache:
	5	- Set CONFIG_SYS_DCACHE_OFF
	6
	7	Enabling I-cache:
	8	- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable().
	9
	10	Enabling D-cache:
	11	- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable().
	12
	13	Enabling Caches at System Startup:
	14	- Implement enable_caches() for your platform and enable the I-cache and
	15	D-cache from this function. This function is called immediately
	16	after relocation.
	17
	18	Guidelines for Working with D-cache:
	19
	20	Memory to Peripheral DMA:
	21	- Flush the buffer after the MPU writes the data and before the DMA is
	22	initiated.
	23
	24	Peripheral to Memory DMA:
	25	- Invalidate the buffer before starting the DMA. In case there are any dirty
	26	lines from the DMA buffer in the cache, subsequent cache-line replacements
	27	may corrupt the buffer in memory while the DMA is still going on. Cache-line
	28	replacement can happen if the CPU tries to bring some other memory locations
	29	into the cache while the DMA is going on.
	30	- Invalidate the buffer after the DMA is complete and before the MPU reads
	31	it. This may be needed in addition to the invalidation before the DMA
	32	mentioned above, because in some processors memory contents can spontaneously
	33	come to the cache due to speculative memory access by the CPU. If this
	34	happens with the DMA buffer while DMA is going on we have a coherency problem.
	35
	36	Buffer Requirements:
	37	- Any buffer that is invalidated(that is, typically the peripheral to
	38	memory DMA buffer) should be aligned to cache-line boundary both at
	39	at the beginning and at the end of the buffer.
	40	- If the buffer is not cache-line aligned invalidation will be restricted
	41	to the aligned part. That is, one cache-line at the respective boundary
	42	may be left out while doing invalidation.
46a6d51c A	43	- A suitable buffer can be alloced on the stack using the
46a6d51c A	44	ALLOC_CACHE_ALIGN_BUFFER macro.
cba4b180 A	45
	46	Cleanup Before Linux:
	47	- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
	48	disable MMU and caches.
	49	- The following sequence is advisable while disabling d-cache:
421044b1	50	1. dcache_disable() - flushes and disables d-cache
cba4b180 A	51	2. invalidate_dcache_all() - invalid any entry that came to the cache
	52	in the short period after the cache was flushed but before the
	53	cache got disabled.