[people/ms/u-boot.git] / doc / README.nand

NAND FLASH commands and notes

# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA

Commands:

   nand bad
      Print a list of all of the bad blocks in the current device.

   nand device
      Print information about the current NAND device.

   nand device num
      Make device `num' the current device and print information about it.

   nand erase off size
   nand erase clean [off size]
      Erase `size' bytes starting at offset `off'.  Only complete erase
      blocks can be erased.

      If `clean' is specified, a JFFS2-style clean marker is written to
      each block after it is erased. If `clean' is specified without an
      offset or size, the entire flash is erased.

      This command will not erase blocks that are marked bad. There is
      a debug option in cmd_nand.c to allow bad blocks to be erased.
      Please read the warning there before using it, as blocks marked
      bad by the manufacturer must _NEVER_ be erased.

   nand info
      Print information about all of the NAND devices found.

   nand read addr ofs size
      Read `size' bytes from `ofs' in NAND flash to `addr'. If a page
      cannot be read because it is marked bad or an uncorrectable data
      error is found the command stops with an error.

   nand read.jffs2 addr ofs size
      Like `read', but the data for blocks that are marked bad is read as
      0xff. This gives a readable JFFS2 image that can be processed by
      the JFFS2 commands such as ls and fsload.

   nand read.oob addr ofs size
      Read `size' bytes from the out-of-band data area corresponding to
      `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
      data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks or ECC errors.

   nand write addr ofs size
      Write `size' bytes from `addr' to `ofs' in NAND flash. If a page
      cannot be written because it is marked bad or the write fails the
      command stops with an error.

   nand write.jffs2 addr ofs size
      Like `write', but blocks that are marked bad are skipped and the
      is written to the next block instead. This allows writing writing
      a JFFS2 image, as long as the image is short enough to fit even
      after skipping the bad blocks. Compact images, such as those
      produced by mkfs.jffs2 should work well, but loading an image copied
      from another flash is going to be trouble if there are any bad blocks.

   nand write.oob addr ofs size
      Write `size' bytes from `addr' to the out-of-band data area
      corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
      of data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks.

Configuration Options:

   CFG_CMD_NAND
      A good one to add to CONFIG_COMMANDS since it enables NAND support.

   CONFIG_MTD_NAND_ECC_JFFS2
      Define this if you want the Error Correction Code information in
      the out-of-band data to be formatted to match the JFFS2 file system.
      CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
      someone to implement.

   CFG_MAX_NAND_DEVICE
      The maximum number of NAND devices you want to support.

NAND Interface:

   #define NAND_WAIT_READY(nand)
      Wait until the NAND flash is ready. Typically this would be a
      loop waiting for the READY/BUSY line from the flash to indicate it
      it is ready.

   #define WRITE_NAND_COMMAND(d, adr)
      Write the command byte `d' to the flash at `adr' with the
      CLE (command latch enable) line true. If your board uses writes to
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_SETCLE()
      and company do it.

   #define WRITE_NAND_ADDRESS(d, adr)
      Write the address byte `d' to the flash at `adr' with the
      ALE (address latch enable) line true. If your board uses writes to
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_SETALE()
      and company do it.

   #define WRITE_NAND(d, adr)
      Write the data byte `d' to the flash at `adr' with the
      ALE and CLE lines false. If your board uses writes to
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_CLRALE()
      and company do it.

   #define READ_NAND(adr)
      Read a data byte from the flash at `adr' with the
      ALE and CLE lines false. If your board uses reads from
      different addresses to control CLE and ALE, you can modify `adr'
      to be the appropriate address here. If your board uses I/O registers
      to control them, it is probably better to let NAND_CTL_CLRALE()
      and company do it.

   #define NAND_DISABLE_CE(nand)
      Set CE (Chip Enable) low to enable the NAND flash.

   #define NAND_ENABLE_CE(nand)
      Set CE (Chip Enable) high to disable the NAND flash.

   #define NAND_CTL_CLRALE(nandptr)
      Set ALE (address latch enable) low. If ALE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

   #define NAND_CTL_SETALE(nandptr)
      Set ALE (address latch enable) high. If ALE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

   #define NAND_CTL_CLRCLE(nandptr)
      Set CLE (command latch enable) low. If CLE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

   #define NAND_CTL_SETCLE(nandptr)
      Set CLE (command latch enable) high. If CLE control is handled by
      WRITE_NAND_ADDRESS() this can be empty.

More Definitions:

   These definitions are needed in the board configuration for now, but
   may really belong in a header file.
   TODO: Figure which ones are truly configuration settings and rename
	 them to CFG_NAND_... and move the rest somewhere appropriate.

   #define SECTORSIZE 512
   #define ADDR_COLUMN 1
   #define ADDR_PAGE 2
   #define ADDR_COLUMN_PAGE 3
   #define NAND_ChipID_UNKNOWN 0x00
   #define NAND_MAX_FLOORS 1
   #define NAND_MAX_CHIPS 1
Commit	Line	Data
7a8e9bed WD	1	NAND FLASH commands and notes
	2
	3	# (C) Copyright 2003
	4	# Dave Ellis, SIXNET, dge@sixnetio.com
	5	#
	6	# See file CREDITS for list of people who contributed to this
	7	# project.
	8	#
	9	# This program is free software; you can redistribute it and/or
	10	# modify it under the terms of the GNU General Public License as
	11	# published by the Free Software Foundation; either version 2 of
	12	# the License, or (at your option) any later version.
	13	#
	14	# This program is distributed in the hope that it will be useful,
	15	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	# GNU General Public License for more details.
	18	#
	19	# You should have received a copy of the GNU General Public License
	20	# along with this program; if not, write to the Free Software
	21	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	# MA 02111-1307 USA
	23
	24	Commands:
	25
	26	nand bad
	27	Print a list of all of the bad blocks in the current device.
	28
	29	nand device
	30	Print information about the current NAND device.
	31
	32	nand device num
	33	Make device `num' the current device and print information about it.
	34
	35	nand erase off size
	36	nand erase clean [off size]
	37	Erase `size' bytes starting at offset `off'. Only complete erase
	38	blocks can be erased.
	39
	40	If `clean' is specified, a JFFS2-style clean marker is written to
	41	each block after it is erased. If `clean' is specified without an
	42	offset or size, the entire flash is erased.
	43
	44	This command will not erase blocks that are marked bad. There is
	45	a debug option in cmd_nand.c to allow bad blocks to be erased.
	46	Please read the warning there before using it, as blocks marked
	47	bad by the manufacturer must _NEVER_ be erased.
	48
	49	nand info
	50	Print information about all of the NAND devices found.
	51
	52	nand read addr ofs size
	53	Read `size' bytes from `ofs' in NAND flash to `addr'. If a page
	54	cannot be read because it is marked bad or an uncorrectable data
8bde7f77	55	error is found the command stops with an error.
7a8e9bed WD	56
	57	nand read.jffs2 addr ofs size
	58	Like `read', but the data for blocks that are marked bad is read as
	59	0xff. This gives a readable JFFS2 image that can be processed by
	60	the JFFS2 commands such as ls and fsload.
	61
	62	nand read.oob addr ofs size
	63	Read `size' bytes from the out-of-band data area corresponding to
	64	`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
	65	data for one 512-byte page or 2 256-byte pages. There is no check
	66	for bad blocks or ECC errors.
	67
	68	nand write addr ofs size
	69	Write `size' bytes from `addr' to `ofs' in NAND flash. If a page
	70	cannot be written because it is marked bad or the write fails the
8bde7f77	71	command stops with an error.
7a8e9bed WD	72
	73	nand write.jffs2 addr ofs size
	74	Like `write', but blocks that are marked bad are skipped and the
	75	is written to the next block instead. This allows writing writing
	76	a JFFS2 image, as long as the image is short enough to fit even
	77	after skipping the bad blocks. Compact images, such as those
	78	produced by mkfs.jffs2 should work well, but loading an image copied
	79	from another flash is going to be trouble if there are any bad blocks.
	80
	81	nand write.oob addr ofs size
	82	Write `size' bytes from `addr' to the out-of-band data area
	83	corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
	84	of data for one 512-byte page or 2 256-byte pages. There is no check
	85	for bad blocks.
	86
	87	Configuration Options:
	88
	89	CFG_CMD_NAND
	90	A good one to add to CONFIG_COMMANDS since it enables NAND support.
	91
	92	CONFIG_MTD_NAND_ECC_JFFS2
	93	Define this if you want the Error Correction Code information in
	94	the out-of-band data to be formatted to match the JFFS2 file system.
	95	CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
	96	someone to implement.
	97
	98	CFG_MAX_NAND_DEVICE
	99	The maximum number of NAND devices you want to support.
	100
	101	NAND Interface:
	102
	103	#define NAND_WAIT_READY(nand)
	104	Wait until the NAND flash is ready. Typically this would be a
	105	loop waiting for the READY/BUSY line from the flash to indicate it
	106	it is ready.
	107
	108	#define WRITE_NAND_COMMAND(d, adr)
	109	Write the command byte `d' to the flash at `adr' with the
	110	CLE (command latch enable) line true. If your board uses writes to
	111	different addresses to control CLE and ALE, you can modify `adr'
	112	to be the appropriate address here. If your board uses I/O registers
	113	to control them, it is probably better to let NAND_CTL_SETCLE()
	114	and company do it.
	115
	116	#define WRITE_NAND_ADDRESS(d, adr)
	117	Write the address byte `d' to the flash at `adr' with the
	118	ALE (address latch enable) line true. If your board uses writes to
	119	different addresses to control CLE and ALE, you can modify `adr'
	120	to be the appropriate address here. If your board uses I/O registers
	121	to control them, it is probably better to let NAND_CTL_SETALE()
	122	and company do it.
	123
	124	#define WRITE_NAND(d, adr)
	125	Write the data byte `d' to the flash at `adr' with the
	126	ALE and CLE lines false. If your board uses writes to
	127	different addresses to control CLE and ALE, you can modify `adr'
	128	to be the appropriate address here. If your board uses I/O registers
	129	to control them, it is probably better to let NAND_CTL_CLRALE()
	130	and company do it.
	131
	132	#define READ_NAND(adr)
	133	Read a data byte from the flash at `adr' with the
	134	ALE and CLE lines false. If your board uses reads from
	135	different addresses to control CLE and ALE, you can modify `adr'
136	to be the appropriate address here. If your board uses I/O registers
137	to control them, it is probably better to let NAND_CTL_CLRALE()
138	and company do it.
139
140	#define NAND_DISABLE_CE(nand)
141	Set CE (Chip Enable) low to enable the NAND flash.
142
143	#define NAND_ENABLE_CE(nand)
144	Set CE (Chip Enable) high to disable the NAND flash.
145
146	#define NAND_CTL_CLRALE(nandptr)
147	Set ALE (address latch enable) low. If ALE control is handled by
148	WRITE_NAND_ADDRESS() this can be empty.
149
150	#define NAND_CTL_SETALE(nandptr)
151	Set ALE (address latch enable) high. If ALE control is handled by
152	WRITE_NAND_ADDRESS() this can be empty.
153
154	#define NAND_CTL_CLRCLE(nandptr)
155	Set CLE (command latch enable) low. If CLE control is handled by
156	WRITE_NAND_ADDRESS() this can be empty.
157
158	#define NAND_CTL_SETCLE(nandptr)
159	Set CLE (command latch enable) high. If CLE control is handled by
160	WRITE_NAND_ADDRESS() this can be empty.
8bde7f77	161
7a8e9bed WD	162	More Definitions:
	163
	164	These definitions are needed in the board configuration for now, but
	165	may really belong in a header file.
	166	TODO: Figure which ones are truly configuration settings and rename
8bde7f77	167	them to CFG_NAND_... and move the rest somewhere appropriate.
7a8e9bed WD	168
	169	#define SECTORSIZE 512
	170	#define ADDR_COLUMN 1
	171	#define ADDR_PAGE 2
	172	#define ADDR_COLUMN_PAGE 3
	173	#define NAND_ChipID_UNKNOWN 0x00
	174	#define NAND_MAX_FLOORS 1
	175	#define NAND_MAX_CHIPS 1