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Commit | Line | Data |
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06c11796 SL |
1 | Overview |
2 | ========= | |
3 | The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. | |
4 | ||
5 | The P1010 is a cost-effective, low-power, highly integrated host processor | |
6 | based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), | |
7 | that addresses the requirements of several routing, gateways, storage, consumer, | |
8 | and industrial applications. Applications of interest include the main CPUs and | |
9 | I/O processors in network attached storage (NAS), the voice over IP (VoIP) | |
10 | router/gateway, and wireless LAN (WLAN) and industrial controllers. | |
11 | ||
12 | The P1010RDB board features are as follows: | |
13 | Memory subsystem: | |
14 | - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) | |
15 | - 32 Mbyte NOR flash single-chip memory | |
16 | - 32 Mbyte NAND flash memory | |
17 | - 256 Kbit M24256 I2C EEPROM | |
18 | - 16 Mbyte SPI memory | |
19 | - I2C Board EEPROM 128x8 bit memory | |
20 | - SD/MMC connector to interface with the SD memory card | |
21 | Interfaces: | |
22 | - PCIe: | |
23 | - Lane0: x1 mini-PCIe slot | |
24 | - Lane1: x1 PCIe standard slot | |
25 | - SATA: | |
26 | - 1 internal SATA connector to 2.5" 160G SATA2 HDD | |
27 | - 1 eSATA connector to rear panel | |
28 | - 10/100/1000 BaseT Ethernet ports: | |
29 | - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO | |
30 | - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 | |
31 | - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 | |
32 | - USB 2.0 port: | |
33 | - x1 USB2.0 port: via an ULPI PHY to micro-AB connector | |
34 | - x1 USB2.0 poort via an internal PHY to micro-AB connector | |
35 | - FlexCAN ports: | |
36 | - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B) | |
37 | interface; | |
38 | - DUART interface: | |
39 | - DUART interface: supports two UARTs up to 115200 bps for | |
40 | console display | |
41 | - J45 connectors are used for these 2 UART ports. | |
42 | - TDM | |
43 | - 2 FXS ports connected via an external SLIC to the TDM | |
44 | interface. SLIC is controllled via SPI. | |
45 | - 1 FXO port connected via a relay to FXS for switchover to | |
46 | POTS | |
47 | Board connectors: | |
48 | - Mini-ITX power supply connector | |
49 | - JTAG/COP for debugging | |
50 | IEEE Std. 1588 signals for test and measurement | |
51 | Real-time clock on I2C bus | |
52 | POR | |
53 | - support critical POR setting changed via switch on board | |
54 | PCB | |
55 | - 6-layer routing (4-layer signals, 2-layer power and ground) | |
56 | ||
57 | ||
58 | Serial Port Configuration on P1010RDB | |
59 | ===================================== | |
60 | Configure the serial port of the attached computer with the following values: | |
61 | -Data rate: 115200 bps | |
62 | -Number of data bits: 8 | |
63 | -Parity: None | |
64 | -Number of Stop bits: 1 | |
65 | -Flow Control: Hardware/None | |
66 | ||
67 | ||
68 | Settings of DIP-switch | |
69 | ====================== | |
70 | SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash | |
71 | SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash | |
72 | SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash | |
73 | Note: 1 stands for 'on', 0 stands for 'off' | |
74 | ||
75 | ||
76 | Setting of hwconfig | |
77 | =================== | |
78 | If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or | |
79 | "fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: | |
80 | setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" | |
81 | By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection | |
82 | is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM | |
83 | instead of to CAN/UART1. | |
84 | ||
85 | ||
86 | Build and burn u-boot to NOR flash | |
87 | ================================== | |
88 | 1. Build u-boot.bin image | |
89 | export ARCH=powerpc | |
90 | export CROSS_COMPILE=/your_path/powerpc-linux-gnu- | |
91 | make P1010RDB_NOR | |
92 | ||
93 | 2. Burn u-boot.bin into NOR flash | |
94 | => tftp $loadaddr $uboot | |
95 | => protect off eff80000 +$filesize | |
96 | => erase eff80000 +$filesize | |
97 | => cp.b $loadaddr eff80000 $filesize | |
98 | ||
99 | 3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. | |
100 | ||
101 | ||
102 | Alternate NOR bank | |
103 | ============================ | |
104 | 1. Burn u-boot.bin into alternate NOR bank | |
105 | => tftp $loadaddr $uboot | |
106 | => protect off eef80000 +$filesize | |
107 | => erase eef80000 +$filesize | |
108 | => cp.b $loadaddr eef80000 $filesize | |
109 | ||
110 | 2. Switch to alternate NOR bank | |
111 | => mw.b ffb00009 1 | |
112 | => reset | |
113 | or set SW1[8]= ON | |
114 | ||
115 | SW1[8]= OFF: Upper bank used for booting start | |
116 | SW1[8]= ON: Lower bank used for booting start | |
117 | CPLD NOR bank selection register address 0xFFB00009 Bit[0]: | |
118 | 0 - boot from upper 4 sectors | |
119 | 1 - boot from lower 4 sectors | |
120 | ||
121 | ||
122 | Build and burn u-boot to NAND flash | |
123 | =================================== | |
124 | 1. Build u-boot.bin image | |
125 | export ARCH=powerpc | |
126 | export CROSS_COMPILE=/your_path/powerpc-linux-gnu- | |
127 | make P1010RDB_NAND | |
128 | ||
129 | 2. Burn u-boot-nand.bin into NAND flash | |
130 | => tftp $loadaddr $uboot-nand | |
131 | => nand erase 0 $filesize | |
132 | => nand write $loadaddr 0 $filesize | |
133 | ||
134 | 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. | |
135 | ||
136 | ||
137 | ||
138 | Build and burn u-boot to SPI flash | |
139 | ================================== | |
140 | 1. Build u-boot-spi.bin image | |
141 | make P1010RDB_SPIFLASH_config; make | |
142 | Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb | |
143 | Download u-boot.bin to linux and you can find some config files | |
144 | under /usr/share such as config_xx.dat. Do below command: | |
145 | boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ | |
146 | u-boot-spi.bin | |
147 | to generate u-boot-spi.bin. | |
148 | ||
149 | 2. Burn u-boot-spi.bin into SPI flash | |
150 | => tftp $loadaddr $uboot-spi | |
151 | => sf erase 0 100000 | |
152 | => sf write $loadaddr 0 $filesize | |
153 | ||
154 | 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. | |
155 | ||
156 | ||
157 | ||
158 | CPLD POR setting registers | |
159 | ========================== | |
160 | 1. Set POR switch selection register (addr 0xFFB00011) to 0. | |
161 | 2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with | |
162 | proper values. | |
163 | If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 | |
164 | switch command by I2C. | |
165 | 3. Send reset command. | |
166 | After reset, the new POR setting will be implemented. | |
167 | ||
168 | Two examples are given in below: | |
169 | Switch from NOR to NAND boot with default frequency: | |
170 | => i2c dev 0 | |
171 | => i2c mw 18 1 f9 | |
172 | => i2c mw 18 3 f0 | |
173 | => mw.b ffb00011 0 | |
174 | => mw.b ffb00017 1 | |
175 | => reset | |
176 | Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): | |
177 | => i2c dev 0 | |
178 | => i2c mw 18 1 f1 | |
179 | => i2c mw 18 3 f0 | |
180 | => mw.b ffb00011 0 | |
181 | => mw.b ffb00014 2 | |
182 | => mw.b ffb00015 5 | |
183 | => mw.b ffb00016 3 | |
184 | => mw.b ffb00017 f | |
185 | => reset | |
186 | ||
187 | ||
188 | ||
189 | Boot Linux from network using TFTP on P1010RDB | |
190 | ============================================== | |
191 | Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. | |
192 | => tftp 1000000 uImage | |
193 | => tftp 2000000 p1010rdb.dtb | |
194 | => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb | |
195 | => bootm 1000000 3000000 2000000 | |
196 | ||
197 | ||
198 | Please contact your local field applications engineer or sales representative | |
199 | to obtain related documents, such as P1010-RDB User Guide for details. |