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ee52b188 YS |
1 | Overview |
2 | -------- | |
3 | The T4240QDS is a high-performance computing evaluation, development and test | |
4 | platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is | |
5 | optimized to support the high-bandwidth DDR3 memory ports, as well as the | |
6 | highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. | |
7 | ||
8 | Board Features | |
9 | SERDES Connections | |
10 | 32 lanes grouped into four 8-lane banks | |
11 | Two “front side” banks dedicated to Ethernet | |
12 | - High-speed crosspoint switch fabric on selected lanes | |
13 | - Two PCI Express slots with side-band connector supporting | |
14 | - SGMII | |
15 | - XAUI | |
16 | - HiGig | |
17 | - I-pass connectors allow board-to-board and loopback support | |
18 | Two “back side” banks dedicated to other protocols | |
19 | - High-speed crosspoint switch fabric on all lanes | |
20 | - Four PCI Express slots with side-band connector supporting | |
21 | - PCI Express 3.0 | |
22 | - SATA 2.0 | |
23 | - SRIO 2.0 | |
24 | - Supports 4X Aurora debug with two connectors | |
25 | DDR Controllers | |
26 | Three independant 64-bit DDR3 controllers | |
27 | Supports rates of 1866 up to 2133 MHz data-rate | |
28 | Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller | |
29 | DDR power supplies 1.5V to all devices with automatic tracking of VTT. | |
30 | Power software-switchable to 1.35V if software detects all DDR3LP devices. | |
31 | MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and | |
32 | 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time | |
33 | increases by 1 clock. | |
34 | ||
35 | IFC/Local Bus | |
36 | NAND flash: 8-bit, async or sync, up to 2GB. | |
37 | NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB | |
38 | NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB | |
39 | - NOR devices support 16 virtual banks | |
40 | GASIC: Minimal target within Qixis FPGA | |
41 | PromJET rapid memory download support | |
42 | Address demultiplexing handled within FPGA. | |
43 | - Flexible demux allows 8 or 16 bit evaluation. | |
44 | IFC Debug/Development card | |
45 | - Support for 32-bit devices | |
46 | Ethernet | |
47 | Support two on-board RGMII 10/100/1G ethernet ports. | |
48 | SGMII and XAUI support via SERDES block (see above). | |
49 | 1588 support via Symmetricom board. | |
50 | QIXIS System Logic FPGA | |
51 | Manages system power and reset sequencing | |
52 | Manages DUT, board, clock, etc. configuration for dynamic shmoo | |
53 | Collects V-I-T data in background for code/power profiling. | |
54 | Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) | |
55 | General fault monitoring and logging | |
56 | Runs from ATX “hot” power rails allowing operation while system is off. | |
57 | Clocks | |
58 | System and DDR clock (SYSCLK, “DDRCLK”) | |
59 | - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. | |
60 | - Software selectable in 1MHz increments from 1-200MHz. | |
61 | SERDES clocks | |
62 | - Provides clocks to all SerDes blocks and slots | |
63 | - 100, 125 and 156.25 MHz | |
64 | Power Supplies | |
65 | Dedicated regulators for VDD | |
66 | - Adjustable from (0.7V to 1.3V at 80A | |
67 | - Regulators can be controlled by VID and/or software | |
68 | Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A | |
69 | - VTT/MVREF automatically track operating voltage | |
70 | Dedicated regulators/filters for AVDD supplies | |
71 | Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. | |
72 | USB | |
73 | Supports two USB 2.0 ports with integrated PHYs | |
74 | - One type A, one type micro-AB with 1.0A power per port. | |
75 | Other IO | |
76 | eSDHC/MMC | |
77 | - SDHC card slot | |
78 | eSPI port | |
79 | - High-speed serial flash | |
80 | Two Serial port | |
81 | Four I2C ports | |
82 | ||
83 | Memory map | |
84 | ---------- | |
85 | The addresses in brackets are physical addresses. | |
86 | ||
87 | 0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) | |
88 | 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory | |
49e946cb | 89 | 0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) |
ee52b188 YS |
90 | 0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan |
91 | 0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan | |
92 | 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO | |
93 | 0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash | |
94 | 0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR | |
95 | 0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS | |
96 | 0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores | |
97 | ||
98 | The physical address of the last (boot page translation) varies with the actual DDR size. | |
0aadf4aa YS |
99 | |
100 | Voltage ID and VDD override | |
101 | -------------------- | |
102 | T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage | |
103 | accordingly. The voltage can also be override by command vdd_override. The | |
104 | syntax is | |
105 | ||
106 | vdd_override <voltage in mV>, eg. 1050 is for 1.050v. | |
107 | ||
108 | Upon success, the actual voltage will be read back. The value is checked | |
109 | for safety and any invalid value will not adjust the voltage. | |
110 | ||
111 | Another way to override VDD is to use environmental variable, in case of using | |
112 | command is too late for some debugging. The syntax is | |
113 | ||
114 | setenv t4240qds_vdd_mv <voltage in mV> | |
115 | saveenv | |
116 | reset | |
117 | ||
118 | The override voltage takes effect when booting. | |
119 | ||
120 | Note: voltage adjustment needs to be done step by step. Changing voltage too | |
121 | rapidly may cause current surge. The voltage stepping is done by software. | |
122 | Users can set the final voltage directly. |