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Commit | Line | Data |
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7168da16 MY |
1 | U-Boot for UniPhier SoC family |
2 | ============================== | |
3 | ||
4 | ||
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5 | Recommended toolchains |
6 | ---------------------- | |
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8 | The UniPhir platform is well tested with Linaro toolchanis. |
9 | You can download pre-built toolchains from: | |
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10 | |
11 | http://www.linaro.org/downloads/ | |
12 | ||
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13 | |
14 | Compile the source | |
15 | ------------------ | |
16 | ||
52159d27 | 17 | sLD3 reference board: |
e90b3686 | 18 | $ make uniphier_sld3_defconfig |
12a5ce72 | 19 | $ make CROSS_COMPILE=arm-linux-gnueabihf- |
7168da16 | 20 | |
52159d27 | 21 | LD4 reference board: |
5fd3f434 | 22 | $ make uniphier_ld4_sld8_defconfig |
12a5ce72 | 23 | $ make CROSS_COMPILE=arm-linux-gnueabihf- |
7168da16 | 24 | |
52159d27 | 25 | sLD8 reference board: |
5fd3f434 | 26 | $ make uniphier_ld4_sld8_defconfig |
12a5ce72 | 27 | $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref |
5fd3f434 | 28 | |
52159d27 | 29 | Pro4 reference board: |
e90b3686 | 30 | $ make uniphier_pro4_defconfig |
12a5ce72 | 31 | $ make CROSS_COMPILE=arm-linux-gnueabihf- |
3365b4eb | 32 | |
52159d27 | 33 | Pro4 Ace board: |
c6c7eed7 | 34 | $ make uniphier_pro4_defconfig |
12a5ce72 | 35 | $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace |
c6c7eed7 | 36 | |
52159d27 | 37 | Pro4 Sanji board: |
c6c7eed7 | 38 | $ make uniphier_pro4_defconfig |
12a5ce72 | 39 | $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji |
c6c7eed7 | 40 | |
52159d27 | 41 | Pro5 4KBOX Board: |
fe7c95ee | 42 | $ make uniphier_pxs2_ld6b_defconfig |
12a5ce72 | 43 | $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox |
28f40d4a | 44 | |
52159d27 | 45 | PXs2 Gentil board: |
1a264534 | 46 | $ make uniphier_pxs2_ld6b_defconfig |
12a5ce72 | 47 | $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil |
019df879 | 48 | |
52159d27 | 49 | PXs2 Vodka board: |
1a264534 | 50 | $ make uniphier_pxs2_ld6b_defconfig |
12a5ce72 | 51 | $ make CROSS_COMPILE=arm-linux-gnueabihf- |
019df879 | 52 | |
52159d27 | 53 | LD6b reference board: |
1a264534 | 54 | $ make uniphier_pxs2_ld6b_defconfig |
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55 | $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref |
56 | ||
57 | LD11 reference board: | |
58 | $ make uniphier_ld11_defconfig | |
59 | $ make CROSS_COMPILE=aarch64-linux-gnu- | |
1a264534 | 60 | |
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61 | LD20 reference board: |
62 | $ make uniphier_ld20_defconfig | |
63 | $ make CROSS_COMPILE=aarch64-linux-gnu- | |
64 | ||
65 | You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler. | |
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66 | |
67 | ||
68 | Burn U-Boot images to NAND | |
69 | -------------------------- | |
70 | ||
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71 | Write the following to the NAND device: |
72 | ||
3cb9abc9 | 73 | - spl/u-boot-spl.bin at the offset address 0x00000000 |
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74 | - u-boot.bin at the offset address 0x00010000 |
75 | ||
76 | or | |
77 | ||
78 | - u-boot-with-spl.bin at the offset address 0x00000000 | |
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79 | |
80 | If a TFTP server is available, the images can be easily updated. | |
d085ecd6 | 81 | Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory, |
95a2d438 | 82 | and then run the following command at the U-Boot command line: |
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83 | |
84 | => run nandupdate | |
85 | ||
86 | ||
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87 | Burn U-Boot images to eMMC |
88 | -------------------------- | |
89 | ||
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90 | Write the following to the Boot partition 1 of the eMMC device: |
91 | ||
c231c436 | 92 | - spl/u-boot-spl.bin at the offset address 0x00000000 |
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93 | - u-boot.bin at the offset address 0x00010000 |
94 | ||
95 | or | |
96 | ||
97 | - u-boot-with-spl.bin at the offset address 0x00000000 | |
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98 | |
99 | If a TFTP server is available, the images can be easily updated. | |
d085ecd6 | 100 | Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory, |
95a2d438 | 101 | and then run the following command at the U-Boot command line: |
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102 | |
103 | => run emmcupdate | |
104 | ||
105 | ||
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106 | UniPhier specific commands |
107 | -------------------------- | |
108 | ||
109 | - pinmon (enabled by CONFIG_CMD_PINMON) | |
110 | shows the boot mode pins that has been latched at the power-on reset | |
111 | ||
112 | - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP) | |
113 | shows the DDR PHY parameters set by the PHY training | |
114 | ||
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115 | - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP) |
116 | shows the DDR Multi PHY parameters set by the PHY training | |
117 | ||
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118 | |
119 | Supported devices | |
120 | ----------------- | |
121 | ||
122 | - UART (on-chip) | |
123 | - NAND | |
a111bfbf | 124 | - SD/eMMC |
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125 | - USB 2.0 (EHCI) |
126 | - USB 3.0 (xHCI) | |
b9a66b63 | 127 | - GPIO |
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128 | - LAN (on-board SMSC9118) |
129 | - I2C | |
130 | - EEPROM (connected to the on-board I2C bus) | |
131 | - Support card (SRAM, NOR flash, some peripherals) | |
132 | ||
133 | ||
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134 | Micro Support Card |
135 | ------------------ | |
136 | ||
137 | The recommended bit switch settings are as follows: | |
138 | ||
139 | SW2 OFF(1)/ON(0) Description | |
140 | ------------------------------------------ | |
141 | bit 1 <---- BKSZ[0] | |
142 | bit 2 ----> BKSZ[1] | |
143 | bit 3 <---- SoC Bus Width 16/32 | |
144 | bit 4 <---- SERIAL_SEL[0] | |
145 | bit 5 ----> SERIAL_SEL[1] | |
146 | bit 6 ----> BOOTSWAP_EN | |
147 | bit 7 <---- CS1/CS5 | |
148 | bit 8 <---- SOC_SERIAL_DISABLE | |
149 | ||
150 | SW8 OFF(1)/ON(0) Description | |
151 | ------------------------------------------ | |
e69514cc | 152 | bit 1 <---- CS1_SPLIT |
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153 | bit 2 <---- CASE9_ON |
154 | bit 3 <---- CASE10_ON | |
155 | bit 4 Don't Care Reserve | |
156 | bit 5 Don't Care Reserve | |
157 | bit 6 Don't Care Reserve | |
158 | bit 7 ----> BURST_EN | |
159 | bit 8 ----> FLASHBUS32_16 | |
160 | ||
161 | The BKSZ[1:0] specifies the address range of memory slot and peripherals | |
162 | as follows: | |
163 | ||
164 | BKSZ Description RAM slot Peripherals | |
165 | -------------------------------------------------------------------- | |
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166 | 0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff |
167 | 0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff | |
168 | 0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff | |
169 | 0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff | |
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170 | |
171 | Set BSKZ[1:0] to 0b01 for U-Boot. | |
172 | This mode is the most handy because EA[24] is always supported by the save pin | |
173 | mode of the system bus. On the other hand, EA[25] is not supported for some | |
174 | newer SoCs. Even if it is, EA[25] is not connected on most of the boards. | |
175 | ||
7168da16 | 176 | -- |
62102bee | 177 | Masahiro Yamada <yamada.masahiro@socionext.com> |
12a5ce72 | 178 | Oct. 2016 |