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1 | # |
2 | # Copyright (C) 2014, Simon Glass <sjg@chromium.org> | |
3 | # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> | |
4 | # | |
5 | # SPDX-License-Identifier: GPL-2.0+ | |
6 | # | |
7 | ||
8 | U-Boot on x86 | |
9 | ============= | |
10 | ||
11 | This document describes the information about U-Boot running on x86 targets, | |
12 | including supported boards, build instructions, todo list, etc. | |
13 | ||
14 | Status | |
15 | ------ | |
16 | U-Boot supports running as a coreboot [1] payload on x86. So far only Link | |
17 | (Chromebook Pixel) has been tested, but it should work with minimal adjustments | |
18 | on other x86 boards since coreboot deals with most of the low-level details. | |
19 | ||
20 | U-Boot also supports booting directly from x86 reset vector without coreboot, | |
21 | aka raw support or bare support. Currently Link and Intel Crown Bay board | |
22 | support running U-Boot 'bare metal'. | |
23 | ||
24 | As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux | |
25 | kernel as part of a FIT image. It also supports a compressed zImage. | |
26 | ||
27 | Build Instructions | |
28 | ------------------ | |
29 | Building U-Boot as a coreboot payload is just like building U-Boot for targets | |
30 | on other architectures, like below: | |
31 | ||
32 | $ make coreboot-x86_defconfig | |
33 | $ make all | |
34 | ||
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35 | Note this default configuration will build a U-Boot payload for the Link board. |
36 | To build a coreboot payload against another board, you can change the build | |
37 | configuration during the 'make menuconfig' process. | |
38 | ||
39 | x86 architecture ---> | |
40 | ... | |
41 | (chromebook_link) Board configuration file | |
42 | (chromebook_link) Board Device Tree Source (dts) file | |
43 | (0x19200000) Board specific Cache-As-RAM (CAR) address | |
44 | (0x4000) Board specific Cache-As-RAM (CAR) size | |
45 | ||
46 | Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' | |
47 | to point to a new board. You can also change the Cache-As-RAM (CAR) related | |
48 | settings here if the default values do not fit your new board. | |
49 | ||
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50 | Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a |
51 | little bit tricky, as generally it requires several binary blobs which are not | |
52 | shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is | |
53 | not turned on by default in the U-Boot source tree. Firstly, you need turn it | |
54 | on by uncommenting the following line in the main U-Boot Makefile: | |
55 | ||
56 | # ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom | |
57 | ||
58 | Link-specific instructions: | |
59 | ||
60 | First, you need the following binary blobs: | |
61 | ||
62 | * descriptor.bin - Intel flash descriptor | |
63 | * me.bin - Intel Management Engine | |
64 | * mrc.bin - Memory Reference Code, which sets up SDRAM | |
65 | * video ROM - sets up the display | |
66 | ||
67 | You can get these binary blobs by: | |
68 | ||
69 | $ git clone http://review.coreboot.org/p/blobs.git | |
70 | $ cd blobs | |
71 | ||
72 | Find the following files: | |
73 | ||
74 | * ./mainboard/google/link/descriptor.bin | |
75 | * ./mainboard/google/link/me.bin | |
76 | * ./northbridge/intel/sandybridge/systemagent-ivybridge.bin | |
77 | ||
78 | The 3rd one should be renamed to mrc.bin. | |
79 | As for the video ROM, you can get it here [2]. | |
80 | Make sure all these binary blobs are put in the board directory. | |
81 | ||
82 | Now you can build U-Boot and obtain u-boot.rom: | |
83 | ||
84 | $ make chromebook_link_defconfig | |
85 | $ make all | |
86 | ||
87 | Intel Crown Bay specific instructions: | |
88 | ||
89 | U-Boot support of Intel Crown Bay board [3] relies on a binary blob called | |
90 | Firmware Support Package [4] to perform all the necessary initialization steps | |
91 | as documented in the BIOS Writer Guide, including initialization of the CPU, | |
92 | memory controller, chipset and certain bus interfaces. | |
93 | ||
94 | Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, | |
95 | install it on your host and locate the FSP binary blob. Note this platform | |
96 | also requires a Chipset Micro Code (CMC) state machine binary to be present in | |
97 | the SPI flash where u-boot.rom resides, and this CMC binary blob can be found | |
98 | in this FSP package too. | |
99 | ||
100 | * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd | |
101 | * ./Microcode/C0_22211.BIN | |
102 | ||
103 | Rename the first one to fsp.bin and second one to cmc.bin and put them in the | |
104 | board directory. | |
105 | ||
617b867f | 106 | Now you can build U-Boot and obtain u-boot.rom |
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107 | |
108 | $ make crownbay_defconfig | |
109 | $ make all | |
110 | ||
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111 | Test with coreboot |
112 | ------------------ | |
113 | For testing U-Boot as the coreboot payload, there are things that need be paid | |
114 | attention to. coreboot supports loading an ELF executable and a 32-bit plain | |
115 | binary, as well as other supported payloads. With the default configuration, | |
116 | U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the | |
117 | generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool | |
118 | provided by coreboot) manually as coreboot's 'make menuconfig' does not provide | |
119 | this capability yet. The command is as follows: | |
120 | ||
121 | # in the coreboot root directory | |
122 | $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ | |
123 | -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 | |
124 | ||
125 | Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the | |
126 | symbol address of _start (in arch/x86/cpu/start.S). | |
127 | ||
128 | If you want to use ELF as the coreboot payload, change U-Boot configuration to | |
129 | use CONFIG_OF_EMBED. | |
130 | ||
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131 | CPU Microcode |
132 | ------------- | |
133 | Modern CPU usually requires a special bit stream called microcode [5] to be | |
134 | loaded on the processor after power up in order to function properly. U-Boot | |
135 | has already integrated these as hex dumps in the source tree. | |
136 | ||
137 | Driver Model | |
138 | ------------ | |
139 | x86 has been converted to use driver model for serial and GPIO. | |
140 | ||
141 | Device Tree | |
142 | ----------- | |
143 | x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to | |
617b867f | 144 | be turned on. Not every device on the board is configured via device tree, but |
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145 | more and more devices will be added as time goes by. Check out the directory |
146 | arch/x86/dts/ for these device tree source files. | |
147 | ||
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148 | Useful Commands |
149 | --------------- | |
150 | ||
151 | In keeping with the U-Boot philosophy of providing functions to check and | |
152 | adjust internal settings, there are several x86-specific commands that may be | |
153 | useful: | |
154 | ||
155 | hob - Display information about Firmware Support Package (FSP) Hand-off | |
156 | Block. This is only available on platforms which use FSP, mostly | |
157 | Atom. | |
158 | iod - Display I/O memory | |
159 | iow - Write I/O memory | |
160 | mtrr - List and set the Memory Type Range Registers (MTRR). These are used to | |
161 | tell the CPU whether memory is cacheable and if so the cache write | |
162 | mode to use. U-Boot sets up some reasonable values but you can | |
163 | adjust then with this command. | |
164 | ||
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165 | TODO List |
166 | --------- | |
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167 | - Audio |
168 | - Chrome OS verified boot | |
169 | - SMI and ACPI support, to provide platform info and facilities to Linux | |
170 | ||
171 | References | |
172 | ---------- | |
173 | [1] http://www.coreboot.org | |
174 | [2] http://www.coreboot.org/~stepan/pci8086,0166.rom | |
175 | [3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html | |
176 | [4] http://www.intel.com/fsp | |
177 | [5] http://en.wikipedia.org/wiki/Microcode |