[people/ms/u-boot.git] / doc / SPI / README.dual-flash

SPI/QSPI Dual flash connection modes:
=====================================

This describes how SPI/QSPI flash memories are connected to a given
controller in a single chip select line.

Current spi_flash framework supports, single flash memory connected
to a given controller with single chip select line, but there are some
hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
connected with a single chip select line from a controller.

"dual_flash" from include/spi.h describes these types of connection mode

Possible connections:
--------------------
SF_SINGLE_FLASH:
       - single spi flash memory connected with single chip select line.

  +------------+             CS         +---------------+
  |            |----------------------->|               |
  | Controller |         I0[3:0]        | Flash memory  |
  | SPI/QSPI   |<======================>| (SPI/QSPI)    |
  |            |           CLK          |               |
  |            |----------------------->|               |
  +------------+                        +---------------+

SF_DUAL_STACKED_FLASH:
       - dual spi/qspi flash memories are connected with a single chipselect
         line and these two memories are operating stacked fasion with shared buses.
       - xilinx zynq qspi controller has implemented this feature [1]

  +------------+        CS             +---------------+
  |            |---------------------->|               |
  |            |              I0[3:0]  | Upper Flash   |
  |            |            +=========>| memory        |
  |            |            |     CLK  | (SPI/QSPI)    |
  |            |            |    +---->|               |
  | Controller |        CS  |    |     +---------------+
  | SPI/QSPI   |------------|----|---->|               |
  |            |    I0[3:0] |    |     | Lower Flash   |
  |            |<===========+====|====>| memory        |
  |            |          CLK    |     | (SPI/QSPI)    |
  |            |-----------------+---->|               |
  +------------+                       +---------------+

       - two memory flash devices should has same hw part attributes (like size,
         vendor..etc)
       - Configurations:
               on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
               Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
               Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
       - Operation:
               accessing memories serially like one after another.
               by default, if U_PAGE is unset lower memory should accessible,
               once user wants to access upper memory need to set U_PAGE.

SPI_FLASH_CONN_DUALPARALLEL:
	- dual spi/qspi flash memories are connected with a single chipselect
	  line and these two memories are operating parallel with separate buses.
	- xilinx zynq qspi controller has implemented this feature [1]

  +-------------+           CS		+---------------+
  |		|---------------------->|		|
  | 		|        I0[3:0]	| Upper Flash	|
  | 		|<=====================>| memory	|
  |		|	   CLK		| (SPI/QSPI)	|
  |		|---------------------->|		|
  | Controller	|	    CS		+---------------+
  | SPI/QSPI	|---------------------->|		|
  | 		|        I0[3:0]	| Lower Flash	|
  | 		|<=====================>| memory	|
  |		|	   CLK		| (SPI/QSPI)	|
  |		|---------------------->|		|
  +-------------+			+---------------+

	- two memory flash devices should has same hw part attributes (like size,
	  vendor..etc)
	- Configurations:
		Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
	- Operation:
		Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
		and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.

Note: Technically there is only one CS line from the controller, but
zynq qspi controller has an internal hw logic to enable additional CS
when controller is configured for dual memories.

[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

--
Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
05-01-2014.
Commit	Line	Data
f77f4691 JT	1	SPI/QSPI Dual flash connection modes:
	2	=====================================
	3
	4	This describes how SPI/QSPI flash memories are connected to a given
	5	controller in a single chip select line.
	6
	7	Current spi_flash framework supports, single flash memory connected
	8	to a given controller with single chip select line, but there are some
	9	hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
	10	connected with a single chip select line from a controller.
	11
	12	"dual_flash" from include/spi.h describes these types of connection mode
	13
	14	Possible connections:
	15	--------------------
	16	SF_SINGLE_FLASH:
	17	- single spi flash memory connected with single chip select line.
	18
	19	+------------+ CS +---------------+
	20	\| \|----------------------->\| \|
	21	\| Controller \| I0[3:0] \| Flash memory \|
	22	\| SPI/QSPI \|<======================>\| (SPI/QSPI) \|
	23	\| \| CLK \| \|
	24	\| \|----------------------->\| \|
	25	+------------+ +---------------+
	26
	27	SF_DUAL_STACKED_FLASH:
	28	- dual spi/qspi flash memories are connected with a single chipselect
	29	line and these two memories are operating stacked fasion with shared buses.
	30	- xilinx zynq qspi controller has implemented this feature [1]
	31
	32	+------------+ CS +---------------+
	33	\| \|---------------------->\| \|
	34	\| \| I0[3:0] \| Upper Flash \|
	35	\| \| +=========>\| memory \|
	36	\| \| \| CLK \| (SPI/QSPI) \|
	37	\| \| \| +---->\| \|
	38	\| Controller \| CS \| \| +---------------+
	39	\| SPI/QSPI \|------------\|----\|---->\| \|
	40	\| \| I0[3:0] \| \| \| Lower Flash \|
	41	\| \|<===========+====\|====>\| memory \|
	42	\| \| CLK \| \| (SPI/QSPI) \|
	43	\| \|-----------------+---->\| \|
	44	+------------+ +---------------+
	45
	46	- two memory flash devices should has same hw part attributes (like size,
	47	vendor..etc)
	48	- Configurations:
	49	on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
	50	Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
	51	Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
	52	- Operation:
	53	accessing memories serially like one after another.
	54	by default, if U_PAGE is unset lower memory should accessible,
	55	once user wants to access upper memory need to set U_PAGE.
	56
056fbc73 JT	57	SPI_FLASH_CONN_DUALPARALLEL:
	58	- dual spi/qspi flash memories are connected with a single chipselect
	59	line and these two memories are operating parallel with separate buses.
	60	- xilinx zynq qspi controller has implemented this feature [1]
	61
	62	+-------------+ CS +---------------+
	63	\| \|---------------------->\| \|
	64	\| \| I0[3:0] \| Upper Flash \|
	65	\| \|<=====================>\| memory \|
	66	\| \| CLK \| (SPI/QSPI) \|
	67	\| \|---------------------->\| \|
	68	\| Controller \| CS +---------------+
	69	\| SPI/QSPI \|---------------------->\| \|
	70	\| \| I0[3:0] \| Lower Flash \|
	71	\| \|<=====================>\| memory \|
	72	\| \| CLK \| (SPI/QSPI) \|
	73	\| \|---------------------->\| \|
	74	+-------------+ +---------------+
	75
	76	- two memory flash devices should has same hw part attributes (like size,
	77	vendor..etc)
	78	- Configurations:
	79	Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
	80	- Operation:
	81	Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
	82	and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
	83
f77f4691 JT	84	Note: Technically there is only one CS line from the controller, but
	85	zynq qspi controller has an internal hw logic to enable additional CS
	86	when controller is configured for dual memories.
	87
	88	[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
	89
	90	--
	91	Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
	92	05-01-2014.