]> git.ipfire.org Git - people/ms/linux.git/blame - drivers/ata/ahci.c
projects / people / ms / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
libata: implement and use SHT initializers
[people/ms/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
a22e6444
TH		 52static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
31556594
KCA		 56static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
1da177e4
LT		 59
60enum {
61 AHCI_PCI_BAR = 5,
648a88be 62 AHCI_MAX_PORTS = 32,
1da177e4
LT		 63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 65 AHCI_MAX_CMDS = 32,
dd410ff1 66 AHCI_CMD_SZ = 32,
12fad3f9 67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 68 AHCI_RX_FIS_SZ = 256,
a0ea7328 69 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
4b10e559 78 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 85
86 board_ahci = 0,
7a234aff
TH		 87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
e39fc8c9 91 board_ahci_sb700 = 5,
1da177e4
LT		 92
93 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */
95 HOST_CTL = 0x04, /* global host control */
96 HOST_IRQ_STAT = 0x08, /* interrupt status */
97 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
98 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
99
100 /* HOST_CTL bits */
101 HOST_RESET = (1 << 0), /* reset controller; self-clear */
102 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
103 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
104
105 /* HOST_CAP bits */
0be0aa98 106 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 107 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 108 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 109 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 110 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 114
115 /* registers for each SATA port */
116 PORT_LST_ADDR = 0x00, /* command list DMA addr */
117 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
118 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
119 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
120 PORT_IRQ_STAT = 0x10, /* interrupt status */
121 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
122 PORT_CMD = 0x18, /* port command */
123 PORT_TFDATA = 0x20, /* taskfile data */
124 PORT_SIG = 0x24, /* device TF signature */
125 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 126 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
127 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
128 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
129 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 130 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 131
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
135 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
137 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
141
142 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
144 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
145 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
151
78cd52d0
TH		 152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
153 PORT_IRQ_IF_ERR |
154 PORT_IRQ_CONNECT |
4296971d 155 PORT_IRQ_PHYRDY |
7d50b60b
TH		 156 PORT_IRQ_UNK_FIS |
157 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
159 PORT_IRQ_TF_ERR |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 164
165 /* PORT_CMD bits */
31556594
KCA		 166 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 168 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 169 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 170 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
171 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
172 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 173 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 174 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
175 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
176 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
177
0be0aa98 178 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 179 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
180 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
181 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 182
417a1a6d
TH		 183 /* hpriv->flags bits */
184 AHCI_HFLAG_NO_NCQ = (1 << 0),
185 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
186 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
187 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
188 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
189 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
417a1a6d 193
bf2af2a2 194 /* ap->flags bits */
1188c0d8
TH		 195
196 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
197 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 198 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
199 ATA_FLAG_IPM,
c4f7792c
TH		 200
201 ICH_MAP = 0x90, /* ICH MAP register */
1da177e4
LT		 202};
203
204struct ahci_cmd_hdr {
4ca4e439
AV		 205 __le32 opts;
206 __le32 status;
207 __le32 tbl_addr;
208 __le32 tbl_addr_hi;
209 __le32 reserved[4];
1da177e4
LT		 210};
211
212struct ahci_sg {
4ca4e439
AV		 213 __le32 addr;
214 __le32 addr_hi;
215 __le32 reserved;
216 __le32 flags_size;
1da177e4
LT		 217};
218
219struct ahci_host_priv {
417a1a6d 220 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 221 u32 cap; /* cap to use */
222 u32 port_map; /* port map to use */
223 u32 saved_cap; /* saved initial cap */
224 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 225};
226
227struct ahci_port_priv {
7d50b60b 228 struct ata_link *active_link;
1da177e4
LT		 229 struct ahci_cmd_hdr *cmd_slot;
230 dma_addr_t cmd_slot_dma;
231 void *cmd_tbl;
232 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 233 void *rx_fis;
234 dma_addr_t rx_fis_dma;
0291f95f 235 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 236 unsigned int ncq_saw_d2h:1;
237 unsigned int ncq_saw_dmas:1;
afb2d552 238 unsigned int ncq_saw_sdb:1;
a7384925 239 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 240};
241
da3dbb17
TH		 242static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
243static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 244static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 245static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4
LT		 246static int ahci_port_start(struct ata_port *ap);
247static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 248static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
249static void ahci_qc_prep(struct ata_queued_cmd *qc);
250static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 251static void ahci_freeze(struct ata_port *ap);
252static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 253static void ahci_pmp_attach(struct ata_port *ap);
254static void ahci_pmp_detach(struct ata_port *ap);
78cd52d0 255static void ahci_error_handler(struct ata_port *ap);
ad616ffb 256static void ahci_vt8251_error_handler(struct ata_port *ap);
edc93052 257static void ahci_p5wdh_error_handler(struct ata_port *ap);
78cd52d0 258static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 259static int ahci_port_resume(struct ata_port *ap);
a878539e 260static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 261static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
262static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
263 u32 opts);
438ac6d5 264#ifdef CONFIG_PM
c1332875 265static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 266static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
267static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 268#endif
1da177e4 269
31556594
KCA		 270static struct class_device_attribute *ahci_shost_attrs[] = {
271 &class_device_attr_link_power_management_policy,
272 NULL
273};
274
193515d5 275static struct scsi_host_template ahci_sht = {
68d1d07b 276 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 277 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 278 .sg_tablesize = AHCI_MAX_SG,
1da177e4 279 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 280 .shost_attrs = ahci_shost_attrs,
1da177e4
LT		 281};
282
057ace5e 283static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 284 .check_status = ahci_check_status,
285 .check_altstatus = ahci_check_status,
1da177e4
LT		 286 .dev_select = ata_noop_dev_select,
287
a878539e
JG		 288 .dev_config = ahci_dev_config,
289
1da177e4
LT		 290 .tf_read = ahci_tf_read,
291
7d50b60b 292 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 293 .qc_prep = ahci_qc_prep,
294 .qc_issue = ahci_qc_issue,
295
358f9a77 296 .irq_clear = ata_noop_irq_clear,
1da177e4
LT		 297
298 .scr_read = ahci_scr_read,
299 .scr_write = ahci_scr_write,
300
78cd52d0
TH		 301 .freeze = ahci_freeze,
302 .thaw = ahci_thaw,
303
304 .error_handler = ahci_error_handler,
305 .post_internal_cmd = ahci_post_internal_cmd,
306
7d50b60b
TH		 307 .pmp_attach = ahci_pmp_attach,
308 .pmp_detach = ahci_pmp_detach,
7d50b60b 309
438ac6d5 310#ifdef CONFIG_PM
c1332875
TH		 311 .port_suspend = ahci_port_suspend,
312 .port_resume = ahci_port_resume,
438ac6d5 313#endif
31556594
KCA		 314 .enable_pm = ahci_enable_alpm,
315 .disable_pm = ahci_disable_alpm,
c1332875 316
1da177e4
LT		 317 .port_start = ahci_port_start,
318 .port_stop = ahci_port_stop,
1da177e4
LT		 319};
320
ad616ffb 321static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 322 .check_status = ahci_check_status,
323 .check_altstatus = ahci_check_status,
324 .dev_select = ata_noop_dev_select,
325
6bd99b4e
TH		 326 .dev_config = ahci_dev_config,
327
ad616ffb
TH		 328 .tf_read = ahci_tf_read,
329
7d50b60b 330 .qc_defer = sata_pmp_qc_defer_cmd_switch,
ad616ffb
TH		 331 .qc_prep = ahci_qc_prep,
332 .qc_issue = ahci_qc_issue,
333
358f9a77 334 .irq_clear = ata_noop_irq_clear,
ad616ffb
TH		 335
336 .scr_read = ahci_scr_read,
337 .scr_write = ahci_scr_write,
338
339 .freeze = ahci_freeze,
340 .thaw = ahci_thaw,
341
342 .error_handler = ahci_vt8251_error_handler,
343 .post_internal_cmd = ahci_post_internal_cmd,
344
7d50b60b
TH		 345 .pmp_attach = ahci_pmp_attach,
346 .pmp_detach = ahci_pmp_detach,
7d50b60b 347
438ac6d5 348#ifdef CONFIG_PM
ad616ffb
TH		 349 .port_suspend = ahci_port_suspend,
350 .port_resume = ahci_port_resume,
438ac6d5 351#endif
6bd99b4e
TH		 352 .enable_pm = ahci_enable_alpm,
353 .disable_pm = ahci_disable_alpm,
ad616ffb
TH		 354
355 .port_start = ahci_port_start,
356 .port_stop = ahci_port_stop,
357};
358
edc93052
TH		 359static const struct ata_port_operations ahci_p5wdh_ops = {
360 .check_status = ahci_check_status,
361 .check_altstatus = ahci_check_status,
362 .dev_select = ata_noop_dev_select,
363
6bd99b4e
TH		 364 .dev_config = ahci_dev_config,
365
edc93052
TH		 366 .tf_read = ahci_tf_read,
367
368 .qc_defer = sata_pmp_qc_defer_cmd_switch,
369 .qc_prep = ahci_qc_prep,
370 .qc_issue = ahci_qc_issue,
371
358f9a77 372 .irq_clear = ata_noop_irq_clear,
edc93052
TH		 373
374 .scr_read = ahci_scr_read,
375 .scr_write = ahci_scr_write,
376
377 .freeze = ahci_freeze,
378 .thaw = ahci_thaw,
379
380 .error_handler = ahci_p5wdh_error_handler,
381 .post_internal_cmd = ahci_post_internal_cmd,
382
383 .pmp_attach = ahci_pmp_attach,
384 .pmp_detach = ahci_pmp_detach,
385
386#ifdef CONFIG_PM
387 .port_suspend = ahci_port_suspend,
388 .port_resume = ahci_port_resume,
389#endif
6bd99b4e
TH		 390 .enable_pm = ahci_enable_alpm,
391 .disable_pm = ahci_disable_alpm,
edc93052
TH		 392
393 .port_start = ahci_port_start,
394 .port_stop = ahci_port_stop,
395};
396
417a1a6d
TH		 397#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
398
98ac62de 399static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 400 /* board_ahci */
401 {
1188c0d8 402 .flags = AHCI_FLAG_COMMON,
7da79312 403 .pio_mask = 0x1f, /* pio0-4 */
469248ab 404 .udma_mask = ATA_UDMA6,
1da177e4
LT		 405 .port_ops = &ahci_ops,
406 },
bf2af2a2
BJ		 407 /* board_ahci_vt8251 */
408 {
6949b914 409 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 410 .flags = AHCI_FLAG_COMMON,
bf2af2a2 411 .pio_mask = 0x1f, /* pio0-4 */
469248ab 412 .udma_mask = ATA_UDMA6,
ad616ffb 413 .port_ops = &ahci_vt8251_ops,
bf2af2a2 414 },
41669553
TH		 415 /* board_ahci_ign_iferr */
416 {
417a1a6d
TH		 417 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
418 .flags = AHCI_FLAG_COMMON,
41669553 419 .pio_mask = 0x1f, /* pio0-4 */
469248ab 420 .udma_mask = ATA_UDMA6,
41669553
TH		 421 .port_ops = &ahci_ops,
422 },
55a61604
CH		 423 /* board_ahci_sb600 */
424 {
417a1a6d 425 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
4cde32fc 426 AHCI_HFLAG_32BIT_ONLY |
a878539e 427 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
417a1a6d 428 .flags = AHCI_FLAG_COMMON,
55a61604 429 .pio_mask = 0x1f, /* pio0-4 */
469248ab 430 .udma_mask = ATA_UDMA6,
55a61604
CH		 431 .port_ops = &ahci_ops,
432 },
cd70c266
JG		 433 /* board_ahci_mv */
434 {
417a1a6d
TH		 435 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
436 AHCI_HFLAG_MV_PATA),
cd70c266 437 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 438 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
cd70c266
JG		 439 .pio_mask = 0x1f, /* pio0-4 */
440 .udma_mask = ATA_UDMA6,
441 .port_ops = &ahci_ops,
442 },
e39fc8c9
SH		 443 /* board_ahci_sb700 */
444 {
445 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
446 AHCI_HFLAG_NO_PMP),
447 .flags = AHCI_FLAG_COMMON,
e39fc8c9
SH		 448 .pio_mask = 0x1f, /* pio0-4 */
449 .udma_mask = ATA_UDMA6,
450 .port_ops = &ahci_ops,
451 },
1da177e4
LT		 452};
453
3b7d697d 454static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 455 /* Intel */
54bb3a94
JG		 456 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
457 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
458 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
459 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
460 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 461 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 462 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
463 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
464 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
465 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 466 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
467 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
468 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
469 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
470 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
471 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
472 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
473 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
474 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
477 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
478 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
479 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
482 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 483 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
484 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 485 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
486 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
fe7fa31a 487
e34bb370
TH		 488 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
489 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
490 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 491
492 /* ATI */
c65ec1c2 493 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 494 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
495 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
496 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
497 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
498 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 500
501 /* VIA */
54bb3a94 502 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 503 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 504
505 /* NVIDIA */
54bb3a94
JG		 506 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
507 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
508 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
509 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 510 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
515 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
516 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 518 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
520 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 526 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 550 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 554 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
556 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
70d562cf 562 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
563 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
564 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
565 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
566 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
567 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
568 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
fe7fa31a 574
95916edd 575 /* SiS */
54bb3a94
JG		 576 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
577 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
578 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 579
cd70c266
JG		 580 /* Marvell */
581 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 582 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 583
415ae2b5
JG		 584 /* Generic, PCI class code for AHCI */
585 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 586 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 587
1da177e4
LT		 588 { } /* terminate list */
589};
590
591
592static struct pci_driver ahci_pci_driver = {
593 .name = DRV_NAME,
594 .id_table = ahci_pci_tbl,
595 .probe = ahci_init_one,
24dc5f33 596 .remove = ata_pci_remove_one,
438ac6d5 597#ifdef CONFIG_PM
c1332875
TH		 598 .suspend = ahci_pci_device_suspend,
599 .resume = ahci_pci_device_resume,
438ac6d5 600#endif
1da177e4
LT		 601};
602
603
98fa4b60
TH		 604static inline int ahci_nr_ports(u32 cap)
605{
606 return (cap & 0x1f) + 1;
607}
608
dab632e8
JG		 609static inline void __iomem *__ahci_port_base(struct ata_host *host,
610 unsigned int port_no)
1da177e4 611{
dab632e8 612 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 613
dab632e8
JG		 614 return mmio + 0x100 + (port_no * 0x80);
615}
616
617static inline void __iomem *ahci_port_base(struct ata_port *ap)
618{
619 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 620}
621
b710a1f4
TH		 622static void ahci_enable_ahci(void __iomem *mmio)
623{
624 u32 tmp;
625
626 /* turn on AHCI_EN */
627 tmp = readl(mmio + HOST_CTL);
628 if (!(tmp & HOST_AHCI_EN)) {
629 tmp |= HOST_AHCI_EN;
630 writel(tmp, mmio + HOST_CTL);
631 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
632 WARN_ON(!(tmp & HOST_AHCI_EN));
633 }
634}
635
d447df14
TH		 636/**
637 * ahci_save_initial_config - Save and fixup initial config values
4447d351 638 * @pdev: target PCI device
4447d351 639 * @hpriv: host private area to store config values
d447df14
TH		 640 *
641 * Some registers containing configuration info might be setup by
642 * BIOS and might be cleared on reset. This function saves the
643 * initial values of those registers into @hpriv such that they
644 * can be restored after controller reset.
645 *
646 * If inconsistent, config values are fixed up by this function.
647 *
648 * LOCKING:
649 * None.
650 */
4447d351 651static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 652 struct ahci_host_priv *hpriv)
d447df14 653{
4447d351 654 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 655 u32 cap, port_map;
17199b18 656 int i;
c40e7cb8 657 int mv;
d447df14 658
b710a1f4
TH		 659 /* make sure AHCI mode is enabled before accessing CAP */
660 ahci_enable_ahci(mmio);
661
d447df14
TH		 662 /* Values prefixed with saved_ are written back to host after
663 * reset. Values without are used for driver operation.
664 */
665 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
666 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
667
274c1fde 668 /* some chips have errata preventing 64bit use */
417a1a6d 669 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 670 dev_printk(KERN_INFO, &pdev->dev,
671 "controller can't do 64bit DMA, forcing 32bit\n");
672 cap &= ~HOST_CAP_64;
673 }
674
417a1a6d 675 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 676 dev_printk(KERN_INFO, &pdev->dev,
677 "controller can't do NCQ, turning off CAP_NCQ\n");
678 cap &= ~HOST_CAP_NCQ;
679 }
680
258cd846 681 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 682 dev_printk(KERN_INFO, &pdev->dev,
683 "controller can't do PMP, turning off CAP_PMP\n");
684 cap &= ~HOST_CAP_PMP;
685 }
686
cd70c266
JG		 687 /*
688 * Temporary Marvell 6145 hack: PATA port presence
689 * is asserted through the standard AHCI port
690 * presence register, as bit 4 (counting from 0)
691 */
417a1a6d 692 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 693 if (pdev->device == 0x6121)
694 mv = 0x3;
695 else
696 mv = 0xf;
cd70c266
JG		 697 dev_printk(KERN_ERR, &pdev->dev,
698 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 699 port_map,
700 port_map & mv);
cd70c266 701
c40e7cb8 702 port_map &= mv;
cd70c266
JG		 703 }
704
17199b18 705 /* cross check port_map and cap.n_ports */
7a234aff 706 if (port_map) {
837f5f8f 707 int map_ports = 0;
17199b18 708
837f5f8f
TH		 709 for (i = 0; i < AHCI_MAX_PORTS; i++)
710 if (port_map & (1 << i))
711 map_ports++;
17199b18 712
837f5f8f
TH		 713 /* If PI has more ports than n_ports, whine, clear
714 * port_map and let it be generated from n_ports.
17199b18 715 */
837f5f8f 716 if (map_ports > ahci_nr_ports(cap)) {
4447d351 717 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 718 "implemented port map (0x%x) contains more "
719 "ports than nr_ports (%u), using nr_ports\n",
720 port_map, ahci_nr_ports(cap));
7a234aff
TH		 721 port_map = 0;
722 }
723 }
724
725 /* fabricate port_map from cap.nr_ports */
726 if (!port_map) {
17199b18 727 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 728 dev_printk(KERN_WARNING, &pdev->dev,
729 "forcing PORTS_IMPL to 0x%x\n", port_map);
730
731 /* write the fixed up value to the PI register */
732 hpriv->saved_port_map = port_map;
17199b18
TH		 733 }
734
d447df14
TH		 735 /* record values to use during operation */
736 hpriv->cap = cap;
737 hpriv->port_map = port_map;
738}
739
740/**
741 * ahci_restore_initial_config - Restore initial config
4447d351 742 * @host: target ATA host
d447df14
TH		 743 *
744 * Restore initial config stored by ahci_save_initial_config().
745 *
746 * LOCKING:
747 * None.
748 */
4447d351 749static void ahci_restore_initial_config(struct ata_host *host)
d447df14 750{
4447d351
TH		 751 struct ahci_host_priv *hpriv = host->private_data;
752 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
753
d447df14
TH		 754 writel(hpriv->saved_cap, mmio + HOST_CAP);
755 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
756 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
757}
758
203ef6c4 759static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 760{
203ef6c4
TH		 761 static const int offset[] = {
762 [SCR_STATUS] = PORT_SCR_STAT,
763 [SCR_CONTROL] = PORT_SCR_CTL,
764 [SCR_ERROR] = PORT_SCR_ERR,
765 [SCR_ACTIVE] = PORT_SCR_ACT,
766 [SCR_NOTIFICATION] = PORT_SCR_NTF,
767 };
768 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 769
203ef6c4
TH		 770 if (sc_reg < ARRAY_SIZE(offset) &&
771 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
772 return offset[sc_reg];
da3dbb17 773 return 0;
1da177e4
LT		 774}
775
203ef6c4 776static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 777{
203ef6c4
TH		 778 void __iomem *port_mmio = ahci_port_base(ap);
779 int offset = ahci_scr_offset(ap, sc_reg);
780
781 if (offset) {
782 *val = readl(port_mmio + offset);
783 return 0;
1da177e4 784 }
203ef6c4
TH		 785 return -EINVAL;
786}
1da177e4 787
203ef6c4
TH		 788static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
789{
790 void __iomem *port_mmio = ahci_port_base(ap);
791 int offset = ahci_scr_offset(ap, sc_reg);
792
793 if (offset) {
794 writel(val, port_mmio + offset);
795 return 0;
796 }
797 return -EINVAL;
1da177e4
LT		 798}
799
4447d351 800static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 801{
4447d351 802 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 803 u32 tmp;
804
d8fcd116 805 /* start DMA */
9f592056 806 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 807 tmp |= PORT_CMD_START;
808 writel(tmp, port_mmio + PORT_CMD);
809 readl(port_mmio + PORT_CMD); /* flush */
810}
811
4447d351 812static int ahci_stop_engine(struct ata_port *ap)
254950cd 813{
4447d351 814 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 815 u32 tmp;
816
817 tmp = readl(port_mmio + PORT_CMD);
818
d8fcd116 819 /* check if the HBA is idle */
254950cd
TH		 820 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
821 return 0;
822
d8fcd116 823 /* setting HBA to idle */
254950cd
TH		 824 tmp &= ~PORT_CMD_START;
825 writel(tmp, port_mmio + PORT_CMD);
826
d8fcd116 827 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 828 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 829 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 830 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 831 return -EIO;
832
833 return 0;
834}
835
4447d351 836static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 837{
4447d351
TH		 838 void __iomem *port_mmio = ahci_port_base(ap);
839 struct ahci_host_priv *hpriv = ap->host->private_data;
840 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 841 u32 tmp;
842
843 /* set FIS registers */
4447d351
TH		 844 if (hpriv->cap & HOST_CAP_64)
845 writel((pp->cmd_slot_dma >> 16) >> 16,
846 port_mmio + PORT_LST_ADDR_HI);
847 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 848
4447d351
TH		 849 if (hpriv->cap & HOST_CAP_64)
850 writel((pp->rx_fis_dma >> 16) >> 16,
851 port_mmio + PORT_FIS_ADDR_HI);
852 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 853
854 /* enable FIS reception */
855 tmp = readl(port_mmio + PORT_CMD);
856 tmp |= PORT_CMD_FIS_RX;
857 writel(tmp, port_mmio + PORT_CMD);
858
859 /* flush */
860 readl(port_mmio + PORT_CMD);
861}
862
4447d351 863static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 864{
4447d351 865 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 866 u32 tmp;
867
868 /* disable FIS reception */
869 tmp = readl(port_mmio + PORT_CMD);
870 tmp &= ~PORT_CMD_FIS_RX;
871 writel(tmp, port_mmio + PORT_CMD);
872
873 /* wait for completion, spec says 500ms, give it 1000 */
874 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
875 PORT_CMD_FIS_ON, 10, 1000);
876 if (tmp & PORT_CMD_FIS_ON)
877 return -EBUSY;
878
879 return 0;
880}
881
4447d351 882static void ahci_power_up(struct ata_port *ap)
0be0aa98 883{
4447d351
TH		 884 struct ahci_host_priv *hpriv = ap->host->private_data;
885 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 886 u32 cmd;
887
888 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
889
890 /* spin up device */
4447d351 891 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 892 cmd |= PORT_CMD_SPIN_UP;
893 writel(cmd, port_mmio + PORT_CMD);
894 }
895
896 /* wake up link */
897 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
898}
899
31556594
KCA		 900static void ahci_disable_alpm(struct ata_port *ap)
901{
902 struct ahci_host_priv *hpriv = ap->host->private_data;
903 void __iomem *port_mmio = ahci_port_base(ap);
904 u32 cmd;
905 struct ahci_port_priv *pp = ap->private_data;
906
907 /* IPM bits should be disabled by libata-core */
908 /* get the existing command bits */
909 cmd = readl(port_mmio + PORT_CMD);
910
911 /* disable ALPM and ASP */
912 cmd &= ~PORT_CMD_ASP;
913 cmd &= ~PORT_CMD_ALPE;
914
915 /* force the interface back to active */
916 cmd |= PORT_CMD_ICC_ACTIVE;
917
918 /* write out new cmd value */
919 writel(cmd, port_mmio + PORT_CMD);
920 cmd = readl(port_mmio + PORT_CMD);
921
922 /* wait 10ms to be sure we've come out of any low power state */
923 msleep(10);
924
925 /* clear out any PhyRdy stuff from interrupt status */
926 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
927
928 /* go ahead and clean out PhyRdy Change from Serror too */
929 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
930
931 /*
932 * Clear flag to indicate that we should ignore all PhyRdy
933 * state changes
934 */
935 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
936
937 /*
938 * Enable interrupts on Phy Ready.
939 */
940 pp->intr_mask |= PORT_IRQ_PHYRDY;
941 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
942
943 /*
944 * don't change the link pm policy - we can be called
945 * just to turn of link pm temporarily
946 */
947}
948
949static int ahci_enable_alpm(struct ata_port *ap,
950 enum link_pm policy)
951{
952 struct ahci_host_priv *hpriv = ap->host->private_data;
953 void __iomem *port_mmio = ahci_port_base(ap);
954 u32 cmd;
955 struct ahci_port_priv *pp = ap->private_data;
956 u32 asp;
957
958 /* Make sure the host is capable of link power management */
959 if (!(hpriv->cap & HOST_CAP_ALPM))
960 return -EINVAL;
961
962 switch (policy) {
963 case MAX_PERFORMANCE:
964 case NOT_AVAILABLE:
965 /*
966 * if we came here with NOT_AVAILABLE,
967 * it just means this is the first time we
968 * have tried to enable - default to max performance,
969 * and let the user go to lower power modes on request.
970 */
971 ahci_disable_alpm(ap);
972 return 0;
973 case MIN_POWER:
974 /* configure HBA to enter SLUMBER */
975 asp = PORT_CMD_ASP;
976 break;
977 case MEDIUM_POWER:
978 /* configure HBA to enter PARTIAL */
979 asp = 0;
980 break;
981 default:
982 return -EINVAL;
983 }
984
985 /*
986 * Disable interrupts on Phy Ready. This keeps us from
987 * getting woken up due to spurious phy ready interrupts
988 * TBD - Hot plug should be done via polling now, is
989 * that even supported?
990 */
991 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
992 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
993
994 /*
995 * Set a flag to indicate that we should ignore all PhyRdy
996 * state changes since these can happen now whenever we
997 * change link state
998 */
999 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1000
1001 /* get the existing command bits */
1002 cmd = readl(port_mmio + PORT_CMD);
1003
1004 /*
1005 * Set ASP based on Policy
1006 */
1007 cmd |= asp;
1008
1009 /*
1010 * Setting this bit will instruct the HBA to aggressively
1011 * enter a lower power link state when it's appropriate and
1012 * based on the value set above for ASP
1013 */
1014 cmd |= PORT_CMD_ALPE;
1015
1016 /* write out new cmd value */
1017 writel(cmd, port_mmio + PORT_CMD);
1018 cmd = readl(port_mmio + PORT_CMD);
1019
1020 /* IPM bits should be set by libata-core */
1021 return 0;
1022}
1023
438ac6d5 1024#ifdef CONFIG_PM
4447d351 1025static void ahci_power_down(struct ata_port *ap)
0be0aa98 1026{
4447d351
TH		 1027 struct ahci_host_priv *hpriv = ap->host->private_data;
1028 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1029 u32 cmd, scontrol;
1030
4447d351 1031 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1032 return;
0be0aa98 1033
07c53dac
TH		 1034 /* put device into listen mode, first set PxSCTL.DET to 0 */
1035 scontrol = readl(port_mmio + PORT_SCR_CTL);
1036 scontrol &= ~0xf;
1037 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1038
07c53dac
TH		 1039 /* then set PxCMD.SUD to 0 */
1040 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1041 cmd &= ~PORT_CMD_SPIN_UP;
1042 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1043}
438ac6d5 1044#endif
0be0aa98 1045
df69c9c5 1046static void ahci_start_port(struct ata_port *ap)
0be0aa98 1047{
0be0aa98 1048 /* enable FIS reception */
4447d351 1049 ahci_start_fis_rx(ap);
0be0aa98
TH		 1050
1051 /* enable DMA */
4447d351 1052 ahci_start_engine(ap);
0be0aa98
TH		 1053}
1054
4447d351 1055static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1056{
1057 int rc;
1058
1059 /* disable DMA */
4447d351 1060 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1061 if (rc) {
1062 *emsg = "failed to stop engine";
1063 return rc;
1064 }
1065
1066 /* disable FIS reception */
4447d351 1067 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1068 if (rc) {
1069 *emsg = "failed stop FIS RX";
1070 return rc;
1071 }
1072
0be0aa98
TH		 1073 return 0;
1074}
1075
4447d351 1076static int ahci_reset_controller(struct ata_host *host)
d91542c1 1077{
4447d351 1078 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1079 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1080 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1081 u32 tmp;
d91542c1 1082
3cc3eb11
JG		 1083 /* we must be in AHCI mode, before using anything
1084 * AHCI-specific, such as HOST_RESET.
1085 */
b710a1f4 1086 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1087
1088 /* global controller reset */
a22e6444
TH		 1089 if (!ahci_skip_host_reset) {
1090 tmp = readl(mmio + HOST_CTL);
1091 if ((tmp & HOST_RESET) == 0) {
1092 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1093 readl(mmio + HOST_CTL); /* flush */
1094 }
d91542c1 1095
a22e6444
TH		 1096 /* reset must complete within 1 second, or
1097 * the hardware should be considered fried.
1098 */
1099 ssleep(1);
d91542c1 1100
a22e6444
TH		 1101 tmp = readl(mmio + HOST_CTL);
1102 if (tmp & HOST_RESET) {
1103 dev_printk(KERN_ERR, host->dev,
1104 "controller reset failed (0x%x)\n", tmp);
1105 return -EIO;
1106 }
d91542c1 1107
a22e6444
TH		 1108 /* turn on AHCI mode */
1109 ahci_enable_ahci(mmio);
98fa4b60 1110
a22e6444
TH		 1111 /* Some registers might be cleared on reset. Restore
1112 * initial values.
1113 */
1114 ahci_restore_initial_config(host);
1115 } else
1116 dev_printk(KERN_INFO, host->dev,
1117 "skipping global host reset\n");
d91542c1
TH		 1118
1119 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1120 u16 tmp16;
1121
1122 /* configure PCS */
1123 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1124 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1125 tmp16 |= hpriv->port_map;
1126 pci_write_config_word(pdev, 0x92, tmp16);
1127 }
d91542c1
TH		 1128 }
1129
1130 return 0;
1131}
1132
2bcd866b
JG		 1133static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1134 int port_no, void __iomem *mmio,
1135 void __iomem *port_mmio)
1136{
1137 const char *emsg = NULL;
1138 int rc;
1139 u32 tmp;
1140
1141 /* make sure port is not active */
1142 rc = ahci_deinit_port(ap, &emsg);
1143 if (rc)
1144 dev_printk(KERN_WARNING, &pdev->dev,
1145 "%s (%d)\n", emsg, rc);
1146
1147 /* clear SError */
1148 tmp = readl(port_mmio + PORT_SCR_ERR);
1149 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1150 writel(tmp, port_mmio + PORT_SCR_ERR);
1151
1152 /* clear port IRQ */
1153 tmp = readl(port_mmio + PORT_IRQ_STAT);
1154 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1155 if (tmp)
1156 writel(tmp, port_mmio + PORT_IRQ_STAT);
1157
1158 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1159}
1160
4447d351 1161static void ahci_init_controller(struct ata_host *host)
d91542c1 1162{
417a1a6d 1163 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1164 struct pci_dev *pdev = to_pci_dev(host->dev);
1165 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1166 int i;
cd70c266 1167 void __iomem *port_mmio;
d91542c1 1168 u32 tmp;
c40e7cb8 1169 int mv;
d91542c1 1170
417a1a6d 1171 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1172 if (pdev->device == 0x6121)
1173 mv = 2;
1174 else
1175 mv = 4;
1176 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1177
1178 writel(0, port_mmio + PORT_IRQ_MASK);
1179
1180 /* clear port IRQ */
1181 tmp = readl(port_mmio + PORT_IRQ_STAT);
1182 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1183 if (tmp)
1184 writel(tmp, port_mmio + PORT_IRQ_STAT);
1185 }
1186
4447d351
TH		 1187 for (i = 0; i < host->n_ports; i++) {
1188 struct ata_port *ap = host->ports[i];
d91542c1 1189
cd70c266 1190 port_mmio = ahci_port_base(ap);
4447d351 1191 if (ata_port_is_dummy(ap))
d91542c1 1192 continue;
d91542c1 1193
2bcd866b 1194 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1195 }
1196
1197 tmp = readl(mmio + HOST_CTL);
1198 VPRINTK("HOST_CTL 0x%x\n", tmp);
1199 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1200 tmp = readl(mmio + HOST_CTL);
1201 VPRINTK("HOST_CTL 0x%x\n", tmp);
1202}
1203
a878539e
JG		 1204static void ahci_dev_config(struct ata_device *dev)
1205{
1206 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1207
4cde32fc 1208 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1209 dev->max_sectors = 255;
4cde32fc
JG		 1210 ata_dev_printk(dev, KERN_INFO,
1211 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1212 }
a878539e
JG		 1213}
1214
422b7595 1215static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1216{
4447d351 1217 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1218 struct ata_taskfile tf;
422b7595
TH		 1219 u32 tmp;
1220
1221 tmp = readl(port_mmio + PORT_SIG);
1222 tf.lbah = (tmp >> 24) & 0xff;
1223 tf.lbam = (tmp >> 16) & 0xff;
1224 tf.lbal = (tmp >> 8) & 0xff;
1225 tf.nsect = (tmp) & 0xff;
1226
1227 return ata_dev_classify(&tf);
1228}
1229
12fad3f9
TH		 1230static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1231 u32 opts)
cc9278ed 1232{
12fad3f9
TH		 1233 dma_addr_t cmd_tbl_dma;
1234
1235 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1236
1237 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1238 pp->cmd_slot[tag].status = 0;
1239 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1240 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1241}
1242
d2e75dff 1243static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1244{
0d5ff566 1245 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 1246 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 1247 u32 tmp;
d2e75dff 1248 int busy, rc;
bf2af2a2 1249
d2e75dff
TH		 1250 /* do we need to kick the port? */
1251 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1252 if (!busy && !force_restart)
1253 return 0;
1254
1255 /* stop engine */
1256 rc = ahci_stop_engine(ap);
1257 if (rc)
1258 goto out_restart;
1259
1260 /* need to do CLO? */
1261 if (!busy) {
1262 rc = 0;
1263 goto out_restart;
1264 }
1265
1266 if (!(hpriv->cap & HOST_CAP_CLO)) {
1267 rc = -EOPNOTSUPP;
1268 goto out_restart;
1269 }
bf2af2a2 1270
d2e75dff 1271 /* perform CLO */
bf2af2a2
BJ		 1272 tmp = readl(port_mmio + PORT_CMD);
1273 tmp |= PORT_CMD_CLO;
1274 writel(tmp, port_mmio + PORT_CMD);
1275
d2e75dff 1276 rc = 0;
bf2af2a2
BJ		 1277 tmp = ata_wait_register(port_mmio + PORT_CMD,
1278 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1279 if (tmp & PORT_CMD_CLO)
d2e75dff 1280 rc = -EIO;
bf2af2a2 1281
d2e75dff
TH		 1282 /* restart engine */
1283 out_restart:
1284 ahci_start_engine(ap);
1285 return rc;
bf2af2a2
BJ		 1286}
1287
91c4a2e0
TH		 1288static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1289 struct ata_taskfile *tf, int is_cmd, u16 flags,
1290 unsigned long timeout_msec)
bf2af2a2 1291{
91c4a2e0 1292 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1293 struct ahci_port_priv *pp = ap->private_data;
4447d351 1294 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1295 u8 *fis = pp->cmd_tbl;
1296 u32 tmp;
1297
1298 /* prep the command */
1299 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1300 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1301
1302 /* issue & wait */
1303 writel(1, port_mmio + PORT_CMD_ISSUE);
1304
1305 if (timeout_msec) {
1306 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1307 1, timeout_msec);
1308 if (tmp & 0x1) {
1309 ahci_kick_engine(ap, 1);
1310 return -EBUSY;
1311 }
1312 } else
1313 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1314
1315 return 0;
1316}
1317
cc0680a5 1318static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1319 int pmp, unsigned long deadline)
91c4a2e0 1320{
cc0680a5 1321 struct ata_port *ap = link->ap;
4658f79b 1322 const char *reason = NULL;
2cbb79eb 1323 unsigned long now, msecs;
4658f79b 1324 struct ata_taskfile tf;
4658f79b
TH		 1325 int rc;
1326
1327 DPRINTK("ENTER\n");
1328
cc0680a5 1329 if (ata_link_offline(link)) {
c2a65852
TH		 1330 DPRINTK("PHY reports no device\n");
1331 *class = ATA_DEV_NONE;
1332 return 0;
1333 }
1334
4658f79b 1335 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1336 rc = ahci_kick_engine(ap, 1);
994056d7 1337 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1338 ata_link_printk(link, KERN_WARNING,
994056d7 1339 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1340
cc0680a5 1341 ata_tf_init(link->device, &tf);
4658f79b
TH		 1342
1343 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1344 msecs = 0;
1345 now = jiffies;
1346 if (time_after(now, deadline))
1347 msecs = jiffies_to_msecs(deadline - now);
1348
4658f79b 1349 tf.ctl |= ATA_SRST;
a9cf5e85 1350 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1351 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1352 rc = -EIO;
1353 reason = "1st FIS failed";
1354 goto fail;
1355 }
1356
1357 /* spec says at least 5us, but be generous and sleep for 1ms */
1358 msleep(1);
1359
1360 /* issue the second D2H Register FIS */
4658f79b 1361 tf.ctl &= ~ATA_SRST;
a9cf5e85 1362 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1363
88ff6eaf
TH		 1364 /* wait a while before checking status */
1365 ata_wait_after_reset(ap, deadline);
4658f79b 1366
9b89391c
TH		 1367 rc = ata_wait_ready(ap, deadline);
1368 /* link occupied, -ENODEV too is an error */
1369 if (rc) {
1370 reason = "device not ready";
1371 goto fail;
4658f79b 1372 }
9b89391c 1373 *class = ahci_dev_classify(ap);
4658f79b
TH		 1374
1375 DPRINTK("EXIT, class=%u\n", *class);
1376 return 0;
1377
4658f79b 1378 fail:
cc0680a5 1379 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1380 return rc;
1381}
1382
cc0680a5 1383static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1384 unsigned long deadline)
1385{
7d50b60b
TH		 1386 int pmp = 0;
1387
1388 if (link->ap->flags & ATA_FLAG_PMP)
1389 pmp = SATA_PMP_CTRL_PORT;
1390
1391 return ahci_do_softreset(link, class, pmp, deadline);
a9cf5e85
TH		 1392}
1393
cc0680a5 1394static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1395 unsigned long deadline)
422b7595 1396{
cc0680a5 1397 struct ata_port *ap = link->ap;
4296971d
TH		 1398 struct ahci_port_priv *pp = ap->private_data;
1399 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1400 struct ata_taskfile tf;
4bd00f6a
TH		 1401 int rc;
1402
1403 DPRINTK("ENTER\n");
1da177e4 1404
4447d351 1405 ahci_stop_engine(ap);
4296971d
TH		 1406
1407 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1408 ata_tf_init(link->device, &tf);
dfd7a3db 1409 tf.command = 0x80;
9977126c 1410 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1411
cc0680a5 1412 rc = sata_std_hardreset(link, class, deadline);
4296971d 1413
4447d351 1414 ahci_start_engine(ap);
1da177e4 1415
cc0680a5 1416 if (rc == 0 && ata_link_online(link))
4bd00f6a 1417 *class = ahci_dev_classify(ap);
7d50b60b 1418 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
4bd00f6a 1419 *class = ATA_DEV_NONE;
1da177e4 1420
4bd00f6a
TH		 1421 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1422 return rc;
1423}
1424
cc0680a5 1425static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1426 unsigned long deadline)
ad616ffb 1427{
cc0680a5 1428 struct ata_port *ap = link->ap;
da3dbb17 1429 u32 serror;
ad616ffb
TH		 1430 int rc;
1431
1432 DPRINTK("ENTER\n");
1433
4447d351 1434 ahci_stop_engine(ap);
ad616ffb 1435
cc0680a5 1436 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1437 deadline);
ad616ffb
TH		 1438
1439 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1440 ahci_scr_read(ap, SCR_ERROR, &serror);
1441 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1442
4447d351 1443 ahci_start_engine(ap);
ad616ffb
TH		 1444
1445 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1446
1447 /* vt8251 doesn't clear BSY on signature FIS reception,
1448 * request follow-up softreset.
1449 */
1450 return rc ?: -EAGAIN;
1451}
1452
edc93052
TH		 1453static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1454 unsigned long deadline)
1455{
1456 struct ata_port *ap = link->ap;
1457 struct ahci_port_priv *pp = ap->private_data;
1458 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1459 struct ata_taskfile tf;
1460 int rc;
1461
1462 ahci_stop_engine(ap);
1463
1464 /* clear D2H reception area to properly wait for D2H FIS */
1465 ata_tf_init(link->device, &tf);
1466 tf.command = 0x80;
1467 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1468
1469 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1470 deadline);
1471
1472 ahci_start_engine(ap);
1473
1474 if (rc || ata_link_offline(link))
1475 return rc;
1476
1477 /* spec mandates ">= 2ms" before checking status */
1478 msleep(150);
1479
1480 /* The pseudo configuration device on SIMG4726 attached to
1481 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1482 * hardreset if no device is attached to the first downstream
1483 * port && the pseudo device locks up on SRST w/ PMP==0. To
1484 * work around this, wait for !BSY only briefly. If BSY isn't
1485 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1486 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1487 *
1488 * Wait for two seconds. Devices attached to downstream port
1489 * which can't process the following IDENTIFY after this will
1490 * have to be reset again. For most cases, this should
1491 * suffice while making probing snappish enough.
1492 */
1493 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1494 if (rc)
1495 ahci_kick_engine(ap, 0);
1496
1497 return 0;
1498}
1499
cc0680a5 1500static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1501{
cc0680a5 1502 struct ata_port *ap = link->ap;
4447d351 1503 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1504 u32 new_tmp, tmp;
1505
cc0680a5 1506 ata_std_postreset(link, class);
02eaa666
JG		 1507
1508 /* Make sure port's ATAPI bit is set appropriately */
1509 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1510 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1511 new_tmp |= PORT_CMD_ATAPI;
1512 else
1513 new_tmp &= ~PORT_CMD_ATAPI;
1514 if (new_tmp != tmp) {
1515 writel(new_tmp, port_mmio + PORT_CMD);
1516 readl(port_mmio + PORT_CMD); /* flush */
1517 }
1da177e4
LT		 1518}
1519
7d50b60b
TH		 1520static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1521 unsigned long deadline)
1522{
1523 return ahci_do_softreset(link, class, link->pmp, deadline);
1524}
1525
1da177e4
LT		 1526static u8 ahci_check_status(struct ata_port *ap)
1527{
0d5ff566 1528 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1529
1530 return readl(mmio + PORT_TFDATA) & 0xFF;
1531}
1532
1da177e4
LT		 1533static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1534{
1535 struct ahci_port_priv *pp = ap->private_data;
1536 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1537
1538 ata_tf_from_fis(d2h_fis, tf);
1539}
1540
12fad3f9 1541static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1542{
cedc9a47 1543 struct scatterlist *sg;
ff2aeb1e
TH		 1544 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1545 unsigned int si;
1da177e4
LT		 1546
1547 VPRINTK("ENTER\n");
1548
1549 /*
1550 * Next, the S/G list.
1551 */
ff2aeb1e 1552 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1553 dma_addr_t addr = sg_dma_address(sg);
1554 u32 sg_len = sg_dma_len(sg);
1555
ff2aeb1e
TH		 1556 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1557 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1558 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1559 }
828d09de 1560
ff2aeb1e 1561 return si;
1da177e4
LT		 1562}
1563
1564static void ahci_qc_prep(struct ata_queued_cmd *qc)
1565{
a0ea7328
JG		 1566 struct ata_port *ap = qc->ap;
1567 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1568 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1569 void *cmd_tbl;
1da177e4
LT		 1570 u32 opts;
1571 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1572 unsigned int n_elem;
1da177e4 1573
1da177e4
LT		 1574 /*
1575 * Fill in command table information. First, the header,
1576 * a SATA Register - Host to Device command FIS.
1577 */
12fad3f9
TH		 1578 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1579
7d50b60b 1580 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1581 if (is_atapi) {
12fad3f9
TH		 1582 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1583 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1584 }
1da177e4 1585
cc9278ed
TH		 1586 n_elem = 0;
1587 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1588 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1589
cc9278ed
TH		 1590 /*
1591 * Fill in command slot information.
1592 */
7d50b60b 1593 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1594 if (qc->tf.flags & ATA_TFLAG_WRITE)
1595 opts |= AHCI_CMD_WRITE;
1596 if (is_atapi)
4b10e559 1597 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1598
12fad3f9 1599 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1600}
1601
78cd52d0 1602static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1603{
417a1a6d 1604 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1605 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1606 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1607 struct ata_link *link = NULL;
1608 struct ata_queued_cmd *active_qc;
1609 struct ata_eh_info *active_ehi;
78cd52d0 1610 u32 serror;
1da177e4 1611
7d50b60b
TH		 1612 /* determine active link */
1613 ata_port_for_each_link(link, ap)
1614 if (ata_link_active(link))
1615 break;
1616 if (!link)
1617 link = &ap->link;
1618
1619 active_qc = ata_qc_from_tag(ap, link->active_tag);
1620 active_ehi = &link->eh_info;
1621
1622 /* record irq stat */
1623 ata_ehi_clear_desc(host_ehi);
1624 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1625
78cd52d0 1626 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1627 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1628 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1629 host_ehi->serror |= serror;
78cd52d0 1630
41669553 1631 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1632 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1633 irq_stat &= ~PORT_IRQ_IF_ERR;
1634
55a61604 1635 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1636 /* If qc is active, charge it; otherwise, the active
1637 * link. There's no active qc on NCQ errors. It will
1638 * be determined by EH by reading log page 10h.
1639 */
1640 if (active_qc)
1641 active_qc->err_mask |= AC_ERR_DEV;
1642 else
1643 active_ehi->err_mask |= AC_ERR_DEV;
1644
417a1a6d 1645 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1646 host_ehi->serror &= ~SERR_INTERNAL;
1647 }
1648
1649 if (irq_stat & PORT_IRQ_UNK_FIS) {
1650 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1651
1652 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1653 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 1654 ata_ehi_push_desc(active_ehi,
1655 "unknown FIS %08x %08x %08x %08x" ,
1656 unk[0], unk[1], unk[2], unk[3]);
1657 }
1658
1659 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1660 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1661 active_ehi->action |= ATA_EH_RESET;
7d50b60b 1662 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1663 }
78cd52d0
TH		 1664
1665 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 1666 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 1667 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1668 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1669 }
1670
78cd52d0 1671 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 1672 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 1673 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1674 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1675 }
1da177e4 1676
78cd52d0 1677 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1678 ata_ehi_hotplugged(host_ehi);
1679 ata_ehi_push_desc(host_ehi, "%s",
1680 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1681 "connection status changed" : "PHY RDY changed");
1682 }
1683
78cd52d0 1684 /* okay, let's hand over to EH */
a72ec4ce 1685
78cd52d0
TH		 1686 if (irq_stat & PORT_IRQ_FREEZE)
1687 ata_port_freeze(ap);
1688 else
1689 ata_port_abort(ap);
1da177e4
LT		 1690}
1691
df69c9c5 1692static void ahci_port_intr(struct ata_port *ap)
1da177e4 1693{
4447d351 1694 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1695 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1696 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 1697 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 1698 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 1699 u32 status, qc_active;
459ad688 1700 int rc;
1da177e4
LT		 1701
1702 status = readl(port_mmio + PORT_IRQ_STAT);
1703 writel(status, port_mmio + PORT_IRQ_STAT);
1704
b06ce3e5
TH		 1705 /* ignore BAD_PMP while resetting */
1706 if (unlikely(resetting))
1707 status &= ~PORT_IRQ_BAD_PMP;
1708
31556594
KCA		 1709 /* If we are getting PhyRdy, this is
1710 * just a power state change, we should
1711 * clear out this, plus the PhyRdy/Comm
1712 * Wake bits from Serror
1713 */
1714 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1715 (status & PORT_IRQ_PHYRDY)) {
1716 status &= ~PORT_IRQ_PHYRDY;
1717 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1718 }
1719
78cd52d0
TH		 1720 if (unlikely(status & PORT_IRQ_ERROR)) {
1721 ahci_error_intr(ap, status);
1722 return;
1da177e4
LT		 1723 }
1724
2f294968 1725 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 1726 /* If SNotification is available, leave notification
1727 * handling to sata_async_notification(). If not,
1728 * emulate it by snooping SDB FIS RX area.
1729 *
1730 * Snooping FIS RX area is probably cheaper than
1731 * poking SNotification but some constrollers which
1732 * implement SNotification, ICH9 for example, don't
1733 * store AN SDB FIS into receive area.
2f294968 1734 */
5f226c6b 1735 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 1736 sata_async_notification(ap);
5f226c6b
TH		 1737 else {
1738 /* If the 'N' bit in word 0 of the FIS is set,
1739 * we just received asynchronous notification.
1740 * Tell libata about it.
1741 */
1742 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1743 u32 f0 = le32_to_cpu(f[0]);
1744
1745 if (f0 & (1 << 15))
1746 sata_async_notification(ap);
1747 }
2f294968
KCA		 1748 }
1749
7d50b60b
TH		 1750 /* pp->active_link is valid iff any command is in flight */
1751 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 1752 qc_active = readl(port_mmio + PORT_SCR_ACT);
1753 else
1754 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1755
1756 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
b06ce3e5 1757
459ad688
TH		 1758 /* while resetting, invalid completions are expected */
1759 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 1760 ehi->err_mask |= AC_ERR_HSM;
cf480626 1761 ehi->action |= ATA_EH_RESET;
12fad3f9 1762 ata_port_freeze(ap);
1da177e4 1763 }
1da177e4
LT		 1764}
1765
7d12e780 1766static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1767{
cca3974e 1768 struct ata_host *host = dev_instance;
1da177e4
LT		 1769 struct ahci_host_priv *hpriv;
1770 unsigned int i, handled = 0;
ea6ba10b 1771 void __iomem *mmio;
1da177e4
LT		 1772 u32 irq_stat, irq_ack = 0;
1773
1774 VPRINTK("ENTER\n");
1775
cca3974e 1776 hpriv = host->private_data;
0d5ff566 1777 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1778
1779 /* sigh. 0xffffffff is a valid return from h/w */
1780 irq_stat = readl(mmio + HOST_IRQ_STAT);
1781 irq_stat &= hpriv->port_map;
1782 if (!irq_stat)
1783 return IRQ_NONE;
1784
2dcb407e 1785 spin_lock(&host->lock);
1da177e4 1786
2dcb407e 1787 for (i = 0; i < host->n_ports; i++) {
1da177e4 1788 struct ata_port *ap;
1da177e4 1789
67846b30
JG		 1790 if (!(irq_stat & (1 << i)))
1791 continue;
1792
cca3974e 1793 ap = host->ports[i];
67846b30 1794 if (ap) {
df69c9c5 1795 ahci_port_intr(ap);
67846b30
JG		 1796 VPRINTK("port %u\n", i);
1797 } else {
1798 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1799 if (ata_ratelimit())
cca3974e 1800 dev_printk(KERN_WARNING, host->dev,
a9524a76 1801 "interrupt on disabled port %u\n", i);
1da177e4 1802 }
67846b30
JG		 1803
1804 irq_ack |= (1 << i);
1da177e4
LT		 1805 }
1806
1807 if (irq_ack) {
1808 writel(irq_ack, mmio + HOST_IRQ_STAT);
1809 handled = 1;
1810 }
1811
cca3974e 1812 spin_unlock(&host->lock);
1da177e4
LT		 1813
1814 VPRINTK("EXIT\n");
1815
1816 return IRQ_RETVAL(handled);
1817}
1818
9a3d9eb0 1819static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1820{
1821 struct ata_port *ap = qc->ap;
4447d351 1822 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 1823 struct ahci_port_priv *pp = ap->private_data;
1824
1825 /* Keep track of the currently active link. It will be used
1826 * in completion path to determine whether NCQ phase is in
1827 * progress.
1828 */
1829 pp->active_link = qc->dev->link;
1da177e4 1830
12fad3f9
TH		 1831 if (qc->tf.protocol == ATA_PROT_NCQ)
1832 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1833 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1834 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1835
1836 return 0;
1837}
1838
78cd52d0
TH		 1839static void ahci_freeze(struct ata_port *ap)
1840{
4447d351 1841 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1842
1843 /* turn IRQ off */
1844 writel(0, port_mmio + PORT_IRQ_MASK);
1845}
1846
1847static void ahci_thaw(struct ata_port *ap)
1848{
0d5ff566 1849 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1850 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1851 u32 tmp;
a7384925 1852 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1853
1854 /* clear IRQ */
1855 tmp = readl(port_mmio + PORT_IRQ_STAT);
1856 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1857 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 1858
1c954a4d
TH		 1859 /* turn IRQ back on */
1860 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1861}
1862
1863static void ahci_error_handler(struct ata_port *ap)
1864{
b51e9e5d 1865 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1866 /* restart engine */
4447d351
TH		 1867 ahci_stop_engine(ap);
1868 ahci_start_engine(ap);
78cd52d0
TH		 1869 }
1870
1871 /* perform recovery */
7d50b60b
TH		 1872 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1873 ahci_hardreset, ahci_postreset,
1874 sata_pmp_std_prereset, ahci_pmp_softreset,
1875 sata_pmp_std_hardreset, sata_pmp_std_postreset);
78cd52d0
TH		 1876}
1877
ad616ffb
TH		 1878static void ahci_vt8251_error_handler(struct ata_port *ap)
1879{
ad616ffb
TH		 1880 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1881 /* restart engine */
4447d351
TH		 1882 ahci_stop_engine(ap);
1883 ahci_start_engine(ap);
ad616ffb
TH		 1884 }
1885
1886 /* perform recovery */
1887 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1888 ahci_postreset);
1889}
1890
edc93052
TH		 1891static void ahci_p5wdh_error_handler(struct ata_port *ap)
1892{
1893 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1894 /* restart engine */
1895 ahci_stop_engine(ap);
1896 ahci_start_engine(ap);
1897 }
1898
1899 /* perform recovery */
1900 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1901 ahci_postreset);
1902}
1903
78cd52d0
TH		 1904static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1905{
1906 struct ata_port *ap = qc->ap;
1907
d2e75dff
TH		 1908 /* make DMA engine forget about the failed command */
1909 if (qc->flags & ATA_QCFLAG_FAILED)
1910 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1911}
1912
7d50b60b
TH		 1913static void ahci_pmp_attach(struct ata_port *ap)
1914{
1915 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1916 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1917 u32 cmd;
1918
1919 cmd = readl(port_mmio + PORT_CMD);
1920 cmd |= PORT_CMD_PMP;
1921 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1922
1923 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1924 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1925}
1926
1927static void ahci_pmp_detach(struct ata_port *ap)
1928{
1929 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1930 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1931 u32 cmd;
1932
1933 cmd = readl(port_mmio + PORT_CMD);
1934 cmd &= ~PORT_CMD_PMP;
1935 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1936
1937 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1938 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1939}
1940
028a2596
AD		 1941static int ahci_port_resume(struct ata_port *ap)
1942{
1943 ahci_power_up(ap);
1944 ahci_start_port(ap);
1945
7d50b60b
TH		 1946 if (ap->nr_pmp_links)
1947 ahci_pmp_attach(ap);
1948 else
1949 ahci_pmp_detach(ap);
1950
028a2596
AD		 1951 return 0;
1952}
1953
438ac6d5 1954#ifdef CONFIG_PM
c1332875
TH		 1955static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1956{
c1332875
TH		 1957 const char *emsg = NULL;
1958 int rc;
1959
4447d351 1960 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1961 if (rc == 0)
4447d351 1962 ahci_power_down(ap);
8e16f941 1963 else {
c1332875 1964 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1965 ahci_start_port(ap);
c1332875
TH		 1966 }
1967
1968 return rc;
1969}
1970
c1332875
TH		 1971static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1972{
cca3974e 1973 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1974 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1975 u32 ctl;
1976
3a2d5b70 1977 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 1978 /* AHCI spec rev1.1 section 8.3.3:
1979 * Software must disable interrupts prior to requesting a
1980 * transition of the HBA to D3 state.
1981 */
1982 ctl = readl(mmio + HOST_CTL);
1983 ctl &= ~HOST_IRQ_EN;
1984 writel(ctl, mmio + HOST_CTL);
1985 readl(mmio + HOST_CTL); /* flush */
1986 }
1987
1988 return ata_pci_device_suspend(pdev, mesg);
1989}
1990
1991static int ahci_pci_device_resume(struct pci_dev *pdev)
1992{
cca3974e 1993 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 1994 int rc;
1995
553c4aa6
TH		 1996 rc = ata_pci_device_do_resume(pdev);
1997 if (rc)
1998 return rc;
c1332875
TH		 1999
2000 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2001 rc = ahci_reset_controller(host);
c1332875
TH		 2002 if (rc)
2003 return rc;
2004
4447d351 2005 ahci_init_controller(host);
c1332875
TH		 2006 }
2007
cca3974e 2008 ata_host_resume(host);
c1332875
TH		 2009
2010 return 0;
2011}
438ac6d5 2012#endif
c1332875 2013
254950cd
TH		 2014static int ahci_port_start(struct ata_port *ap)
2015{
cca3974e 2016 struct device *dev = ap->host->dev;
254950cd 2017 struct ahci_port_priv *pp;
254950cd
TH		 2018 void *mem;
2019 dma_addr_t mem_dma;
254950cd 2020
24dc5f33 2021 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2022 if (!pp)
2023 return -ENOMEM;
254950cd 2024
24dc5f33
TH		 2025 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2026 GFP_KERNEL);
2027 if (!mem)
254950cd 2028 return -ENOMEM;
254950cd
TH		 2029 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2030
2031 /*
2032 * First item in chunk of DMA memory: 32-slot command table,
2033 * 32 bytes each in size
2034 */
2035 pp->cmd_slot = mem;
2036 pp->cmd_slot_dma = mem_dma;
2037
2038 mem += AHCI_CMD_SLOT_SZ;
2039 mem_dma += AHCI_CMD_SLOT_SZ;
2040
2041 /*
2042 * Second item: Received-FIS area
2043 */
2044 pp->rx_fis = mem;
2045 pp->rx_fis_dma = mem_dma;
2046
2047 mem += AHCI_RX_FIS_SZ;
2048 mem_dma += AHCI_RX_FIS_SZ;
2049
2050 /*
2051 * Third item: data area for storing a single command
2052 * and its scatter-gather table
2053 */
2054 pp->cmd_tbl = mem;
2055 pp->cmd_tbl_dma = mem_dma;
2056
a7384925 2057 /*
2dcb407e
JG		 2058 * Save off initial list of interrupts to be enabled.
2059 * This could be changed later
2060 */
a7384925
KCA		 2061 pp->intr_mask = DEF_PORT_IRQ;
2062
254950cd
TH		 2063 ap->private_data = pp;
2064
df69c9c5
JG		 2065 /* engage engines, captain */
2066 return ahci_port_resume(ap);
254950cd
TH		 2067}
2068
2069static void ahci_port_stop(struct ata_port *ap)
2070{
0be0aa98
TH		 2071 const char *emsg = NULL;
2072 int rc;
254950cd 2073
0be0aa98 2074 /* de-initialize port */
4447d351 2075 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2076 if (rc)
2077 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2078}
2079
4447d351 2080static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2081{
1da177e4 2082 int rc;
1da177e4 2083
1da177e4
LT		 2084 if (using_dac &&
2085 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2086 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2087 if (rc) {
2088 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2089 if (rc) {
a9524a76
JG		 2090 dev_printk(KERN_ERR, &pdev->dev,
2091 "64-bit DMA enable failed\n");
1da177e4
LT		 2092 return rc;
2093 }
2094 }
1da177e4
LT		 2095 } else {
2096 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2097 if (rc) {
a9524a76
JG		 2098 dev_printk(KERN_ERR, &pdev->dev,
2099 "32-bit DMA enable failed\n");
1da177e4
LT		 2100 return rc;
2101 }
2102 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2103 if (rc) {
a9524a76
JG		 2104 dev_printk(KERN_ERR, &pdev->dev,
2105 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2106 return rc;
2107 }
2108 }
1da177e4
LT		 2109 return 0;
2110}
2111
4447d351 2112static void ahci_print_info(struct ata_host *host)
1da177e4 2113{
4447d351
TH		 2114 struct ahci_host_priv *hpriv = host->private_data;
2115 struct pci_dev *pdev = to_pci_dev(host->dev);
2116 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2117 u32 vers, cap, impl, speed;
2118 const char *speed_s;
2119 u16 cc;
2120 const char *scc_s;
2121
2122 vers = readl(mmio + HOST_VERSION);
2123 cap = hpriv->cap;
2124 impl = hpriv->port_map;
2125
2126 speed = (cap >> 20) & 0xf;
2127 if (speed == 1)
2128 speed_s = "1.5";
2129 else if (speed == 2)
2130 speed_s = "3";
2131 else
2132 speed_s = "?";
2133
2134 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2135 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2136 scc_s = "IDE";
c9f89475 2137 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2138 scc_s = "SATA";
c9f89475 2139 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2140 scc_s = "RAID";
2141 else
2142 scc_s = "unknown";
2143
a9524a76
JG		 2144 dev_printk(KERN_INFO, &pdev->dev,
2145 "AHCI %02x%02x.%02x%02x "
1da177e4 2146 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2147 ,
1da177e4 2148
2dcb407e
JG		 2149 (vers >> 24) & 0xff,
2150 (vers >> 16) & 0xff,
2151 (vers >> 8) & 0xff,
2152 vers & 0xff,
1da177e4
LT		 2153
2154 ((cap >> 8) & 0x1f) + 1,
2155 (cap & 0x1f) + 1,
2156 speed_s,
2157 impl,
2158 scc_s);
2159
a9524a76
JG		 2160 dev_printk(KERN_INFO, &pdev->dev,
2161 "flags: "
203ef6c4
TH		 2162 "%s%s%s%s%s%s%s"
2163 "%s%s%s%s%s%s%s\n"
2dcb407e 2164 ,
1da177e4
LT		 2165
2166 cap & (1 << 31) ? "64bit " : "",
2167 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2168 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2169 cap & (1 << 28) ? "ilck " : "",
2170 cap & (1 << 27) ? "stag " : "",
2171 cap & (1 << 26) ? "pm " : "",
2172 cap & (1 << 25) ? "led " : "",
2173
2174 cap & (1 << 24) ? "clo " : "",
2175 cap & (1 << 19) ? "nz " : "",
2176 cap & (1 << 18) ? "only " : "",
2177 cap & (1 << 17) ? "pmp " : "",
2178 cap & (1 << 15) ? "pio " : "",
2179 cap & (1 << 14) ? "slum " : "",
2180 cap & (1 << 13) ? "part " : ""
2181 );
2182}
2183
edc93052
TH		 2184/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2185 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2186 * support PMP and the 4726 either directly exports the device
2187 * attached to the first downstream port or acts as a hardware storage
2188 * controller and emulate a single ATA device (can be RAID 0/1 or some
2189 * other configuration).
2190 *
2191 * When there's no device attached to the first downstream port of the
2192 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2193 * configure the 4726. However, ATA emulation of the device is very
2194 * lame. It doesn't send signature D2H Reg FIS after the initial
2195 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2196 *
2197 * The following function works around the problem by always using
2198 * hardreset on the port and not depending on receiving signature FIS
2199 * afterward. If signature FIS isn't received soon, ATA class is
2200 * assumed without follow-up softreset.
2201 */
2202static void ahci_p5wdh_workaround(struct ata_host *host)
2203{
2204 static struct dmi_system_id sysids[] = {
2205 {
2206 .ident = "P5W DH Deluxe",
2207 .matches = {
2208 DMI_MATCH(DMI_SYS_VENDOR,
2209 "ASUSTEK COMPUTER INC"),
2210 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2211 },
2212 },
2213 { }
2214 };
2215 struct pci_dev *pdev = to_pci_dev(host->dev);
2216
2217 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2218 dmi_check_system(sysids)) {
2219 struct ata_port *ap = host->ports[1];
2220
2221 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2222 "Deluxe on-board SIMG4726 workaround\n");
2223
2224 ap->ops = &ahci_p5wdh_ops;
2225 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2226 }
2227}
2228
24dc5f33 2229static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2230{
2231 static int printed_version;
4447d351
TH		 2232 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2233 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2234 struct device *dev = &pdev->dev;
1da177e4 2235 struct ahci_host_priv *hpriv;
4447d351 2236 struct ata_host *host;
837f5f8f 2237 int n_ports, i, rc;
1da177e4
LT		 2238
2239 VPRINTK("ENTER\n");
2240
12fad3f9
TH		 2241 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2242
1da177e4 2243 if (!printed_version++)
a9524a76 2244 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2245
4447d351 2246 /* acquire resources */
24dc5f33 2247 rc = pcim_enable_device(pdev);
1da177e4
LT		 2248 if (rc)
2249 return rc;
2250
dea55137
TH		 2251 /* AHCI controllers often implement SFF compatible interface.
2252 * Grab all PCI BARs just in case.
2253 */
2254 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2255 if (rc == -EBUSY)
24dc5f33 2256 pcim_pin_device(pdev);
0d5ff566 2257 if (rc)
24dc5f33 2258 return rc;
1da177e4 2259
c4f7792c
TH		 2260 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2261 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2262 u8 map;
2263
2264 /* ICH6s share the same PCI ID for both piix and ahci
2265 * modes. Enabling ahci mode while MAP indicates
2266 * combined mode is a bad idea. Yield to ata_piix.
2267 */
2268 pci_read_config_byte(pdev, ICH_MAP, &map);
2269 if (map & 0x3) {
2270 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2271 "combined mode, can't enable AHCI mode\n");
2272 return -ENODEV;
2273 }
2274 }
2275
24dc5f33
TH		 2276 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2277 if (!hpriv)
2278 return -ENOMEM;
417a1a6d
TH		 2279 hpriv->flags |= (unsigned long)pi.private_data;
2280
2281 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2282 pci_intx(pdev, 1);
1da177e4 2283
4447d351 2284 /* save initial config */
417a1a6d 2285 ahci_save_initial_config(pdev, hpriv);
1da177e4 2286
4447d351 2287 /* prepare host */
274c1fde 2288 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2289 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2290
7d50b60b
TH		 2291 if (hpriv->cap & HOST_CAP_PMP)
2292 pi.flags |= ATA_FLAG_PMP;
2293
837f5f8f
TH		 2294 /* CAP.NP sometimes indicate the index of the last enabled
2295 * port, at other times, that of the last possible port, so
2296 * determining the maximum port number requires looking at
2297 * both CAP.NP and port_map.
2298 */
2299 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2300
2301 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2302 if (!host)
2303 return -ENOMEM;
2304 host->iomap = pcim_iomap_table(pdev);
2305 host->private_data = hpriv;
2306
2307 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 2308 struct ata_port *ap = host->ports[i];
2309 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 2310
cbcdd875
TH		 2311 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2312 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2313 0x100 + ap->port_no * 0x80, "port");
2314
31556594
KCA		 2315 /* set initial link pm policy */
2316 ap->pm_policy = NOT_AVAILABLE;
2317
dab632e8 2318 /* standard SATA port setup */
203ef6c4 2319 if (hpriv->port_map & (1 << i))
4447d351 2320 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 2321
2322 /* disabled/not-implemented port */
2323 else
2324 ap->ops = &ata_dummy_port_ops;
4447d351 2325 }
d447df14 2326
edc93052
TH		 2327 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2328 ahci_p5wdh_workaround(host);
2329
4447d351
TH		 2330 /* initialize adapter */
2331 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2332 if (rc)
24dc5f33 2333 return rc;
1da177e4 2334
4447d351
TH		 2335 rc = ahci_reset_controller(host);
2336 if (rc)
2337 return rc;
1da177e4 2338
4447d351
TH		 2339 ahci_init_controller(host);
2340 ahci_print_info(host);
1da177e4 2341
4447d351
TH		 2342 pci_set_master(pdev);
2343 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2344 &ahci_sht);
907f4678 2345}
1da177e4
LT		 2346
2347static int __init ahci_init(void)
2348{
b7887196 2349 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2350}
2351
1da177e4
LT		 2352static void __exit ahci_exit(void)
2353{
2354 pci_unregister_driver(&ahci_pci_driver);
2355}
2356
2357
2358MODULE_AUTHOR("Jeff Garzik");
2359MODULE_DESCRIPTION("AHCI SATA low-level driver");
2360MODULE_LICENSE("GPL");
2361MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2362MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2363
2364module_init(ahci_init);
2365module_exit(ahci_exit);
Michael's Linux tree.