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[people/ms/linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
66a7cbc3 63 board_ahci_nomsi,
67809f85 64 board_ahci_noncq,
441577ef 65 board_ahci_nosntf,
5f173107 66 board_ahci_yes_fbs,
1da177e4 67
441577ef
TH		 68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
83f2b963
TH		 70 board_ahci_mcp77,
71 board_ahci_mcp89,
441577ef
TH		 72 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 81 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 82};
83
2dcb407e 84static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 85static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
cb85696d
JL		 87static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 89static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
438ac6d5 91#ifdef CONFIG_PM
c1332875
TH		 92static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 94#endif
ad616ffb 95
fad16e7a
TH		 96static struct scsi_host_template ahci_sht = {
97 AHCI_SHT("ahci"),
98};
99
029cfd6b
TH		 100static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
a1efdaba 102 .hardreset = ahci_vt8251_hardreset,
029cfd6b 103};
edc93052 104
029cfd6b
TH		 105static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
a1efdaba 107 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 108};
109
98ac62de 110static const struct ata_port_info ahci_port_info[] = {
441577ef 111 /* by features */
facb8fa6 112 [board_ahci] = {
1188c0d8 113 .flags = AHCI_FLAG_COMMON,
14bdef98 114 .pio_mask = ATA_PIO4,
469248ab 115 .udma_mask = ATA_UDMA6,
1da177e4
LT		 116 .port_ops = &ahci_ops,
117 },
facb8fa6 118 [board_ahci_ign_iferr] = {
441577ef 119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 120 .flags = AHCI_FLAG_COMMON,
14bdef98 121 .pio_mask = ATA_PIO4,
469248ab 122 .udma_mask = ATA_UDMA6,
441577ef 123 .port_ops = &ahci_ops,
bf2af2a2 124 },
66a7cbc3
TH		 125 [board_ahci_nomsi] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
67809f85
LK		 132 [board_ahci_noncq] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
facb8fa6 139 [board_ahci_nosntf] = {
441577ef 140 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 141 .flags = AHCI_FLAG_COMMON,
14bdef98 142 .pio_mask = ATA_PIO4,
469248ab 143 .udma_mask = ATA_UDMA6,
41669553
TH		 144 .port_ops = &ahci_ops,
145 },
facb8fa6 146 [board_ahci_yes_fbs] = {
5f173107
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
441577ef 153 /* by chipsets */
facb8fa6 154 [board_ahci_mcp65] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 AHCI_HFLAG_YES_NCQ),
ae01b249 157 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
facb8fa6 162 [board_ahci_mcp77] = {
83f2b963
TH		 163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
facb8fa6 169 [board_ahci_mcp89] = {
83f2b963 170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
469248ab 173 .udma_mask = ATA_UDMA6,
441577ef 174 .port_ops = &ahci_ops,
55a61604 175 },
facb8fa6 176 [board_ahci_mv] = {
417a1a6d 177 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 178 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 180 .pio_mask = ATA_PIO4,
cd70c266
JG		 181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
facb8fa6 184 [board_ahci_sb600] = {
441577ef
TH		 185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 188 .flags = AHCI_FLAG_COMMON,
14bdef98 189 .pio_mask = ATA_PIO4,
e39fc8c9 190 .udma_mask = ATA_UDMA6,
345347c5 191 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 192 },
facb8fa6 193 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 194 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
345347c5 198 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 199 },
facb8fa6 200 [board_ahci_vt8251] = {
441577ef 201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
441577ef 205 .port_ops = &ahci_vt8251_ops,
1b677afd 206 },
1da177e4
LT		 207};
208
3b7d697d 209static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 210 /* Intel */
54bb3a94
JG		 211 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 216 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 217 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 221 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 222 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 223 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 238 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 240 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 241 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 242 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 243 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 245 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 246 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 247 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 248 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 249 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 250 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 251 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 257 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 260 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 261 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 262 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 268 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 269 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 277 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 285 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 311 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 312 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 316 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
249cd0a1
DR		 324 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
325 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
690000b9 327 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
690000b9
JR		 328 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
329 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
330 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
fe7fa31a 331
e34bb370
TH		 332 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
333 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
334 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 335 /* JMicron 362B and 362C have an AHCI function with IDE class code */
336 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
337 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 338
339 /* ATI */
c65ec1c2 340 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 341 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
346 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 347
e2dd90b1 348 /* AMD */
5deab536 349 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 350 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 351 /* AMD is using RAID class only for ahci controllers */
352 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
353 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
354
fe7fa31a 355 /* VIA */
54bb3a94 356 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 357 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 358
359 /* NVIDIA */
e297d99e
TH		 360 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 368 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
380 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
432 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
443 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 444
95916edd 445 /* SiS */
20e2de4a
TH		 446 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
447 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
448 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 449
318893e1
AR		 450 /* ST Microelectronics */
451 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
452
cd70c266
JG		 453 /* Marvell */
454 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 455 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 457 .class = PCI_CLASS_STORAGE_SATA_AHCI,
458 .class_mask = 0xffffff,
5f173107 459 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 461 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 462 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
463 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
464 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 465 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 466 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35 467 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
c5edfff9
MK		 468 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
469 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
fcce9a35 470 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 472 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
474 .driver_data = board_ahci_yes_fbs },
69fd3157 475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 476 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 477 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
478 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 479 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
480 .driver_data = board_ahci_yes_fbs },
cd70c266 481
c77a036b
MN		 482 /* Promise */
483 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 484 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 485
c9703765 486 /* Asmedia */
7b4f6eca
AC		 487 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
488 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
489 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
490 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 491
67809f85 492 /*
66a7cbc3
TH		 493 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
494 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
67809f85 495 */
66a7cbc3 496 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
2b21ef0a 497 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
67809f85 498
7f9c9f8e
HD		 499 /* Enmotus */
500 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
501
415ae2b5
JG		 502 /* Generic, PCI class code for AHCI */
503 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 504 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 505
1da177e4
LT		 506 { } /* terminate list */
507};
508
509
510static struct pci_driver ahci_pci_driver = {
511 .name = DRV_NAME,
512 .id_table = ahci_pci_tbl,
513 .probe = ahci_init_one,
24dc5f33 514 .remove = ata_pci_remove_one,
438ac6d5 515#ifdef CONFIG_PM
c1332875 516 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 517 .resume = ahci_pci_device_resume,
518#endif
519};
1da177e4 520
365cfa1e
AV		 521#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
522static int marvell_enable;
523#else
524static int marvell_enable = 1;
525#endif
526module_param(marvell_enable, int, 0644);
527MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 528
1da177e4 529
365cfa1e
AV		 530static void ahci_pci_save_initial_config(struct pci_dev *pdev,
531 struct ahci_host_priv *hpriv)
532{
365cfa1e
AV		 533 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
534 dev_info(&pdev->dev, "JMB361 has only one port\n");
9a23c1d6 535 hpriv->force_port_map = 1;
1da177e4
LT		 536 }
537
365cfa1e
AV		 538 /*
539 * Temporary Marvell 6145 hack: PATA port presence
540 * is asserted through the standard AHCI port
541 * presence register, as bit 4 (counting from 0)
d28f87aa 542 */
365cfa1e
AV		 543 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
544 if (pdev->device == 0x6121)
9a23c1d6 545 hpriv->mask_port_map = 0x3;
365cfa1e 546 else
9a23c1d6 547 hpriv->mask_port_map = 0xf;
365cfa1e
AV		 548 dev_info(&pdev->dev,
549 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
550 }
1da177e4 551
725c7b57 552 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 553}
554
365cfa1e 555static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 556{
365cfa1e 557 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 558
365cfa1e 559 ahci_reset_controller(host);
1da177e4 560
365cfa1e
AV		 561 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
562 struct ahci_host_priv *hpriv = host->private_data;
563 u16 tmp16;
d6ef3153 564
365cfa1e
AV		 565 /* configure PCS */
566 pci_read_config_word(pdev, 0x92, &tmp16);
567 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
568 tmp16 |= hpriv->port_map;
569 pci_write_config_word(pdev, 0x92, tmp16);
570 }
d6ef3153
SH		 571 }
572
1da177e4
LT		 573 return 0;
574}
575
365cfa1e 576static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 577{
365cfa1e
AV		 578 struct ahci_host_priv *hpriv = host->private_data;
579 struct pci_dev *pdev = to_pci_dev(host->dev);
580 void __iomem *port_mmio;
78cd52d0 581 u32 tmp;
365cfa1e 582 int mv;
78cd52d0 583
365cfa1e
AV		 584 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
585 if (pdev->device == 0x6121)
586 mv = 2;
587 else
588 mv = 4;
589 port_mmio = __ahci_port_base(host, mv);
78cd52d0 590
365cfa1e 591 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 592
365cfa1e
AV		 593 /* clear port IRQ */
594 tmp = readl(port_mmio + PORT_IRQ_STAT);
595 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
596 if (tmp)
597 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 598 }
599
365cfa1e 600 ahci_init_controller(host);
edc93052
TH		 601}
602
365cfa1e
AV		 603static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
604 unsigned long deadline)
d6ef3153 605{
365cfa1e 606 struct ata_port *ap = link->ap;
039ece38 607 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 608 bool online;
d6ef3153
SH		 609 int rc;
610
365cfa1e 611 DPRINTK("ENTER\n");
d6ef3153 612
365cfa1e 613 ahci_stop_engine(ap);
d6ef3153 614
365cfa1e
AV		 615 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
616 deadline, &online, NULL);
d6ef3153 617
039ece38 618 hpriv->start_engine(ap);
d6ef3153 619
365cfa1e 620 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 621
365cfa1e
AV		 622 /* vt8251 doesn't clear BSY on signature FIS reception,
623 * request follow-up softreset.
624 */
625 return online ? -EAGAIN : rc;
7d50b60b
TH		 626}
627
365cfa1e
AV		 628static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
629 unsigned long deadline)
7d50b60b 630{
365cfa1e 631 struct ata_port *ap = link->ap;
1c954a4d 632 struct ahci_port_priv *pp = ap->private_data;
039ece38 633 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 634 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
635 struct ata_taskfile tf;
636 bool online;
637 int rc;
7d50b60b 638
365cfa1e 639 ahci_stop_engine(ap);
028a2596 640
365cfa1e
AV		 641 /* clear D2H reception area to properly wait for D2H FIS */
642 ata_tf_init(link->device, &tf);
9bbb1b0e 643 tf.command = ATA_BUSY;
365cfa1e 644 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 645
365cfa1e
AV		 646 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
647 deadline, &online, NULL);
028a2596 648
039ece38 649 hpriv->start_engine(ap);
c1332875 650
365cfa1e
AV		 651 /* The pseudo configuration device on SIMG4726 attached to
652 * ASUS P5W-DH Deluxe doesn't send signature FIS after
653 * hardreset if no device is attached to the first downstream
654 * port && the pseudo device locks up on SRST w/ PMP==0. To
655 * work around this, wait for !BSY only briefly. If BSY isn't
656 * cleared, perform CLO and proceed to IDENTIFY (achieved by
657 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
658 *
659 * Wait for two seconds. Devices attached to downstream port
660 * which can't process the following IDENTIFY after this will
661 * have to be reset again. For most cases, this should
662 * suffice while making probing snappish enough.
663 */
664 if (online) {
665 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
666 ahci_check_ready);
667 if (rc)
668 ahci_kick_engine(ap);
c1332875 669 }
c1332875
TH		 670 return rc;
671}
672
365cfa1e 673#ifdef CONFIG_PM
c1332875
TH		 674static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
675{
0a86e1c8 676 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 677 struct ahci_host_priv *hpriv = host->private_data;
d8993349 678 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 679 u32 ctl;
680
9b10ae86
TH		 681 if (mesg.event & PM_EVENT_SUSPEND &&
682 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 683 dev_err(&pdev->dev,
684 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 685 return -EIO;
686 }
687
3a2d5b70 688 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 689 /* AHCI spec rev1.1 section 8.3.3:
690 * Software must disable interrupts prior to requesting a
691 * transition of the HBA to D3 state.
692 */
693 ctl = readl(mmio + HOST_CTL);
694 ctl &= ~HOST_IRQ_EN;
695 writel(ctl, mmio + HOST_CTL);
696 readl(mmio + HOST_CTL); /* flush */
697 }
698
699 return ata_pci_device_suspend(pdev, mesg);
700}
701
702static int ahci_pci_device_resume(struct pci_dev *pdev)
703{
0a86e1c8 704 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 705 int rc;
706
553c4aa6
TH		 707 rc = ata_pci_device_do_resume(pdev);
708 if (rc)
709 return rc;
c1332875 710
cb85696d
JL		 711 /* Apple BIOS helpfully mangles the registers on resume */
712 if (is_mcp89_apple(pdev))
713 ahci_mcp89_apple_enable(pdev);
714
c1332875 715 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 716 rc = ahci_pci_reset_controller(host);
c1332875
TH		 717 if (rc)
718 return rc;
719
781d6550 720 ahci_pci_init_controller(host);
c1332875
TH		 721 }
722
cca3974e 723 ata_host_resume(host);
c1332875
TH		 724
725 return 0;
726}
438ac6d5 727#endif
c1332875 728
4447d351 729static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 730{
1da177e4 731 int rc;
1da177e4 732
318893e1
AR		 733 /*
734 * If the device fixup already set the dma_mask to some non-standard
735 * value, don't extend it here. This happens on STA2X11, for example.
736 */
737 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
738 return 0;
739
1da177e4 740 if (using_dac &&
c54c719b
QL		 741 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
742 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1da177e4 743 if (rc) {
c54c719b 744 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 745 if (rc) {
a44fec1f
JP		 746 dev_err(&pdev->dev,
747 "64-bit DMA enable failed\n");
1da177e4
LT		 748 return rc;
749 }
750 }
1da177e4 751 } else {
c54c719b 752 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 753 if (rc) {
a44fec1f 754 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 755 return rc;
756 }
c54c719b 757 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1da177e4 758 if (rc) {
a44fec1f
JP		 759 dev_err(&pdev->dev,
760 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 761 return rc;
762 }
763 }
1da177e4
LT		 764 return 0;
765}
766
439fcaec
AV		 767static void ahci_pci_print_info(struct ata_host *host)
768{
769 struct pci_dev *pdev = to_pci_dev(host->dev);
770 u16 cc;
771 const char *scc_s;
772
773 pci_read_config_word(pdev, 0x0a, &cc);
774 if (cc == PCI_CLASS_STORAGE_IDE)
775 scc_s = "IDE";
776 else if (cc == PCI_CLASS_STORAGE_SATA)
777 scc_s = "SATA";
778 else if (cc == PCI_CLASS_STORAGE_RAID)
779 scc_s = "RAID";
780 else
781 scc_s = "unknown";
782
783 ahci_print_info(host, scc_s);
784}
785
edc93052
TH		 786/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
787 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
788 * support PMP and the 4726 either directly exports the device
789 * attached to the first downstream port or acts as a hardware storage
790 * controller and emulate a single ATA device (can be RAID 0/1 or some
791 * other configuration).
792 *
793 * When there's no device attached to the first downstream port of the
794 * 4726, "Config Disk" appears, which is a pseudo ATA device to
795 * configure the 4726. However, ATA emulation of the device is very
796 * lame. It doesn't send signature D2H Reg FIS after the initial
797 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
798 *
799 * The following function works around the problem by always using
800 * hardreset on the port and not depending on receiving signature FIS
801 * afterward. If signature FIS isn't received soon, ATA class is
802 * assumed without follow-up softreset.
803 */
804static void ahci_p5wdh_workaround(struct ata_host *host)
805{
1bd06867 806 static const struct dmi_system_id sysids[] = {
edc93052
TH		 807 {
808 .ident = "P5W DH Deluxe",
809 .matches = {
810 DMI_MATCH(DMI_SYS_VENDOR,
811 "ASUSTEK COMPUTER INC"),
812 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
813 },
814 },
815 { }
816 };
817 struct pci_dev *pdev = to_pci_dev(host->dev);
818
819 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
820 dmi_check_system(sysids)) {
821 struct ata_port *ap = host->ports[1];
822
a44fec1f
JP		 823 dev_info(&pdev->dev,
824 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 825
826 ap->ops = &ahci_p5wdh_ops;
827 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
828 }
829}
830
cb85696d
JL		 831/*
832 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
833 * booting in BIOS compatibility mode. We restore the registers but not ID.
834 */
835static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
836{
837 u32 val;
838
839 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
840
841 pci_read_config_dword(pdev, 0xf8, &val);
842 val |= 1 << 0x1b;
843 /* the following changes the device ID, but appears not to affect function */
844 /* val = (val & ~0xf0000000) | 0x80000000; */
845 pci_write_config_dword(pdev, 0xf8, val);
846
847 pci_read_config_dword(pdev, 0x54c, &val);
848 val |= 1 << 0xc;
849 pci_write_config_dword(pdev, 0x54c, val);
850
851 pci_read_config_dword(pdev, 0x4a4, &val);
852 val &= 0xff;
853 val |= 0x01060100;
854 pci_write_config_dword(pdev, 0x4a4, val);
855
856 pci_read_config_dword(pdev, 0x54c, &val);
857 val &= ~(1 << 0xc);
858 pci_write_config_dword(pdev, 0x54c, val);
859
860 pci_read_config_dword(pdev, 0xf8, &val);
861 val &= ~(1 << 0x1b);
862 pci_write_config_dword(pdev, 0xf8, val);
863}
864
865static bool is_mcp89_apple(struct pci_dev *pdev)
866{
867 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
868 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
869 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
870 pdev->subsystem_device == 0xcb89;
871}
872
2fcad9d2
TH		 873/* only some SB600 ahci controllers can do 64bit DMA */
874static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 875{
876 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 877 /*
878 * The oldest version known to be broken is 0901 and
879 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 880 * Enable 64bit DMA on 1501 and anything newer.
881 *
03d783bf
TH		 882 * Please read bko#9412 for more info.
883 */
58a09b38
SH		 884 {
885 .ident = "ASUS M2A-VM",
886 .matches = {
887 DMI_MATCH(DMI_BOARD_VENDOR,
888 "ASUSTeK Computer INC."),
889 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
890 },
03d783bf 891 .driver_data = "20071026", /* yyyymmdd */
58a09b38 892 },
e65cc194
MN		 893 /*
894 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
895 * support 64bit DMA.
896 *
897 * BIOS versions earlier than 1.5 had the Manufacturer DMI
898 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
899 * This spelling mistake was fixed in BIOS version 1.5, so
900 * 1.5 and later have the Manufacturer as
901 * "MICRO-STAR INTERNATIONAL CO.,LTD".
902 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
903 *
904 * BIOS versions earlier than 1.9 had a Board Product Name
905 * DMI field of "MS-7376". This was changed to be
906 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
907 * match on DMI_BOARD_NAME of "MS-7376".
908 */
909 {
910 .ident = "MSI K9A2 Platinum",
911 .matches = {
912 DMI_MATCH(DMI_BOARD_VENDOR,
913 "MICRO-STAR INTER"),
914 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
915 },
916 },
ff0173c1
MN		 917 /*
918 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
919 * 64bit DMA.
920 *
921 * This board also had the typo mentioned above in the
922 * Manufacturer DMI field (fixed in BIOS version 1.5), so
923 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
924 */
925 {
926 .ident = "MSI K9AGM2",
927 .matches = {
928 DMI_MATCH(DMI_BOARD_VENDOR,
929 "MICRO-STAR INTER"),
930 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
931 },
932 },
3c4aa91f
MN		 933 /*
934 * All BIOS versions for the Asus M3A support 64bit DMA.
935 * (all release versions from 0301 to 1206 were tested)
936 */
937 {
938 .ident = "ASUS M3A",
939 .matches = {
940 DMI_MATCH(DMI_BOARD_VENDOR,
941 "ASUSTeK Computer INC."),
942 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
943 },
944 },
58a09b38
SH		 945 { }
946 };
03d783bf 947 const struct dmi_system_id *match;
2fcad9d2
TH		 948 int year, month, date;
949 char buf[9];
58a09b38 950
03d783bf 951 match = dmi_first_match(sysids);
58a09b38 952 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 953 !match)
58a09b38
SH		 954 return false;
955
e65cc194
MN		 956 if (!match->driver_data)
957 goto enable_64bit;
958
2fcad9d2
TH		 959 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
960 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 961
e65cc194
MN		 962 if (strcmp(buf, match->driver_data) >= 0)
963 goto enable_64bit;
964 else {
a44fec1f
JP		 965 dev_warn(&pdev->dev,
966 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
967 match->ident);
2fcad9d2
TH		 968 return false;
969 }
e65cc194
MN		 970
971enable_64bit:
a44fec1f 972 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 973 return true;
58a09b38
SH		 974}
975
1fd68434
RW		 976static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
977{
978 static const struct dmi_system_id broken_systems[] = {
979 {
980 .ident = "HP Compaq nx6310",
981 .matches = {
982 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
983 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
984 },
985 /* PCI slot number of the controller */
986 .driver_data = (void *)0x1FUL,
987 },
d2f9c061
MR		 988 {
989 .ident = "HP Compaq 6720s",
990 .matches = {
991 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
993 },
994 /* PCI slot number of the controller */
995 .driver_data = (void *)0x1FUL,
996 },
1fd68434
RW		 997
998 { } /* terminate list */
999 };
1000 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1001
1002 if (dmi) {
1003 unsigned long slot = (unsigned long)dmi->driver_data;
1004 /* apply the quirk only to on-board controllers */
1005 return slot == PCI_SLOT(pdev->devfn);
1006 }
1007
1008 return false;
1009}
1010
9b10ae86
TH		 1011static bool ahci_broken_suspend(struct pci_dev *pdev)
1012{
1013 static const struct dmi_system_id sysids[] = {
1014 /*
1015 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1016 * to the harddisk doesn't become online after
1017 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1018 *
1019 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1020 *
1021 * Use dates instead of versions to match as HP is
1022 * apparently recycling both product and version
1023 * strings.
1024 *
1025 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1026 */
1027 {
1028 .ident = "dv4",
1029 .matches = {
1030 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1031 DMI_MATCH(DMI_PRODUCT_NAME,
1032 "HP Pavilion dv4 Notebook PC"),
1033 },
9deb3431 1034 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1035 },
1036 {
1037 .ident = "dv5",
1038 .matches = {
1039 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1040 DMI_MATCH(DMI_PRODUCT_NAME,
1041 "HP Pavilion dv5 Notebook PC"),
1042 },
9deb3431 1043 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1044 },
1045 {
1046 .ident = "dv6",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1049 DMI_MATCH(DMI_PRODUCT_NAME,
1050 "HP Pavilion dv6 Notebook PC"),
1051 },
9deb3431 1052 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1053 },
1054 {
1055 .ident = "HDX18",
1056 .matches = {
1057 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1058 DMI_MATCH(DMI_PRODUCT_NAME,
1059 "HP HDX18 Notebook PC"),
1060 },
9deb3431 1061 .driver_data = "20090430", /* F.23 */
9b10ae86 1062 },
cedc9bf9
TH		 1063 /*
1064 * Acer eMachines G725 has the same problem. BIOS
1065 * V1.03 is known to be broken. V3.04 is known to
25985edc 1066 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1067 * that we don't have much idea about. For now,
1068 * blacklist anything older than V3.04.
9deb3431
TH		 1069 *
1070 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1071 */
1072 {
1073 .ident = "G725",
1074 .matches = {
1075 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1076 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1077 },
9deb3431 1078 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1079 },
9b10ae86
TH		 1080 { } /* terminate list */
1081 };
1082 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1083 int year, month, date;
1084 char buf[9];
9b10ae86
TH		 1085
1086 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1087 return false;
1088
9deb3431
TH		 1089 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1090 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1091
9deb3431 1092 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1093}
1094
5594639a
TH		 1095static bool ahci_broken_online(struct pci_dev *pdev)
1096{
1097#define ENCODE_BUSDEVFN(bus, slot, func) \
1098 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1099 static const struct dmi_system_id sysids[] = {
1100 /*
1101 * There are several gigabyte boards which use
1102 * SIMG5723s configured as hardware RAID. Certain
1103 * 5723 firmware revisions shipped there keep the link
1104 * online but fail to answer properly to SRST or
1105 * IDENTIFY when no device is attached downstream
1106 * causing libata to retry quite a few times leading
1107 * to excessive detection delay.
1108 *
1109 * As these firmwares respond to the second reset try
1110 * with invalid device signature, considering unknown
1111 * sig as offline works around the problem acceptably.
1112 */
1113 {
1114 .ident = "EP45-DQ6",
1115 .matches = {
1116 DMI_MATCH(DMI_BOARD_VENDOR,
1117 "Gigabyte Technology Co., Ltd."),
1118 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1119 },
1120 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1121 },
1122 {
1123 .ident = "EP45-DS5",
1124 .matches = {
1125 DMI_MATCH(DMI_BOARD_VENDOR,
1126 "Gigabyte Technology Co., Ltd."),
1127 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1128 },
1129 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1130 },
1131 { } /* terminate list */
1132 };
1133#undef ENCODE_BUSDEVFN
1134 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1135 unsigned int val;
1136
1137 if (!dmi)
1138 return false;
1139
1140 val = (unsigned long)dmi->driver_data;
1141
1142 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1143}
1144
0cf4a7d6
JP		 1145static bool ahci_broken_devslp(struct pci_dev *pdev)
1146{
1147 /* device with broken DEVSLP but still showing SDS capability */
1148 static const struct pci_device_id ids[] = {
1149 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1150 {}
1151 };
1152
1153 return pci_match_id(ids, pdev);
1154}
1155
8e513217 1156#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1157static void ahci_gtf_filter_workaround(struct ata_host *host)
1158{
1159 static const struct dmi_system_id sysids[] = {
1160 /*
1161 * Aspire 3810T issues a bunch of SATA enable commands
1162 * via _GTF including an invalid one and one which is
1163 * rejected by the device. Among the successful ones
1164 * is FPDMA non-zero offset enable which when enabled
1165 * only on the drive side leads to NCQ command
1166 * failures. Filter it out.
1167 */
1168 {
1169 .ident = "Aspire 3810T",
1170 .matches = {
1171 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1172 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1173 },
1174 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1175 },
1176 { }
1177 };
1178 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1179 unsigned int filter;
1180 int i;
1181
1182 if (!dmi)
1183 return;
1184
1185 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1186 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1187 filter, dmi->ident);
f80ae7e4
TH		 1188
1189 for (i = 0; i < host->n_ports; i++) {
1190 struct ata_port *ap = host->ports[i];
1191 struct ata_link *link;
1192 struct ata_device *dev;
1193
1194 ata_for_each_link(link, ap, EDGE)
1195 ata_for_each_dev(dev, link, ALL)
1196 dev->gtf_filter |= filter;
1197 }
1198}
8e513217
MT		 1199#else
1200static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1201{}
1202#endif
f80ae7e4 1203
e1ba8459 1204static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1205 struct ahci_host_priv *hpriv)
5ca72c4f 1206{
ccf8f53c 1207 int rc, nvec;
5ca72c4f 1208
7b92b4f6
AG		 1209 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1210 goto intx;
1211
fc061d96
AG		 1212 nvec = pci_msi_vec_count(pdev);
1213 if (nvec < 0)
7b92b4f6
AG		 1214 goto intx;
1215
1216 /*
1217 * If number of MSIs is less than number of ports then Sharing Last
1218 * Message mode could be enforced. In this case assume that advantage
1219 * of multipe MSIs is negated and use single MSI mode instead.
1220 */
fc061d96 1221 if (nvec < n_ports)
7b92b4f6
AG		 1222 goto single_msi;
1223
ccf8f53c
AG		 1224 rc = pci_enable_msi_exact(pdev, nvec);
1225 if (rc == -ENOSPC)
fc40363b 1226 goto single_msi;
ccf8f53c 1227 else if (rc < 0)
fc061d96 1228 goto intx;
5ca72c4f 1229
ab0f9e78
AG		 1230 /* fallback to single MSI mode if the controller enforced MRSM mode */
1231 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1232 pci_disable_msi(pdev);
1233 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1234 goto single_msi;
1235 }
1236
c3ebd6a9
AG		 1237 if (nvec > 1)
1238 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1239
7b92b4f6
AG		 1240 return nvec;
1241
1242single_msi:
fc061d96 1243 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1244 goto intx;
1245 return 1;
1246
1247intx:
5ca72c4f
AG		 1248 pci_intx(pdev, 1);
1249 return 0;
1250}
1251
24dc5f33 1252static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1253{
e297d99e
TH		 1254 unsigned int board_id = ent->driver_data;
1255 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1256 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1257 struct device *dev = &pdev->dev;
1da177e4 1258 struct ahci_host_priv *hpriv;
4447d351 1259 struct ata_host *host;
c3ebd6a9 1260 int n_ports, i, rc;
318893e1 1261 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1262
1263 VPRINTK("ENTER\n");
1264
b429dd59 1265 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1266
06296a1e 1267 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1268
5b66c829
AC		 1269 /* The AHCI driver can only drive the SATA ports, the PATA driver
1270 can drive them all so if both drivers are selected make sure
1271 AHCI stays out of the way */
1272 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1273 return -ENODEV;
1274
cb85696d
JL		 1275 /* Apple BIOS on MCP89 prevents us using AHCI */
1276 if (is_mcp89_apple(pdev))
1277 ahci_mcp89_apple_enable(pdev);
c6353b45 1278
7a02267e
MN		 1279 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1280 * At the moment, we can only use the AHCI mode. Let the users know
1281 * that for SAS drives they're out of luck.
1282 */
1283 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1284 dev_info(&pdev->dev,
1285 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1286
7f9c9f8e 1287 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1288 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1289 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1290 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1291 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1292
e6b7e41c
CL		 1293 /*
1294 * The JMicron chip 361/363 contains one SATA controller and one
1295 * PATA controller,for powering on these both controllers, we must
1296 * follow the sequence one by one, otherwise one of them can not be
1297 * powered on successfully, so here we disable the async suspend
1298 * method for these chips.
1299 */
1300 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1301 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1302 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1303 device_disable_async_suspend(&pdev->dev);
1304
4447d351 1305 /* acquire resources */
24dc5f33 1306 rc = pcim_enable_device(pdev);
1da177e4
LT		 1307 if (rc)
1308 return rc;
1309
c4f7792c
TH		 1310 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1311 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1312 u8 map;
1313
1314 /* ICH6s share the same PCI ID for both piix and ahci
1315 * modes. Enabling ahci mode while MAP indicates
1316 * combined mode is a bad idea. Yield to ata_piix.
1317 */
1318 pci_read_config_byte(pdev, ICH_MAP, &map);
1319 if (map & 0x3) {
a44fec1f
JP		 1320 dev_info(&pdev->dev,
1321 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1322 return -ENODEV;
1323 }
1324 }
1325
6fec8871
PB		 1326 /* AHCI controllers often implement SFF compatible interface.
1327 * Grab all PCI BARs just in case.
1328 */
1329 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1330 if (rc == -EBUSY)
1331 pcim_pin_device(pdev);
1332 if (rc)
1333 return rc;
1334
24dc5f33
TH		 1335 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1336 if (!hpriv)
1337 return -ENOMEM;
417a1a6d
TH		 1338 hpriv->flags |= (unsigned long)pi.private_data;
1339
e297d99e
TH		 1340 /* MCP65 revision A1 and A2 can't do MSI */
1341 if (board_id == board_ahci_mcp65 &&
1342 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1343 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1344
e427fe04
SH		 1345 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1346 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1347 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1348
2fcad9d2
TH		 1349 /* only some SB600s can do 64bit DMA */
1350 if (ahci_sb600_enable_64bit(pdev))
1351 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1352
318893e1 1353 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1354
0cf4a7d6
JP		 1355 /* must set flag prior to save config in order to take effect */
1356 if (ahci_broken_devslp(pdev))
1357 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1358
4447d351 1359 /* save initial config */
394d6e53 1360 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1361
4447d351 1362 /* prepare host */
453d3131
RH		 1363 if (hpriv->cap & HOST_CAP_NCQ) {
1364 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1365 /*
1366 * Auto-activate optimization is supposed to be
1367 * supported on all AHCI controllers indicating NCQ
1368 * capability, but it seems to be broken on some
1369 * chipsets including NVIDIAs.
1370 */
1371 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1372 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1373
1374 /*
1375 * All AHCI controllers should be forward-compatible
1376 * with the new auxiliary field. This code should be
1377 * conditionalized if any buggy AHCI controllers are
1378 * encountered.
1379 */
1380 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1381 }
1da177e4 1382
7d50b60b
TH		 1383 if (hpriv->cap & HOST_CAP_PMP)
1384 pi.flags |= ATA_FLAG_PMP;
1385
0cbb0e77 1386 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1387
1fd68434
RW		 1388 if (ahci_broken_system_poweroff(pdev)) {
1389 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1390 dev_info(&pdev->dev,
1391 "quirky BIOS, skipping spindown on poweroff\n");
1392 }
1393
9b10ae86
TH		 1394 if (ahci_broken_suspend(pdev)) {
1395 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1396 dev_warn(&pdev->dev,
1397 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1398 }
1399
5594639a
TH		 1400 if (ahci_broken_online(pdev)) {
1401 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1402 dev_info(&pdev->dev,
1403 "online status unreliable, applying workaround\n");
1404 }
1405
837f5f8f
TH		 1406 /* CAP.NP sometimes indicate the index of the last enabled
1407 * port, at other times, that of the last possible port, so
1408 * determining the maximum port number requires looking at
1409 * both CAP.NP and port_map.
1410 */
1411 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1412
c3ebd6a9 1413 ahci_init_interrupts(pdev, n_ports, hpriv);
7b92b4f6 1414
837f5f8f 1415 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1416 if (!host)
1417 return -ENOMEM;
4447d351
TH		 1418 host->private_data = hpriv;
1419
f3d7f23f 1420 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1421 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1422 else
d2782d96 1423 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1424
18f7ba4c
KCA		 1425 if (pi.flags & ATA_FLAG_EM)
1426 ahci_reset_em(host);
1427
4447d351 1428 for (i = 0; i < host->n_ports; i++) {
dab632e8 1429 struct ata_port *ap = host->ports[i];
4447d351 1430
318893e1
AR		 1431 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1432 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1433 0x100 + ap->port_no * 0x80, "port");
1434
18f7ba4c
KCA		 1435 /* set enclosure management message type */
1436 if (ap->flags & ATA_FLAG_EM)
008dbd61 1437 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1438
1439
dab632e8 1440 /* disabled/not-implemented port */
350756f6 1441 if (!(hpriv->port_map & (1 << i)))
dab632e8 1442 ap->ops = &ata_dummy_port_ops;
4447d351 1443 }
d447df14 1444
edc93052
TH		 1445 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1446 ahci_p5wdh_workaround(host);
1447
f80ae7e4
TH		 1448 /* apply gtf filter quirk */
1449 ahci_gtf_filter_workaround(host);
1450
4447d351
TH		 1451 /* initialize adapter */
1452 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1453 if (rc)
24dc5f33 1454 return rc;
1da177e4 1455
3303040d 1456 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1457 if (rc)
1458 return rc;
1da177e4 1459
781d6550 1460 ahci_pci_init_controller(host);
439fcaec 1461 ahci_pci_print_info(host);
1da177e4 1462
4447d351 1463 pci_set_master(pdev);
5ca72c4f 1464
d1028e2f 1465 return ahci_host_activate(host, pdev->irq, &ahci_sht);
907f4678 1466}
1da177e4 1467
2fc75da0 1468module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1469
1470MODULE_AUTHOR("Jeff Garzik");
1471MODULE_DESCRIPTION("AHCI SATA low-level driver");
1472MODULE_LICENSE("GPL");
1473MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1474MODULE_VERSION(DRV_VERSION);
Michael's Linux tree.