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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
9f472e65 SB |
2 | /* |
3 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
4 | * Terry Lv <r65388@freescale.com> | |
9f472e65 SB |
5 | */ |
6 | ||
0f07df43 | 7 | #include <common.h> |
9f472e65 | 8 | #include <ahci.h> |
1eb69ae4 | 9 | #include <cpu_func.h> |
c893f1e6 SG |
10 | #include <dm.h> |
11 | #include <dwc_ahsata.h> | |
9f472e65 | 12 | #include <fis.h> |
0f07df43 | 13 | #include <libata.h> |
9f472e65 | 14 | #include <malloc.h> |
752126a0 | 15 | #include <memalign.h> |
0f07df43 | 16 | #include <sata.h> |
90526e9f | 17 | #include <asm/cache.h> |
9f472e65 | 18 | #include <asm/io.h> |
9f472e65 | 19 | #include <asm/arch/clock.h> |
ca84d72d | 20 | #include <asm/arch/sys_proto.h> |
046a69b8 | 21 | #include <asm/mach-imx/sata.h> |
0f07df43 SG |
22 | #include <linux/bitops.h> |
23 | #include <linux/ctype.h> | |
24 | #include <linux/errno.h> | |
90abb28f | 25 | #include "dwc_ahsata_priv.h" |
9f472e65 SB |
26 | |
27 | struct sata_port_regs { | |
28 | u32 clb; | |
29 | u32 clbu; | |
30 | u32 fb; | |
31 | u32 fbu; | |
32 | u32 is; | |
33 | u32 ie; | |
34 | u32 cmd; | |
35 | u32 res1[1]; | |
36 | u32 tfd; | |
37 | u32 sig; | |
38 | u32 ssts; | |
39 | u32 sctl; | |
40 | u32 serr; | |
41 | u32 sact; | |
42 | u32 ci; | |
43 | u32 sntf; | |
44 | u32 res2[1]; | |
45 | u32 dmacr; | |
46 | u32 res3[1]; | |
47 | u32 phycr; | |
48 | u32 physr; | |
49 | }; | |
50 | ||
51 | struct sata_host_regs { | |
52 | u32 cap; | |
53 | u32 ghc; | |
54 | u32 is; | |
55 | u32 pi; | |
56 | u32 vs; | |
57 | u32 ccc_ctl; | |
58 | u32 ccc_ports; | |
59 | u32 res1[2]; | |
60 | u32 cap2; | |
61 | u32 res2[30]; | |
62 | u32 bistafr; | |
63 | u32 bistcr; | |
64 | u32 bistfctr; | |
65 | u32 bistsr; | |
66 | u32 bistdecr; | |
67 | u32 res3[2]; | |
68 | u32 oobr; | |
69 | u32 res4[8]; | |
70 | u32 timer1ms; | |
71 | u32 res5[1]; | |
72 | u32 gparam1r; | |
73 | u32 gparam2r; | |
74 | u32 pparamr; | |
75 | u32 testr; | |
76 | u32 versionr; | |
77 | u32 idr; | |
78 | }; | |
79 | ||
80 | #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) | |
81 | #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) | |
82 | ||
83 | #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) | |
84 | ||
fa31377e | 85 | static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) |
9f472e65 SB |
86 | { |
87 | return base + 0x100 + (port * 0x80); | |
88 | } | |
89 | ||
90 | static int waiting_for_cmd_completed(u8 *offset, | |
91 | int timeout_msec, | |
92 | u32 sign) | |
93 | { | |
94 | int i; | |
95 | u32 status; | |
96 | ||
97 | for (i = 0; | |
98 | ((status = readl(offset)) & sign) && i < timeout_msec; | |
99 | ++i) | |
100 | mdelay(1); | |
101 | ||
102 | return (i < timeout_msec) ? 0 : -1; | |
103 | } | |
104 | ||
09bb951b | 105 | static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) |
9f472e65 | 106 | { |
4b640dbc | 107 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
9f472e65 | 108 | |
3e59c30f SG |
109 | writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); |
110 | writel(0x02060b14, &host_mmio->oobr); | |
9f472e65 SB |
111 | |
112 | return 0; | |
113 | } | |
114 | ||
09bb951b | 115 | static int ahci_host_init(struct ahci_uc_priv *uc_priv) |
9f472e65 SB |
116 | { |
117 | u32 tmp, cap_save, num_ports; | |
118 | int i, j, timeout = 1000; | |
119 | struct sata_port_regs *port_mmio = NULL; | |
4b640dbc | 120 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
9f472e65 SB |
121 | int clk = mxc_get_clock(MXC_SATA_CLK); |
122 | ||
3e59c30f | 123 | cap_save = readl(&host_mmio->cap); |
9f472e65 SB |
124 | cap_save |= SATA_HOST_CAP_SSS; |
125 | ||
126 | /* global controller reset */ | |
3e59c30f | 127 | tmp = readl(&host_mmio->ghc); |
9f472e65 | 128 | if ((tmp & SATA_HOST_GHC_HR) == 0) |
3e59c30f | 129 | writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); |
9f472e65 | 130 | |
3e59c30f | 131 | while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) |
9f472e65 SB |
132 | ; |
133 | ||
134 | if (timeout <= 0) { | |
135 | debug("controller reset failed (0x%x)\n", tmp); | |
136 | return -1; | |
137 | } | |
138 | ||
139 | /* Set timer 1ms */ | |
3e59c30f | 140 | writel(clk / 1000, &host_mmio->timer1ms); |
9f472e65 | 141 | |
09bb951b | 142 | ahci_setup_oobr(uc_priv, 0); |
9f472e65 | 143 | |
3e59c30f SG |
144 | writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); |
145 | writel(cap_save, &host_mmio->cap); | |
9f472e65 | 146 | num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; |
3e59c30f | 147 | writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); |
9f472e65 SB |
148 | |
149 | /* | |
150 | * Determine which Ports are implemented by the DWC_ahsata, | |
151 | * by reading the PI register. This bit map value aids the | |
152 | * software to determine how many Ports are available and | |
153 | * which Port registers need to be initialized. | |
154 | */ | |
3e59c30f SG |
155 | uc_priv->cap = readl(&host_mmio->cap); |
156 | uc_priv->port_map = readl(&host_mmio->pi); | |
9f472e65 SB |
157 | |
158 | /* Determine how many command slots the HBA supports */ | |
09bb951b | 159 | uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; |
9f472e65 SB |
160 | |
161 | debug("cap 0x%x port_map 0x%x n_ports %d\n", | |
09bb951b | 162 | uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); |
9f472e65 | 163 | |
09bb951b SG |
164 | for (i = 0; i < uc_priv->n_ports; i++) { |
165 | uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); | |
4b640dbc | 166 | port_mmio = uc_priv->port[i].port_mmio; |
9f472e65 SB |
167 | |
168 | /* Ensure that the DWC_ahsata is in idle state */ | |
3e59c30f | 169 | tmp = readl(&port_mmio->cmd); |
9f472e65 SB |
170 | |
171 | /* | |
172 | * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR | |
173 | * are all cleared, the Port is in an idle state. | |
174 | */ | |
175 | if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | | |
176 | SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { | |
177 | ||
178 | /* | |
179 | * System software places a Port into the idle state by | |
180 | * clearing P#CMD.ST and waiting for P#CMD.CR to return | |
181 | * 0 when read. | |
182 | */ | |
183 | tmp &= ~SATA_PORT_CMD_ST; | |
3e59c30f | 184 | writel_with_flush(tmp, &port_mmio->cmd); |
9f472e65 SB |
185 | |
186 | /* | |
187 | * spec says 500 msecs for each bit, so | |
188 | * this is slightly incorrect. | |
189 | */ | |
190 | mdelay(500); | |
191 | ||
192 | timeout = 1000; | |
3e59c30f | 193 | while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) |
9f472e65 SB |
194 | && --timeout) |
195 | ; | |
196 | ||
197 | if (timeout <= 0) { | |
198 | debug("port reset failed (0x%x)\n", tmp); | |
199 | return -1; | |
200 | } | |
201 | } | |
202 | ||
203 | /* Spin-up device */ | |
3e59c30f SG |
204 | tmp = readl(&port_mmio->cmd); |
205 | writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); | |
9f472e65 SB |
206 | |
207 | /* Wait for spin-up to finish */ | |
208 | timeout = 1000; | |
3e59c30f | 209 | while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) |
9f472e65 SB |
210 | && --timeout) |
211 | ; | |
212 | if (timeout <= 0) { | |
213 | debug("Spin-Up can't finish!\n"); | |
214 | return -1; | |
215 | } | |
216 | ||
217 | for (j = 0; j < 100; ++j) { | |
218 | mdelay(10); | |
3e59c30f | 219 | tmp = readl(&port_mmio->ssts); |
9f472e65 SB |
220 | if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || |
221 | ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) | |
222 | break; | |
223 | } | |
224 | ||
225 | /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ | |
226 | timeout = 1000; | |
87e2cb53 | 227 | while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X) |
9f472e65 SB |
228 | && --timeout) |
229 | ; | |
230 | if (timeout <= 0) { | |
231 | debug("Can't find DIAG_X set!\n"); | |
232 | return -1; | |
233 | } | |
234 | ||
235 | /* | |
236 | * For each implemented Port, clear the P#SERR | |
237 | * register, by writing ones to each implemented\ | |
238 | * bit location. | |
239 | */ | |
3e59c30f | 240 | tmp = readl(&port_mmio->serr); |
9f472e65 SB |
241 | debug("P#SERR 0x%x\n", |
242 | tmp); | |
3e59c30f | 243 | writel(tmp, &port_mmio->serr); |
9f472e65 SB |
244 | |
245 | /* Ack any pending irq events for this port */ | |
3e59c30f | 246 | tmp = readl(&host_mmio->is); |
9f472e65 SB |
247 | debug("IS 0x%x\n", tmp); |
248 | if (tmp) | |
3e59c30f | 249 | writel(tmp, &host_mmio->is); |
9f472e65 | 250 | |
3e59c30f | 251 | writel(1 << i, &host_mmio->is); |
9f472e65 SB |
252 | |
253 | /* set irq mask (enables interrupts) */ | |
3e59c30f | 254 | writel(DEF_PORT_IRQ, &port_mmio->ie); |
9f472e65 SB |
255 | |
256 | /* register linkup ports */ | |
3e59c30f | 257 | tmp = readl(&port_mmio->ssts); |
9f472e65 SB |
258 | debug("Port %d status: 0x%x\n", i, tmp); |
259 | if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) | |
09bb951b | 260 | uc_priv->link_port_map |= (0x01 << i); |
9f472e65 SB |
261 | } |
262 | ||
3e59c30f | 263 | tmp = readl(&host_mmio->ghc); |
9f472e65 | 264 | debug("GHC 0x%x\n", tmp); |
3e59c30f SG |
265 | writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); |
266 | tmp = readl(&host_mmio->ghc); | |
9f472e65 SB |
267 | debug("GHC 0x%x\n", tmp); |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
09bb951b | 272 | static void ahci_print_info(struct ahci_uc_priv *uc_priv) |
9f472e65 | 273 | { |
4b640dbc | 274 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; |
9f472e65 SB |
275 | u32 vers, cap, impl, speed; |
276 | const char *speed_s; | |
277 | const char *scc_s; | |
278 | ||
3e59c30f | 279 | vers = readl(&host_mmio->vs); |
09bb951b SG |
280 | cap = uc_priv->cap; |
281 | impl = uc_priv->port_map; | |
9f472e65 SB |
282 | |
283 | speed = (cap & SATA_HOST_CAP_ISS_MASK) | |
284 | >> SATA_HOST_CAP_ISS_OFFSET; | |
285 | if (speed == 1) | |
286 | speed_s = "1.5"; | |
287 | else if (speed == 2) | |
288 | speed_s = "3"; | |
289 | else | |
290 | speed_s = "?"; | |
291 | ||
292 | scc_s = "SATA"; | |
293 | ||
294 | printf("AHCI %02x%02x.%02x%02x " | |
295 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n", | |
296 | (vers >> 24) & 0xff, | |
297 | (vers >> 16) & 0xff, | |
298 | (vers >> 8) & 0xff, | |
299 | vers & 0xff, | |
300 | ((cap >> 8) & 0x1f) + 1, | |
301 | (cap & 0x1f) + 1, | |
302 | speed_s, | |
303 | impl, | |
304 | scc_s); | |
305 | ||
306 | printf("flags: " | |
307 | "%s%s%s%s%s%s" | |
308 | "%s%s%s%s%s%s%s\n", | |
309 | cap & (1 << 31) ? "64bit " : "", | |
310 | cap & (1 << 30) ? "ncq " : "", | |
311 | cap & (1 << 28) ? "ilck " : "", | |
312 | cap & (1 << 27) ? "stag " : "", | |
313 | cap & (1 << 26) ? "pm " : "", | |
314 | cap & (1 << 25) ? "led " : "", | |
315 | cap & (1 << 24) ? "clo " : "", | |
316 | cap & (1 << 19) ? "nz " : "", | |
317 | cap & (1 << 18) ? "only " : "", | |
318 | cap & (1 << 17) ? "pmp " : "", | |
319 | cap & (1 << 15) ? "pio " : "", | |
320 | cap & (1 << 14) ? "slum " : "", | |
321 | cap & (1 << 13) ? "part " : ""); | |
322 | } | |
323 | ||
09bb951b SG |
324 | static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, |
325 | unsigned char *buf, int buf_len) | |
9f472e65 | 326 | { |
3e59c30f | 327 | struct ahci_ioports *pp = &uc_priv->port[port]; |
9f472e65 SB |
328 | struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; |
329 | u32 sg_count, max_bytes; | |
330 | int i; | |
331 | ||
332 | max_bytes = MAX_DATA_BYTES_PER_SG; | |
333 | sg_count = ((buf_len - 1) / max_bytes) + 1; | |
334 | if (sg_count > AHCI_MAX_SG) { | |
335 | printf("Error:Too much sg!\n"); | |
336 | return -1; | |
337 | } | |
338 | ||
339 | for (i = 0; i < sg_count; i++) { | |
340 | ahci_sg->addr = | |
341 | cpu_to_le32((u32)buf + i * max_bytes); | |
342 | ahci_sg->addr_hi = 0; | |
343 | ahci_sg->flags_size = cpu_to_le32(0x3fffff & | |
344 | (buf_len < max_bytes | |
345 | ? (buf_len - 1) | |
346 | : (max_bytes - 1))); | |
347 | ahci_sg++; | |
348 | buf_len -= max_bytes; | |
349 | } | |
350 | ||
351 | return sg_count; | |
352 | } | |
353 | ||
354 | static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) | |
355 | { | |
356 | struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + | |
357 | AHCI_CMD_SLOT_SZ * cmd_slot); | |
358 | ||
359 | memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); | |
360 | cmd_hdr->opts = cpu_to_le32(opts); | |
361 | cmd_hdr->status = 0; | |
fa31377e TY |
362 | pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); |
363 | #ifdef CONFIG_PHYS_64BIT | |
364 | pp->cmd_slot->tbl_addr_hi = | |
365 | cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); | |
366 | #endif | |
9f472e65 SB |
367 | } |
368 | ||
369 | #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) | |
370 | ||
09bb951b SG |
371 | static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, |
372 | struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, | |
373 | s32 is_write) | |
9f472e65 | 374 | { |
3e59c30f | 375 | struct ahci_ioports *pp = &uc_priv->port[port]; |
4b640dbc | 376 | struct sata_port_regs *port_mmio = pp->port_mmio; |
9f472e65 SB |
377 | u32 opts; |
378 | int sg_count = 0, cmd_slot = 0; | |
379 | ||
3e59c30f | 380 | cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); |
9f472e65 SB |
381 | if (32 == cmd_slot) { |
382 | printf("Can't find empty command slot!\n"); | |
383 | return 0; | |
384 | } | |
385 | ||
386 | /* Check xfer length */ | |
387 | if (buf_len > MAX_BYTES_PER_TRANS) { | |
388 | printf("Max transfer length is %dB\n\r", | |
389 | MAX_BYTES_PER_TRANS); | |
390 | return 0; | |
391 | } | |
392 | ||
393 | memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); | |
394 | if (buf && buf_len) | |
09bb951b | 395 | sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); |
9f472e65 | 396 | opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); |
2dbe64ca | 397 | if (is_write) { |
9f472e65 | 398 | opts |= 0x40; |
2dbe64ca EN |
399 | flush_cache((ulong)buf, buf_len); |
400 | } | |
9f472e65 SB |
401 | ahci_fill_cmd_slot(pp, cmd_slot, opts); |
402 | ||
2dbe64ca | 403 | flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); |
3e59c30f | 404 | writel_with_flush(1 << cmd_slot, &port_mmio->ci); |
9f472e65 | 405 | |
3e59c30f SG |
406 | if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, |
407 | 0x1 << cmd_slot)) { | |
9f472e65 SB |
408 | printf("timeout exit!\n"); |
409 | return -1; | |
410 | } | |
2dbe64ca EN |
411 | invalidate_dcache_range((int)(pp->cmd_slot), |
412 | (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); | |
9f472e65 SB |
413 | debug("ahci_exec_ata_cmd: %d byte transferred.\n", |
414 | pp->cmd_slot->status); | |
2dbe64ca EN |
415 | if (!is_write) |
416 | invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); | |
9f472e65 SB |
417 | |
418 | return buf_len; | |
419 | } | |
420 | ||
47c0f369 | 421 | static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) |
9f472e65 | 422 | { |
2dbe64ca EN |
423 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
424 | struct sata_fis_h2d *cfis = &h2d; | |
9f472e65 SB |
425 | |
426 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); | |
427 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
428 | cfis->pm_port_c = 1 << 7; | |
429 | cfis->command = ATA_CMD_SET_FEATURES; | |
430 | cfis->features = SETFEATURES_XFER; | |
09bb951b | 431 | cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; |
9f472e65 | 432 | |
09bb951b | 433 | ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); |
9f472e65 SB |
434 | } |
435 | ||
09bb951b | 436 | static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) |
9f472e65 | 437 | { |
3e59c30f | 438 | struct ahci_ioports *pp = &uc_priv->port[port]; |
4b640dbc | 439 | struct sata_port_regs *port_mmio = pp->port_mmio; |
9f472e65 SB |
440 | u32 port_status; |
441 | u32 mem; | |
442 | int timeout = 10000000; | |
443 | ||
444 | debug("Enter start port: %d\n", port); | |
3e59c30f | 445 | port_status = readl(&port_mmio->ssts); |
9f472e65 SB |
446 | debug("Port %d status: %x\n", port, port_status); |
447 | if ((port_status & 0xf) != 0x03) { | |
448 | printf("No Link on this port!\n"); | |
449 | return -1; | |
450 | } | |
451 | ||
452 | mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); | |
453 | if (!mem) { | |
9f472e65 SB |
454 | printf("No mem for table!\n"); |
455 | return -ENOMEM; | |
456 | } | |
457 | ||
458 | mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ | |
459 | memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
460 | ||
461 | /* | |
462 | * First item in chunk of DMA memory: 32-slot command table, | |
463 | * 32 bytes each in size | |
464 | */ | |
465 | pp->cmd_slot = (struct ahci_cmd_hdr *)mem; | |
466 | debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); | |
467 | mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); | |
468 | ||
469 | /* | |
470 | * Second item: Received-FIS area, 256-Byte aligned | |
471 | */ | |
472 | pp->rx_fis = mem; | |
473 | mem += AHCI_RX_FIS_SZ; | |
474 | ||
475 | /* | |
476 | * Third item: data area for storing a single command | |
477 | * and its scatter-gather table | |
478 | */ | |
479 | pp->cmd_tbl = mem; | |
fa31377e | 480 | debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); |
9f472e65 SB |
481 | |
482 | mem += AHCI_CMD_TBL_HDR; | |
483 | ||
3e59c30f | 484 | writel_with_flush(0x00004444, &port_mmio->dmacr); |
9f472e65 | 485 | pp->cmd_tbl_sg = (struct ahci_sg *)mem; |
3e59c30f SG |
486 | writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); |
487 | writel_with_flush(pp->rx_fis, &port_mmio->fb); | |
9f472e65 SB |
488 | |
489 | /* Enable FRE */ | |
3e59c30f SG |
490 | writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), |
491 | &port_mmio->cmd); | |
9f472e65 SB |
492 | |
493 | /* Wait device ready */ | |
3e59c30f | 494 | while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | |
9f472e65 SB |
495 | SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) |
496 | && --timeout) | |
497 | ; | |
498 | if (timeout <= 0) { | |
499 | debug("Device not ready for BSY, DRQ and" | |
500 | "ERR in TFD!\n"); | |
501 | return -1; | |
502 | } | |
503 | ||
504 | writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
505 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | | |
3e59c30f | 506 | PORT_CMD_START, &port_mmio->cmd); |
9f472e65 SB |
507 | |
508 | debug("Exit start port %d\n", port); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
47c0f369 | 513 | static void dwc_ahsata_print_info(struct blk_desc *pdev) |
9f472e65 | 514 | { |
9f472e65 | 515 | printf("SATA Device Info:\n\r"); |
9f472e65 | 516 | printf("S/N: %s\n\rProduct model number: %s\n\r" |
d5326dfa | 517 | "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r", |
9f472e65 | 518 | pdev->product, pdev->vendor, pdev->revision, pdev->lba); |
9f472e65 SB |
519 | } |
520 | ||
47c0f369 | 521 | static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) |
9f472e65 | 522 | { |
2dbe64ca EN |
523 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
524 | struct sata_fis_h2d *cfis = &h2d; | |
09bb951b | 525 | u8 port = uc_priv->hard_port_no; |
9f472e65 SB |
526 | |
527 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); | |
528 | ||
529 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
530 | cfis->pm_port_c = 0x80; /* is command */ | |
531 | cfis->command = ATA_CMD_ID_ATA; | |
532 | ||
09bb951b SG |
533 | ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, |
534 | READ_CMD); | |
9f472e65 SB |
535 | ata_swap_buf_le16(id, ATA_ID_WORDS); |
536 | } | |
537 | ||
47c0f369 | 538 | static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) |
9f472e65 | 539 | { |
09bb951b SG |
540 | uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; |
541 | uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; | |
542 | debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); | |
9f472e65 SB |
543 | } |
544 | ||
47c0f369 SG |
545 | static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, |
546 | u32 blkcnt, u8 *buffer, int is_write) | |
9f472e65 | 547 | { |
2dbe64ca EN |
548 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
549 | struct sata_fis_h2d *cfis = &h2d; | |
09bb951b | 550 | u8 port = uc_priv->hard_port_no; |
9f472e65 SB |
551 | u32 block; |
552 | ||
553 | block = start; | |
554 | ||
555 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); | |
556 | ||
557 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
558 | cfis->pm_port_c = 0x80; /* is command */ | |
559 | cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; | |
560 | cfis->device = ATA_LBA; | |
561 | ||
562 | cfis->device |= (block >> 24) & 0xf; | |
563 | cfis->lba_high = (block >> 16) & 0xff; | |
564 | cfis->lba_mid = (block >> 8) & 0xff; | |
565 | cfis->lba_low = block & 0xff; | |
566 | cfis->sector_count = (u8)(blkcnt & 0xff); | |
567 | ||
09bb951b SG |
568 | if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, |
569 | ATA_SECT_SIZE * blkcnt, is_write) > 0) | |
9f472e65 SB |
570 | return blkcnt; |
571 | else | |
572 | return 0; | |
573 | } | |
574 | ||
47c0f369 | 575 | static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) |
9f472e65 | 576 | { |
2dbe64ca EN |
577 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
578 | struct sata_fis_h2d *cfis = &h2d; | |
09bb951b | 579 | u8 port = uc_priv->hard_port_no; |
9f472e65 SB |
580 | |
581 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); | |
582 | ||
583 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
584 | cfis->pm_port_c = 0x80; /* is command */ | |
585 | cfis->command = ATA_CMD_FLUSH; | |
586 | ||
09bb951b | 587 | ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); |
9f472e65 SB |
588 | } |
589 | ||
47c0f369 SG |
590 | static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, |
591 | lbaint_t blkcnt, u8 *buffer, int is_write) | |
9f472e65 | 592 | { |
2dbe64ca EN |
593 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
594 | struct sata_fis_h2d *cfis = &h2d; | |
09bb951b | 595 | u8 port = uc_priv->hard_port_no; |
9f472e65 SB |
596 | u64 block; |
597 | ||
598 | block = (u64)start; | |
599 | ||
600 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); | |
601 | ||
602 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
603 | cfis->pm_port_c = 0x80; /* is command */ | |
604 | ||
605 | cfis->command = (is_write) ? ATA_CMD_WRITE_EXT | |
606 | : ATA_CMD_READ_EXT; | |
607 | ||
608 | cfis->lba_high_exp = (block >> 40) & 0xff; | |
609 | cfis->lba_mid_exp = (block >> 32) & 0xff; | |
610 | cfis->lba_low_exp = (block >> 24) & 0xff; | |
611 | cfis->lba_high = (block >> 16) & 0xff; | |
612 | cfis->lba_mid = (block >> 8) & 0xff; | |
613 | cfis->lba_low = block & 0xff; | |
614 | cfis->device = ATA_LBA; | |
615 | cfis->sector_count_exp = (blkcnt >> 8) & 0xff; | |
616 | cfis->sector_count = blkcnt & 0xff; | |
617 | ||
09bb951b SG |
618 | if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, |
619 | ATA_SECT_SIZE * blkcnt, is_write) > 0) | |
9f472e65 SB |
620 | return blkcnt; |
621 | else | |
622 | return 0; | |
623 | } | |
624 | ||
47c0f369 | 625 | static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) |
9f472e65 | 626 | { |
2dbe64ca EN |
627 | struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); |
628 | struct sata_fis_h2d *cfis = &h2d; | |
09bb951b | 629 | u8 port = uc_priv->hard_port_no; |
9f472e65 SB |
630 | |
631 | memset(cfis, 0, sizeof(struct sata_fis_h2d)); | |
632 | ||
633 | cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; | |
634 | cfis->pm_port_c = 0x80; /* is command */ | |
635 | cfis->command = ATA_CMD_FLUSH_EXT; | |
636 | ||
09bb951b | 637 | ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); |
9f472e65 SB |
638 | } |
639 | ||
47c0f369 | 640 | static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) |
9f472e65 | 641 | { |
9f472e65 | 642 | if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) |
09bb951b | 643 | uc_priv->flags |= SATA_FLAG_WCACHE; |
9f472e65 | 644 | if (ata_id_has_flush(id)) |
09bb951b | 645 | uc_priv->flags |= SATA_FLAG_FLUSH; |
9f472e65 | 646 | if (ata_id_has_flush_ext(id)) |
09bb951b | 647 | uc_priv->flags |= SATA_FLAG_FLUSH_EXT; |
9f472e65 SB |
648 | } |
649 | ||
47c0f369 SG |
650 | static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, |
651 | lbaint_t blkcnt, const void *buffer, | |
652 | int is_write) | |
9f472e65 SB |
653 | { |
654 | u32 start, blks; | |
655 | u8 *addr; | |
656 | int max_blks; | |
657 | ||
658 | start = blknr; | |
659 | blks = blkcnt; | |
660 | addr = (u8 *)buffer; | |
661 | ||
662 | max_blks = ATA_MAX_SECTORS_LBA48; | |
663 | ||
664 | do { | |
665 | if (blks > max_blks) { | |
47c0f369 SG |
666 | if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, |
667 | max_blks, addr, | |
668 | is_write)) | |
9f472e65 SB |
669 | return 0; |
670 | start += max_blks; | |
671 | blks -= max_blks; | |
672 | addr += ATA_SECT_SIZE * max_blks; | |
673 | } else { | |
47c0f369 SG |
674 | if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, |
675 | addr, is_write)) | |
9f472e65 SB |
676 | return 0; |
677 | start += blks; | |
678 | blks = 0; | |
679 | addr += ATA_SECT_SIZE * blks; | |
680 | } | |
681 | } while (blks != 0); | |
682 | ||
683 | return blkcnt; | |
684 | } | |
685 | ||
47c0f369 SG |
686 | static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, |
687 | lbaint_t blkcnt, const void *buffer, | |
688 | int is_write) | |
9f472e65 SB |
689 | { |
690 | u32 start, blks; | |
691 | u8 *addr; | |
692 | int max_blks; | |
693 | ||
694 | start = blknr; | |
695 | blks = blkcnt; | |
696 | addr = (u8 *)buffer; | |
697 | ||
698 | max_blks = ATA_MAX_SECTORS; | |
699 | do { | |
700 | if (blks > max_blks) { | |
47c0f369 SG |
701 | if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, |
702 | max_blks, addr, | |
703 | is_write)) | |
9f472e65 SB |
704 | return 0; |
705 | start += max_blks; | |
706 | blks -= max_blks; | |
707 | addr += ATA_SECT_SIZE * max_blks; | |
708 | } else { | |
47c0f369 SG |
709 | if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, |
710 | addr, is_write)) | |
9f472e65 SB |
711 | return 0; |
712 | start += blks; | |
713 | blks = 0; | |
714 | addr += ATA_SECT_SIZE * blks; | |
715 | } | |
716 | } while (blks != 0); | |
717 | ||
718 | return blkcnt; | |
719 | } | |
720 | ||
752126a0 SG |
721 | static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv) |
722 | { | |
723 | u32 linkmap; | |
724 | int i; | |
725 | ||
726 | linkmap = uc_priv->link_port_map; | |
727 | ||
728 | if (0 == linkmap) { | |
729 | printf("No port device detected!\n"); | |
730 | return -ENXIO; | |
731 | } | |
732 | ||
733 | for (i = 0; i < uc_priv->n_ports; i++) { | |
734 | if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { | |
735 | if (ahci_port_start(uc_priv, (u8)i)) { | |
736 | printf("Can not start port %d\n", i); | |
737 | return 1; | |
738 | } | |
739 | uc_priv->hard_port_no = i; | |
740 | break; | |
741 | } | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, | |
748 | struct blk_desc *pdev) | |
749 | { | |
750 | u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; | |
751 | u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; | |
752 | u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; | |
752126a0 SG |
753 | u8 port = uc_priv->hard_port_no; |
754 | ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS); | |
755 | ||
756 | /* Identify device to get information */ | |
757 | dwc_ahsata_identify(uc_priv, id); | |
758 | ||
759 | /* Serial number */ | |
760 | ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); | |
761 | memcpy(pdev->product, serial, sizeof(serial)); | |
762 | ||
763 | /* Firmware version */ | |
764 | ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); | |
765 | memcpy(pdev->revision, firmware, sizeof(firmware)); | |
766 | ||
767 | /* Product model */ | |
768 | ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); | |
769 | memcpy(pdev->vendor, product, sizeof(product)); | |
770 | ||
d5326dfa SM |
771 | /* Total sectors */ |
772 | pdev->lba = ata_id_n_sectors(id); | |
752126a0 SG |
773 | |
774 | pdev->type = DEV_TYPE_HARDDISK; | |
775 | pdev->blksz = ATA_SECT_SIZE; | |
776 | pdev->lun = 0; | |
777 | ||
778 | /* Check if support LBA48 */ | |
779 | if (ata_id_has_lba48(id)) { | |
780 | pdev->lba48 = 1; | |
781 | debug("Device support LBA48\n\r"); | |
782 | } | |
783 | ||
784 | /* Get the NCQ queue depth from device */ | |
785 | uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); | |
786 | uc_priv->flags |= ata_id_queue_depth(id); | |
787 | ||
788 | /* Get the xfer mode from device */ | |
789 | dwc_ahsata_xfer_mode(uc_priv, id); | |
790 | ||
791 | /* Get the write cache status from device */ | |
792 | dwc_ahsata_init_wcache(uc_priv, id); | |
793 | ||
794 | /* Set the xfer mode to highest speed */ | |
795 | ahci_set_feature(uc_priv, port); | |
796 | ||
797 | dwc_ahsata_print_info(pdev); | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | /* | |
803 | * SATA interface between low level driver and command layer | |
804 | */ | |
805 | static ulong sata_read_common(struct ahci_uc_priv *uc_priv, | |
806 | struct blk_desc *desc, ulong blknr, | |
807 | lbaint_t blkcnt, void *buffer) | |
808 | { | |
809 | u32 rc; | |
810 | ||
811 | if (desc->lba48) | |
812 | rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, | |
813 | READ_CMD); | |
814 | else | |
815 | rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, | |
816 | READ_CMD); | |
817 | ||
818 | return rc; | |
819 | } | |
820 | ||
821 | static ulong sata_write_common(struct ahci_uc_priv *uc_priv, | |
822 | struct blk_desc *desc, ulong blknr, | |
823 | lbaint_t blkcnt, const void *buffer) | |
824 | { | |
825 | u32 rc; | |
826 | u32 flags = uc_priv->flags; | |
827 | ||
828 | if (desc->lba48) { | |
829 | rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, | |
830 | WRITE_CMD); | |
831 | if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT)) | |
832 | dwc_ahsata_flush_cache_ext(uc_priv); | |
833 | } else { | |
834 | rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, | |
835 | WRITE_CMD); | |
836 | if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH)) | |
837 | dwc_ahsata_flush_cache(uc_priv); | |
838 | } | |
839 | ||
840 | return rc; | |
841 | } | |
842 | ||
c893f1e6 | 843 | #if !CONFIG_IS_ENABLED(AHCI) |
036a803e SG |
844 | static int ahci_init_one(int pdev) |
845 | { | |
846 | int rc; | |
847 | struct ahci_uc_priv *uc_priv = NULL; | |
848 | ||
849 | uc_priv = malloc(sizeof(struct ahci_uc_priv)); | |
bf38cbf9 YL |
850 | if (!uc_priv) |
851 | return -ENOMEM; | |
852 | ||
036a803e SG |
853 | memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); |
854 | uc_priv->dev = pdev; | |
855 | ||
856 | uc_priv->host_flags = ATA_FLAG_SATA | |
857 | | ATA_FLAG_NO_LEGACY | |
858 | | ATA_FLAG_MMIO | |
859 | | ATA_FLAG_PIO_DMA | |
860 | | ATA_FLAG_NO_ATAPI; | |
861 | ||
862 | uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; | |
863 | ||
864 | /* initialize adapter */ | |
865 | rc = ahci_host_init(uc_priv); | |
866 | if (rc) | |
867 | goto err_out; | |
868 | ||
869 | ahci_print_info(uc_priv); | |
870 | ||
871 | /* Save the uc_private struct to block device struct */ | |
872 | sata_dev_desc[pdev].priv = uc_priv; | |
873 | ||
874 | return 0; | |
875 | ||
876 | err_out: | |
bf38cbf9 YL |
877 | if (uc_priv) |
878 | free(uc_priv); | |
036a803e SG |
879 | return rc; |
880 | } | |
881 | ||
c5273acf SG |
882 | int init_sata(int dev) |
883 | { | |
09bb951b | 884 | struct ahci_uc_priv *uc_priv = NULL; |
c5273acf SG |
885 | |
886 | #if defined(CONFIG_MX6) | |
887 | if (!is_mx6dq() && !is_mx6dqp()) | |
888 | return 1; | |
889 | #endif | |
890 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { | |
891 | printf("The sata index %d is out of ranges\n\r", dev); | |
892 | return -1; | |
893 | } | |
894 | ||
895 | ahci_init_one(dev); | |
896 | ||
4b640dbc | 897 | uc_priv = sata_dev_desc[dev].priv; |
c5273acf | 898 | |
752126a0 | 899 | return dwc_ahci_start_ports(uc_priv) ? 1 : 0; |
c5273acf SG |
900 | } |
901 | ||
902 | int reset_sata(int dev) | |
903 | { | |
09bb951b | 904 | struct ahci_uc_priv *uc_priv; |
c5273acf SG |
905 | struct sata_host_regs *host_mmio; |
906 | ||
907 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { | |
908 | printf("The sata index %d is out of ranges\n\r", dev); | |
909 | return -1; | |
910 | } | |
911 | ||
4b640dbc | 912 | uc_priv = sata_dev_desc[dev].priv; |
09bb951b | 913 | if (NULL == uc_priv) |
c5273acf SG |
914 | /* not initialized, so nothing to reset */ |
915 | return 0; | |
916 | ||
4b640dbc | 917 | host_mmio = uc_priv->mmio_base; |
c5273acf SG |
918 | setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); |
919 | while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) | |
920 | udelay(100); | |
921 | ||
6b6c620c YL |
922 | free(uc_priv); |
923 | memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc)); | |
924 | ||
c5273acf SG |
925 | return 0; |
926 | } | |
927 | ||
dc383dd5 NK |
928 | int sata_port_status(int dev, int port) |
929 | { | |
930 | struct sata_port_regs *port_mmio; | |
09bb951b | 931 | struct ahci_uc_priv *uc_priv = NULL; |
dc383dd5 NK |
932 | |
933 | if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) | |
934 | return -EINVAL; | |
935 | ||
936 | if (sata_dev_desc[dev].priv == NULL) | |
937 | return -ENODEV; | |
938 | ||
4b640dbc SG |
939 | uc_priv = sata_dev_desc[dev].priv; |
940 | port_mmio = uc_priv->port[port].port_mmio; | |
dc383dd5 | 941 | |
3e59c30f | 942 | return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; |
dc383dd5 NK |
943 | } |
944 | ||
9f472e65 SB |
945 | /* |
946 | * SATA interface between low level driver and command layer | |
947 | */ | |
dac87571 | 948 | ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) |
9f472e65 | 949 | { |
47c0f369 | 950 | struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; |
9f472e65 | 951 | |
752126a0 SG |
952 | return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, |
953 | buffer); | |
9f472e65 SB |
954 | } |
955 | ||
dac87571 | 956 | ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) |
9f472e65 | 957 | { |
4b640dbc | 958 | struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; |
9f472e65 | 959 | |
752126a0 SG |
960 | return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, |
961 | buffer); | |
9f472e65 SB |
962 | } |
963 | ||
964 | int scan_sata(int dev) | |
965 | { | |
4b640dbc | 966 | struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; |
3e59c30f | 967 | struct blk_desc *pdev = &sata_dev_desc[dev]; |
9f472e65 | 968 | |
752126a0 | 969 | return dwc_ahsata_scan_common(uc_priv, pdev); |
9f472e65 | 970 | } |
c893f1e6 SG |
971 | #endif /* CONFIG_IS_ENABLED(AHCI) */ |
972 | ||
973 | #if CONFIG_IS_ENABLED(AHCI) | |
974 | ||
975 | int dwc_ahsata_port_status(struct udevice *dev, int port) | |
976 | { | |
977 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); | |
978 | struct sata_port_regs *port_mmio; | |
979 | ||
980 | port_mmio = uc_priv->port[port].port_mmio; | |
981 | return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO; | |
982 | } | |
983 | ||
984 | int dwc_ahsata_bus_reset(struct udevice *dev) | |
985 | { | |
986 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); | |
987 | struct sata_host_regs *host_mmio = uc_priv->mmio_base; | |
988 | ||
989 | setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); | |
990 | while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) | |
991 | udelay(100); | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
996 | int dwc_ahsata_scan(struct udevice *dev) | |
997 | { | |
998 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); | |
999 | struct blk_desc *desc; | |
1000 | struct udevice *blk; | |
1001 | int ret; | |
1002 | ||
1003 | /* | |
1004 | * Create only one block device and do detection | |
1005 | * to make sure that there won't be a lot of | |
1006 | * block devices created | |
1007 | */ | |
1008 | device_find_first_child(dev, &blk); | |
1009 | if (!blk) { | |
1010 | ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk", | |
1011 | IF_TYPE_SATA, -1, 512, 0, &blk); | |
1012 | if (ret) { | |
1013 | debug("Can't create device\n"); | |
1014 | return ret; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | desc = dev_get_uclass_platdata(blk); | |
1019 | ret = dwc_ahsata_scan_common(uc_priv, desc); | |
1020 | if (ret) { | |
1021 | debug("%s: Failed to scan bus\n", __func__); | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | int dwc_ahsata_probe(struct udevice *dev) | |
1029 | { | |
1030 | struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); | |
1031 | int ret; | |
1032 | ||
046a69b8 SM |
1033 | #if defined(CONFIG_MX6) |
1034 | setup_sata(); | |
1035 | #endif | |
c893f1e6 SG |
1036 | uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
1037 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; | |
1038 | uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); | |
1039 | ||
1040 | /* initialize adapter */ | |
1041 | ret = ahci_host_init(uc_priv); | |
1042 | if (ret) | |
1043 | return ret; | |
1044 | ||
1045 | ahci_print_info(uc_priv); | |
1046 | ||
1047 | return dwc_ahci_start_ports(uc_priv); | |
1048 | } | |
1049 | ||
1050 | static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr, | |
1051 | lbaint_t blkcnt, void *buffer) | |
1052 | { | |
1053 | struct blk_desc *desc = dev_get_uclass_platdata(blk); | |
1054 | struct udevice *dev = dev_get_parent(blk); | |
1055 | struct ahci_uc_priv *uc_priv; | |
1056 | ||
1057 | uc_priv = dev_get_uclass_priv(dev); | |
1058 | return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer); | |
1059 | } | |
1060 | ||
1061 | static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr, | |
1062 | lbaint_t blkcnt, const void *buffer) | |
1063 | { | |
1064 | struct blk_desc *desc = dev_get_uclass_platdata(blk); | |
1065 | struct udevice *dev = dev_get_parent(blk); | |
1066 | struct ahci_uc_priv *uc_priv; | |
1067 | ||
1068 | uc_priv = dev_get_uclass_priv(dev); | |
1069 | return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer); | |
1070 | } | |
1071 | ||
1072 | static const struct blk_ops dwc_ahsata_blk_ops = { | |
1073 | .read = dwc_ahsata_read, | |
1074 | .write = dwc_ahsata_write, | |
1075 | }; | |
1076 | ||
1077 | U_BOOT_DRIVER(dwc_ahsata_blk) = { | |
1078 | .name = "dwc_ahsata_blk", | |
1079 | .id = UCLASS_BLK, | |
1080 | .ops = &dwc_ahsata_blk_ops, | |
1081 | }; | |
1082 | ||
046a69b8 SM |
1083 | #if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI) |
1084 | struct ahci_ops dwc_ahsata_ahci_ops = { | |
1085 | .port_status = dwc_ahsata_port_status, | |
1086 | .reset = dwc_ahsata_bus_reset, | |
1087 | .scan = dwc_ahsata_scan, | |
1088 | }; | |
1089 | ||
1090 | static const struct udevice_id dwc_ahsata_ahci_ids[] = { | |
1091 | { .compatible = "fsl,imx6q-ahci" }, | |
1092 | { } | |
1093 | }; | |
1094 | ||
1095 | U_BOOT_DRIVER(dwc_ahsata_ahci) = { | |
1096 | .name = "dwc_ahsata_ahci", | |
1097 | .id = UCLASS_AHCI, | |
1098 | .of_match = dwc_ahsata_ahci_ids, | |
1099 | .ops = &dwc_ahsata_ahci_ops, | |
1100 | .probe = dwc_ahsata_probe, | |
1101 | }; | |
1102 | #endif | |
c893f1e6 | 1103 | #endif |