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76f260d1 MV |
1 | /* |
2 | * Freescale iMX51 ATA driver | |
3 | * | |
4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
6 | * Based on code by: | |
7 | * Mahesh Mahadevan <mahesh.mahadevan@freescale.com> | |
8 | * | |
9 | * Based on code from original FSL ATA driver, which is | |
10 | * part of eCos, the Embedded Configurable Operating System. | |
11 | * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. | |
12 | * | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
76f260d1 MV |
14 | */ |
15 | ||
16 | #include <common.h> | |
17 | #include <command.h> | |
18 | #include <config.h> | |
19 | #include <asm/byteorder.h> | |
20 | #include <asm/io.h> | |
21 | #include <ide.h> | |
22 | ||
23 | #include <asm/arch/imx-regs.h> | |
24 | #include <asm/arch/clock.h> | |
25 | ||
26 | /* MXC ATA register offsets */ | |
27 | struct mxc_ata_config_regs { | |
28 | u8 time_off; /* 0x00 */ | |
29 | u8 time_on; | |
30 | u8 time_1; | |
31 | u8 time_2w; | |
32 | u8 time_2r; | |
33 | u8 time_ax; | |
34 | u8 time_pio_rdx; | |
35 | u8 time_4; | |
36 | u8 time_9; | |
37 | u8 time_m; | |
38 | u8 time_jn; | |
39 | u8 time_d; | |
40 | u8 time_k; | |
41 | u8 time_ack; | |
42 | u8 time_env; | |
43 | u8 time_udma_rdx; | |
44 | u8 time_zah; /* 0x10 */ | |
45 | u8 time_mlix; | |
46 | u8 time_dvh; | |
47 | u8 time_dzfs; | |
48 | u8 time_dvs; | |
49 | u8 time_cvh; | |
50 | u8 time_ss; | |
51 | u8 time_cyc; | |
52 | u32 fifo_data_32; /* 0x18 */ | |
53 | u32 fifo_data_16; | |
54 | u32 fifo_fill; | |
55 | u32 ata_control; | |
56 | u32 interrupt_pending; | |
57 | u32 interrupt_enable; | |
58 | u32 interrupt_clear; | |
59 | u32 fifo_alarm; | |
60 | }; | |
61 | ||
62 | struct mxc_data_hdd_regs { | |
63 | u32 drive_data; /* 0xa0 */ | |
64 | u32 drive_features; | |
65 | u32 drive_sector_count; | |
66 | u32 drive_sector_num; | |
67 | u32 drive_cyl_low; | |
68 | u32 drive_cyl_high; | |
69 | u32 drive_dev_head; | |
70 | u32 command; | |
71 | u32 status; | |
72 | u32 alt_status; | |
73 | }; | |
74 | ||
75 | /* PIO timing table */ | |
76 | #define NR_PIO_SPECS 5 | |
76f260d1 MV |
77 | static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 }; |
78 | static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 }; | |
76f260d1 MV |
79 | static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 }; |
80 | static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 }; | |
81 | static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 }; | |
82 | ||
83 | #define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8) | |
84 | static void set_ata_bus_timing(unsigned char mode) | |
85 | { | |
76f260d1 MV |
86 | uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); |
87 | ||
88 | struct mxc_ata_config_regs *ata_regs; | |
89 | ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; | |
90 | ||
91 | if (mode >= NR_PIO_SPECS) | |
92 | return; | |
93 | ||
94 | /* Write TIME_OFF/ON/1/2W */ | |
e063342c MV |
95 | writeb(3, &ata_regs->time_off); |
96 | writeb(3, &ata_regs->time_on); | |
97 | writeb((pio_t1[mode] + T) / T, &ata_regs->time_1); | |
98 | writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w); | |
76f260d1 MV |
99 | |
100 | /* Write TIME_2R/AX/RDX/4 */ | |
e063342c MV |
101 | writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r); |
102 | writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax); | |
103 | writeb(1, &ata_regs->time_pio_rdx); | |
104 | writeb((pio_t4[mode] + T) / T, &ata_regs->time_4); | |
76f260d1 MV |
105 | |
106 | /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ | |
e063342c | 107 | writeb((pio_t9[mode] + T) / T, &ata_regs->time_9); |
76f260d1 MV |
108 | } |
109 | ||
110 | int ide_preinit(void) | |
111 | { | |
112 | struct mxc_ata_config_regs *ata_regs; | |
113 | ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; | |
114 | ||
115 | /* 46.3.3.4 @ FSL iMX51 manual */ | |
116 | /* FIFO normal op., drive reset */ | |
117 | writel(0x80, &ata_regs->ata_control); | |
118 | /* FIFO normal op., drive not reset */ | |
119 | writel(0xc0, &ata_regs->ata_control); | |
120 | ||
121 | /* Configure the PIO timing */ | |
122 | set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE); | |
123 | ||
124 | /* 46.3.3.4 @ FSL iMX51 manual */ | |
125 | /* Drive not reset, IORDY handshake */ | |
126 | writel(0x41, &ata_regs->ata_control); | |
127 | ||
128 | return 0; | |
129 | } |