]> git.ipfire.org Git - people/ms/linux.git/blame - drivers/ata/pata_amd.c
[PATCH] pata_it821x: Suspend/Resume support
[people/ms/linux.git] / drivers / ata / pata_amd.c
CommitLineData
669a5db4
JG
1/*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_amd"
c961922b 28#define DRV_VERSION "0.2.4"
669a5db4
JG
29
30/**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45{
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
119}
120
121/**
122 * amd_probe_init - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. The BIOS stores this in PCI config
126 * space for us.
127 */
128
129static int amd_pre_reset(struct ata_port *ap)
130{
131 static const u32 bitmask[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
135 };
136
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 u8 ata66;
85cd7251 139
c961922b
AC
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
141 return -ENOENT;
669a5db4
JG
142
143 pci_read_config_byte(pdev, 0x42, &ata66);
144 if (ata66 & bitmask[ap->port_no])
145 ap->cbl = ATA_CBL_PATA80;
146 else
147 ap->cbl = ATA_CBL_PATA40;
148 return ata_std_prereset(ap);
149
150}
151
152static void amd_error_handler(struct ata_port *ap)
153{
154 return ata_bmdma_drive_eh(ap, amd_pre_reset,
155 ata_std_softreset, NULL,
156 ata_std_postreset);
157}
158
159static int amd_early_pre_reset(struct ata_port *ap)
160{
161 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
162 static struct pci_bits amd_enable_bits[] = {
163 { 0x40, 1, 0x02, 0x02 },
164 { 0x40, 1, 0x01, 0x01 }
165 };
166
c961922b
AC
167 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
168 return -ENOENT;
169
669a5db4
JG
170 /* No host side cable detection */
171 ap->cbl = ATA_CBL_PATA80;
172 return ata_std_prereset(ap);
173
174}
175
176static void amd_early_error_handler(struct ata_port *ap)
177{
178 ata_bmdma_drive_eh(ap, amd_early_pre_reset,
179 ata_std_softreset, NULL,
180 ata_std_postreset);
181}
182
183/**
184 * amd33_set_piomode - set initial PIO mode data
185 * @ap: ATA interface
186 * @adev: ATA device
187 *
188 * Program the AMD registers for PIO mode.
189 */
190
191static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
192{
193 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
194}
195
196static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
197{
198 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
199}
200
201static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
202{
203 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
204}
205
206static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
207{
208 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
209}
210
211/**
212 * amd33_set_dmamode - set initial DMA mode data
213 * @ap: ATA interface
214 * @adev: ATA device
215 *
216 * Program the MWDMA/UDMA modes for the AMD and Nvidia
217 * chipset.
218 */
219
220static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
221{
222 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
223}
224
225static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
226{
227 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
228}
229
230static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
231{
232 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
233}
234
235static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
236{
237 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
238}
239
240
241/**
242 * nv_probe_init - cable detection
243 * @ap: ATA port
244 *
245 * Perform cable detection. The BIOS stores this in PCI config
246 * space for us.
247 */
248
249static int nv_pre_reset(struct ata_port *ap) {
250 static const u8 bitmask[2] = {0x03, 0xC0};
76ff3c6e
AC
251 static const struct pci_bits nv_enable_bits[] = {
252 { 0x50, 1, 0x02, 0x02 },
253 { 0x50, 1, 0x01, 0x01 }
254 };
669a5db4
JG
255
256 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
257 u8 ata66;
258 u16 udma;
259
c961922b
AC
260 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
261 return -ENOENT;
76ff3c6e 262
669a5db4
JG
263 pci_read_config_byte(pdev, 0x52, &ata66);
264 if (ata66 & bitmask[ap->port_no])
265 ap->cbl = ATA_CBL_PATA80;
266 else
267 ap->cbl = ATA_CBL_PATA40;
268
269 /* We now have to double check because the Nvidia boxes BIOS
270 doesn't always set the cable bits but does set mode bits */
271
272 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
273 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
274 ap->cbl = ATA_CBL_PATA80;
275 return ata_std_prereset(ap);
276}
277
278static void nv_error_handler(struct ata_port *ap)
279{
280 ata_bmdma_drive_eh(ap, nv_pre_reset,
281 ata_std_softreset, NULL,
282 ata_std_postreset);
283}
284/**
285 * nv100_set_piomode - set initial PIO mode data
286 * @ap: ATA interface
287 * @adev: ATA device
288 *
289 * Program the AMD registers for PIO mode.
290 */
291
292static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
293{
294 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
295}
296
297static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
298{
299 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
300}
301
302/**
303 * nv100_set_dmamode - set initial DMA mode data
304 * @ap: ATA interface
305 * @adev: ATA device
306 *
307 * Program the MWDMA/UDMA modes for the AMD and Nvidia
308 * chipset.
309 */
310
311static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
312{
313 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
314}
315
316static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
317{
318 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
319}
320
321static struct scsi_host_template amd_sht = {
322 .module = THIS_MODULE,
323 .name = DRV_NAME,
324 .ioctl = ata_scsi_ioctl,
325 .queuecommand = ata_scsi_queuecmd,
326 .can_queue = ATA_DEF_QUEUE,
327 .this_id = ATA_SHT_THIS_ID,
328 .sg_tablesize = LIBATA_MAX_PRD,
329 .max_sectors = ATA_MAX_SECTORS,
330 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
331 .emulated = ATA_SHT_EMULATED,
332 .use_clustering = ATA_SHT_USE_CLUSTERING,
333 .proc_name = DRV_NAME,
334 .dma_boundary = ATA_DMA_BOUNDARY,
335 .slave_configure = ata_scsi_slave_config,
afdfe899 336 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG
337 .bios_param = ata_std_bios_param,
338};
339
340static struct ata_port_operations amd33_port_ops = {
341 .port_disable = ata_port_disable,
342 .set_piomode = amd33_set_piomode,
343 .set_dmamode = amd33_set_dmamode,
344 .mode_filter = ata_pci_default_filter,
345 .tf_load = ata_tf_load,
346 .tf_read = ata_tf_read,
347 .check_status = ata_check_status,
348 .exec_command = ata_exec_command,
349 .dev_select = ata_std_dev_select,
350
351 .freeze = ata_bmdma_freeze,
352 .thaw = ata_bmdma_thaw,
353 .error_handler = amd_early_error_handler,
354 .post_internal_cmd = ata_bmdma_post_internal_cmd,
355
356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
bda30288 363
669a5db4
JG
364 .data_xfer = ata_pio_data_xfer,
365
366 .irq_handler = ata_interrupt,
367 .irq_clear = ata_bmdma_irq_clear,
368
369 .port_start = ata_port_start,
370 .port_stop = ata_port_stop,
371 .host_stop = ata_host_stop
372};
373
374static struct ata_port_operations amd66_port_ops = {
375 .port_disable = ata_port_disable,
376 .set_piomode = amd66_set_piomode,
377 .set_dmamode = amd66_set_dmamode,
378 .mode_filter = ata_pci_default_filter,
379 .tf_load = ata_tf_load,
380 .tf_read = ata_tf_read,
381 .check_status = ata_check_status,
382 .exec_command = ata_exec_command,
383 .dev_select = ata_std_dev_select,
384
385 .freeze = ata_bmdma_freeze,
386 .thaw = ata_bmdma_thaw,
387 .error_handler = amd_early_error_handler,
388 .post_internal_cmd = ata_bmdma_post_internal_cmd,
389
390 .bmdma_setup = ata_bmdma_setup,
391 .bmdma_start = ata_bmdma_start,
392 .bmdma_stop = ata_bmdma_stop,
393 .bmdma_status = ata_bmdma_status,
394
395 .qc_prep = ata_qc_prep,
396 .qc_issue = ata_qc_issue_prot,
bda30288 397
669a5db4
JG
398 .data_xfer = ata_pio_data_xfer,
399
400 .irq_handler = ata_interrupt,
401 .irq_clear = ata_bmdma_irq_clear,
402
403 .port_start = ata_port_start,
404 .port_stop = ata_port_stop,
405 .host_stop = ata_host_stop
406};
407
408static struct ata_port_operations amd100_port_ops = {
409 .port_disable = ata_port_disable,
410 .set_piomode = amd100_set_piomode,
411 .set_dmamode = amd100_set_dmamode,
412 .mode_filter = ata_pci_default_filter,
413 .tf_load = ata_tf_load,
414 .tf_read = ata_tf_read,
415 .check_status = ata_check_status,
416 .exec_command = ata_exec_command,
417 .dev_select = ata_std_dev_select,
418
419 .freeze = ata_bmdma_freeze,
420 .thaw = ata_bmdma_thaw,
421 .error_handler = amd_error_handler,
422 .post_internal_cmd = ata_bmdma_post_internal_cmd,
423
424 .bmdma_setup = ata_bmdma_setup,
425 .bmdma_start = ata_bmdma_start,
426 .bmdma_stop = ata_bmdma_stop,
427 .bmdma_status = ata_bmdma_status,
428
429 .qc_prep = ata_qc_prep,
430 .qc_issue = ata_qc_issue_prot,
bda30288 431
669a5db4
JG
432 .data_xfer = ata_pio_data_xfer,
433
434 .irq_handler = ata_interrupt,
435 .irq_clear = ata_bmdma_irq_clear,
436
437 .port_start = ata_port_start,
438 .port_stop = ata_port_stop,
439 .host_stop = ata_host_stop
440};
441
442static struct ata_port_operations amd133_port_ops = {
443 .port_disable = ata_port_disable,
444 .set_piomode = amd133_set_piomode,
445 .set_dmamode = amd133_set_dmamode,
446 .mode_filter = ata_pci_default_filter,
447 .tf_load = ata_tf_load,
448 .tf_read = ata_tf_read,
449 .check_status = ata_check_status,
450 .exec_command = ata_exec_command,
451 .dev_select = ata_std_dev_select,
452
453 .freeze = ata_bmdma_freeze,
454 .thaw = ata_bmdma_thaw,
455 .error_handler = amd_error_handler,
456 .post_internal_cmd = ata_bmdma_post_internal_cmd,
457
458 .bmdma_setup = ata_bmdma_setup,
459 .bmdma_start = ata_bmdma_start,
460 .bmdma_stop = ata_bmdma_stop,
461 .bmdma_status = ata_bmdma_status,
462
463 .qc_prep = ata_qc_prep,
464 .qc_issue = ata_qc_issue_prot,
bda30288 465
669a5db4
JG
466 .data_xfer = ata_pio_data_xfer,
467
468 .irq_handler = ata_interrupt,
469 .irq_clear = ata_bmdma_irq_clear,
470
471 .port_start = ata_port_start,
472 .port_stop = ata_port_stop,
473 .host_stop = ata_host_stop
474};
475
476static struct ata_port_operations nv100_port_ops = {
477 .port_disable = ata_port_disable,
478 .set_piomode = nv100_set_piomode,
479 .set_dmamode = nv100_set_dmamode,
480 .mode_filter = ata_pci_default_filter,
481 .tf_load = ata_tf_load,
482 .tf_read = ata_tf_read,
483 .check_status = ata_check_status,
484 .exec_command = ata_exec_command,
485 .dev_select = ata_std_dev_select,
486
487 .freeze = ata_bmdma_freeze,
488 .thaw = ata_bmdma_thaw,
489 .error_handler = nv_error_handler,
490 .post_internal_cmd = ata_bmdma_post_internal_cmd,
491
492 .bmdma_setup = ata_bmdma_setup,
493 .bmdma_start = ata_bmdma_start,
494 .bmdma_stop = ata_bmdma_stop,
495 .bmdma_status = ata_bmdma_status,
496
497 .qc_prep = ata_qc_prep,
498 .qc_issue = ata_qc_issue_prot,
bda30288 499
669a5db4
JG
500 .data_xfer = ata_pio_data_xfer,
501
502 .irq_handler = ata_interrupt,
503 .irq_clear = ata_bmdma_irq_clear,
504
505 .port_start = ata_port_start,
506 .port_stop = ata_port_stop,
507 .host_stop = ata_host_stop
508};
509
510static struct ata_port_operations nv133_port_ops = {
511 .port_disable = ata_port_disable,
512 .set_piomode = nv133_set_piomode,
513 .set_dmamode = nv133_set_dmamode,
514 .mode_filter = ata_pci_default_filter,
515 .tf_load = ata_tf_load,
516 .tf_read = ata_tf_read,
517 .check_status = ata_check_status,
518 .exec_command = ata_exec_command,
519 .dev_select = ata_std_dev_select,
520
521 .freeze = ata_bmdma_freeze,
522 .thaw = ata_bmdma_thaw,
523 .error_handler = nv_error_handler,
524 .post_internal_cmd = ata_bmdma_post_internal_cmd,
525
526 .bmdma_setup = ata_bmdma_setup,
527 .bmdma_start = ata_bmdma_start,
528 .bmdma_stop = ata_bmdma_stop,
529 .bmdma_status = ata_bmdma_status,
530
531 .qc_prep = ata_qc_prep,
532 .qc_issue = ata_qc_issue_prot,
bda30288 533
669a5db4
JG
534 .data_xfer = ata_pio_data_xfer,
535
536 .irq_handler = ata_interrupt,
537 .irq_clear = ata_bmdma_irq_clear,
538
539 .port_start = ata_port_start,
540 .port_stop = ata_port_stop,
541 .host_stop = ata_host_stop
542};
543
544static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
545{
546 static struct ata_port_info info[10] = {
547 { /* 0: AMD 7401 */
548 .sht = &amd_sht,
549 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
550 .pio_mask = 0x1f,
551 .mwdma_mask = 0x07, /* No SWDMA */
552 .udma_mask = 0x07, /* UDMA 33 */
553 .port_ops = &amd33_port_ops
554 },
555 { /* 1: Early AMD7409 - no swdma */
556 .sht = &amd_sht,
557 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
558 .pio_mask = 0x1f,
559 .mwdma_mask = 0x07,
560 .udma_mask = 0x1f, /* UDMA 66 */
561 .port_ops = &amd66_port_ops
562 },
563 { /* 2: AMD 7409, no swdma errata */
564 .sht = &amd_sht,
565 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
566 .pio_mask = 0x1f,
567 .mwdma_mask = 0x07,
568 .udma_mask = 0x1f, /* UDMA 66 */
569 .port_ops = &amd66_port_ops
570 },
571 { /* 3: AMD 7411 */
572 .sht = &amd_sht,
573 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
574 .pio_mask = 0x1f,
575 .mwdma_mask = 0x07,
576 .udma_mask = 0x3f, /* UDMA 100 */
577 .port_ops = &amd100_port_ops
578 },
579 { /* 4: AMD 7441 */
580 .sht = &amd_sht,
581 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
582 .pio_mask = 0x1f,
583 .mwdma_mask = 0x07,
584 .udma_mask = 0x3f, /* UDMA 100 */
585 .port_ops = &amd100_port_ops
586 },
587 { /* 5: AMD 8111*/
588 .sht = &amd_sht,
589 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
590 .pio_mask = 0x1f,
591 .mwdma_mask = 0x07,
592 .udma_mask = 0x7f, /* UDMA 133, no swdma */
593 .port_ops = &amd133_port_ops
594 },
595 { /* 6: AMD 8111 UDMA 100 (Serenade) */
596 .sht = &amd_sht,
597 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
598 .pio_mask = 0x1f,
599 .mwdma_mask = 0x07,
600 .udma_mask = 0x3f, /* UDMA 100, no swdma */
601 .port_ops = &amd133_port_ops
602 },
603 { /* 7: Nvidia Nforce */
604 .sht = &amd_sht,
605 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
606 .pio_mask = 0x1f,
607 .mwdma_mask = 0x07,
608 .udma_mask = 0x3f, /* UDMA 100 */
609 .port_ops = &nv100_port_ops
610 },
611 { /* 8: Nvidia Nforce2 and later */
612 .sht = &amd_sht,
613 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
614 .pio_mask = 0x1f,
615 .mwdma_mask = 0x07,
616 .udma_mask = 0x7f, /* UDMA 133, no swdma */
617 .port_ops = &nv133_port_ops
618 },
619 { /* 9: AMD CS5536 (Geode companion) */
620 .sht = &amd_sht,
621 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
622 .pio_mask = 0x1f,
623 .mwdma_mask = 0x07,
624 .udma_mask = 0x3f, /* UDMA 100 */
625 .port_ops = &amd100_port_ops
626 }
627 };
628 static struct ata_port_info *port_info[2];
629 static int printed_version;
630 int type = id->driver_data;
631 u8 rev;
632 u8 fifo;
633
634 if (!printed_version++)
635 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
636
637 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
638 pci_read_config_byte(pdev, 0x41, &fifo);
639
640 /* Check for AMD7409 without swdma errata and if found adjust type */
641 if (type == 1 && rev > 0x7)
642 type = 2;
643
644 /* Check for AMD7411 */
645 if (type == 3)
646 /* FIFO is broken */
647 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
648 else
649 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
650
651 /* Serenade ? */
652 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
653 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
654 type = 6; /* UDMA 100 only */
655
656 if (type < 3)
657 ata_pci_clear_simplex(pdev);
658
659 /* And fire it up */
660
661 port_info[0] = port_info[1] = &info[type];
662 return ata_pci_init_one(pdev, port_info, 2);
663}
664
665static const struct pci_device_id amd[] = {
2d2744fc
JG
666 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
667 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
668 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
669 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
670 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
671 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
672 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
673 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
674 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
675 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
676 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
677 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
678 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
679 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
680 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
05e2867a
PC
681 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
682 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
2d2744fc
JG
683 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
684
685 { },
669a5db4
JG
686};
687
688static struct pci_driver amd_pci_driver = {
2d2744fc 689 .name = DRV_NAME,
669a5db4
JG
690 .id_table = amd,
691 .probe = amd_init_one,
692 .remove = ata_pci_remove_one
693};
694
695static int __init amd_init(void)
696{
697 return pci_register_driver(&amd_pci_driver);
698}
699
700static void __exit amd_exit(void)
701{
702 pci_unregister_driver(&amd_pci_driver);
703}
704
669a5db4
JG
705MODULE_AUTHOR("Alan Cox");
706MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
707MODULE_LICENSE("GPL");
708MODULE_DEVICE_TABLE(pci, amd);
709MODULE_VERSION(DRV_VERSION);
710
711module_init(amd_init);
712module_exit(amd_exit);