[people/ms/linux.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Maybe PLL mode
 *	Look into engine reset on timeout errors. Should not be
 *		required.
 */


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.6.8"

struct hpt_clock {
	u8	xfer_mode;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *        register access.
 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 *        register access.
 * 28     UDMA enable.
 * 29     DMA  enable.
 * 30     PIO_MST enable. If set, the chip is in bus master mode during
 *        PIO xfer.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
{
	unsigned char model_num[ATA_ID_PROD_LEN + 1];
	int i = 0;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	while (list[i] != NULL) {
		if (!strcmp(list[i], model_num)) {
			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
				modestr, list[i]);
			return 1;
		}
		i++;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */

static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
	} else if (adev->class == ATA_DEV_ATAPI)
		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);

	return ata_bmdma_mode_filter(adev, mask);
}

static int hpt36x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	/*
	 * Each channel of pata_hpt366 occupies separate PCI function
	 * as the primary channel and bit1 indicates the cable type.
	 */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & 2)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
			    u8 mode)
{
	struct hpt_clock *clocks = ap->host->private_data;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr = 0x40 + 4 * adev->devno;
	u32 mask, reg;

	/* determine timing mask and find matching clock entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xc1f8ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x303800ff;
	else
		mask = 0x30070000;

	while (clocks->xfer_mode) {
		if (clocks->xfer_mode == mode)
			break;
		clocks++;
	}
	if (!clocks->xfer_mode)
		BUG();

	/*
	 * Combine new mode bits with old config bits and disable
	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	 * problems handling I/O errors later.
	 */
	pci_read_config_dword(pdev, addr, &reg);
	reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
	pci_write_config_dword(pdev, addr, reg);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */

static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->dma_mode);
}

static struct scsi_host_template hpt36x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT366/68
 */

static struct ata_port_operations hpt366_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= hpt36x_cable_detect,
	.mode_filter	= hpt366_filter,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
};

/**
 *	hpt36x_init_chipset	-	common chip setup
 *	@dev: PCI device
 *
 *	Perform the chip setup work that must be done at both init and
 *	resume time
 */

static void hpt36x_init_chipset(struct pci_dev *dev)
{
	u8 drive_fast;
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
}

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */

static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_hpt366 = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &hpt366_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };

	void *hpriv = NULL;
	u32 reg1;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (dev->revision > 2)
		return -ENODEV;

	hpt36x_init_chipset(dev);

	pci_read_config_dword(dev, 0x40,  &reg1);

	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch((reg1 & 0x700) >> 8) {
		case 9:
			hpriv = &hpt366_40;
			break;
		case 5:
			hpriv = &hpt366_25;
			break;
		default:
			hpriv = &hpt366_33;
			break;
	}
	/* Now kick off ATA set up */
	return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
}

#ifdef CONFIG_PM
static int hpt36x_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = dev_get_drvdata(&dev->dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;
	hpt36x_init_chipset(dev);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt36x[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ },
};

static struct pci_driver hpt36x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= hpt36x,
	.probe 		= hpt36x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt36x_reinit_one,
#endif
};

static int __init hpt36x_init(void)
{
	return pci_register_driver(&hpt36x_pci_driver);
}

static void __exit hpt36x_exit(void)
{
	pci_unregister_driver(&hpt36x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);

module_init(hpt36x_init);
module_exit(hpt36x_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
	14	* Maybe PLL mode
	15	* Look into engine reset on timeout errors. Should not be
	16	* required.
	17	*/
	18
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/pci.h>
	23	#include <linux/init.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/delay.h>
	26	#include <scsi/scsi_host.h>
	27	#include <linux/libata.h>
	28
	29	#define DRV_NAME "pata_hpt366"
859faa87	30	#define DRV_VERSION "0.6.8"
669a5db4 JG	31
669a5db4 JG	32	struct hpt_clock {
6ecb6f25	33	u8 xfer_mode;
669a5db4 JG	34	u32 timing;
	35	};
	36
	37	/* key for bus clock timings
	38	* bit
82beb5d8 SS	39	* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
	40	* cycles = value + 1
	41	* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
	42	* cycles = value + 1
	43	* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
669a5db4	44	* register access.
82beb5d8	45	* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
669a5db4	46	* register access.
82beb5d8 SS	47	* 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
	48	* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
	49	* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
669a5db4	50	* register access.
82beb5d8 SS	51	* 28 UDMA enable.
	52	* 29 DMA enable.
	53	* 30 PIO_MST enable. If set, the chip is in bus master mode during
	54	* PIO xfer.
669a5db4 JG	55	* 31 FIFO enable.
	56	*/
	57
	58	static const struct hpt_clock hpt366_40[] = {
	59	{ XFER_UDMA_4, 0x900fd943 },
	60	{ XFER_UDMA_3, 0x900ad943 },
	61	{ XFER_UDMA_2, 0x900bd943 },
	62	{ XFER_UDMA_1, 0x9008d943 },
	63	{ XFER_UDMA_0, 0x9008d943 },
	64
	65	{ XFER_MW_DMA_2, 0xa008d943 },
	66	{ XFER_MW_DMA_1, 0xa010d955 },
	67	{ XFER_MW_DMA_0, 0xa010d9fc },
	68
	69	{ XFER_PIO_4, 0xc008d963 },
	70	{ XFER_PIO_3, 0xc010d974 },
	71	{ XFER_PIO_2, 0xc010d997 },
	72	{ XFER_PIO_1, 0xc010d9c7 },
	73	{ XFER_PIO_0, 0xc018d9d9 },
	74	{ 0, 0x0120d9d9 }
	75	};
	76
	77	static const struct hpt_clock hpt366_33[] = {
	78	{ XFER_UDMA_4, 0x90c9a731 },
	79	{ XFER_UDMA_3, 0x90cfa731 },
	80	{ XFER_UDMA_2, 0x90caa731 },
	81	{ XFER_UDMA_1, 0x90cba731 },
	82	{ XFER_UDMA_0, 0x90c8a731 },
	83
	84	{ XFER_MW_DMA_2, 0xa0c8a731 },
	85	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
	86	{ XFER_MW_DMA_0, 0xa0c8a797 },
	87
	88	{ XFER_PIO_4, 0xc0c8a731 },
	89	{ XFER_PIO_3, 0xc0c8a742 },
	90	{ XFER_PIO_2, 0xc0d0a753 },
	91	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
	92	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
	93	{ 0, 0x0120a7a7 }
	94	};
	95
	96	static const struct hpt_clock hpt366_25[] = {
	97	{ XFER_UDMA_4, 0x90c98521 },
	98	{ XFER_UDMA_3, 0x90cf8521 },
	99	{ XFER_UDMA_2, 0x90cf8521 },
	100	{ XFER_UDMA_1, 0x90cb8521 },
	101	{ XFER_UDMA_0, 0x90cb8521 },
	102
	103	{ XFER_MW_DMA_2, 0xa0ca8521 },
	104	{ XFER_MW_DMA_1, 0xa0ca8532 },
	105	{ XFER_MW_DMA_0, 0xa0ca8575 },
	106
	107	{ XFER_PIO_4, 0xc0ca8521 },
	108	{ XFER_PIO_3, 0xc0ca8532 },
	109	{ XFER_PIO_2, 0xc0ca8542 },
	110	{ XFER_PIO_1, 0xc0d08572 },
	111	{ XFER_PIO_0, 0xc0d08585 },
	112	{ 0, 0x01208585 }
	113	};
	114
	115	static const char *bad_ata33[] = {
	116	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	117	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	118	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
119	"Maxtor 90510D4",
120	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
121	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
122	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
123	NULL
124	};
125
126	static const char *bad_ata66_4[] = {
127	"IBM-DTLA-307075",
128	"IBM-DTLA-307060",
129	"IBM-DTLA-307045",
130	"IBM-DTLA-307030",
131	"IBM-DTLA-307020",
132	"IBM-DTLA-307015",
133	"IBM-DTLA-305040",
134	"IBM-DTLA-305030",
135	"IBM-DTLA-305020",
136	"IC35L010AVER07-0",
137	"IC35L020AVER07-0",
138	"IC35L030AVER07-0",
139	"IC35L040AVER07-0",
140	"IC35L060AVER07-0",
141	"WDC AC310200R",
142	NULL
143	};
144
145	static const char *bad_ata66_3[] = {
146	"WDC AC310200R",
147	NULL
148	};
149
150	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr, const char *list[])
151	{
8bfa79fc	152	unsigned char model_num[ATA_ID_PROD_LEN + 1];
669a5db4 JG	153	int i = 0;
669a5db4 JG	154
8bfa79fc	155	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4	156
8bfa79fc TH	157	while (list[i] != NULL) {
8bfa79fc TH	158	if (!strcmp(list[i], model_num)) {
85cd7251	159	printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
669a5db4 JG	160	modestr, list[i]);
	161	return 1;
	162	}
	163	i++;
	164	}
	165	return 0;
	166	}
	167
	168	/**
	169	* hpt366_filter - mode selection filter
669a5db4 JG	170	* @adev: ATA device
	171	*
	172	* Block UDMA on devices that cause trouble with this controller.
	173	*/
85cd7251	174
a76b62ca	175	static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	176	{
	177	if (adev->class == ATA_DEV_ATA) {
	178	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
	179	mask &= ~ATA_MASK_UDMA;
	180	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
6ddd6861	181	mask &= ~(0xF8 << ATA_SHIFT_UDMA);
669a5db4	182	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
6ddd6861	183	mask &= ~(0xF0 << ATA_SHIFT_UDMA);
3ee89f17 TH	184	} else if (adev->class == ATA_DEV_ATAPI)
	185	mask &= ~(ATA_MASK_MWDMA \| ATA_MASK_UDMA);
	186
9363c382	187	return ata_bmdma_mode_filter(adev, mask);
669a5db4 JG	188	}
669a5db4 JG	189
fecfda5d AC	190	static int hpt36x_cable_detect(struct ata_port *ap)
fecfda5d AC	191	{
fecfda5d	192	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
bab5b32a	193	u8 ata66;
fecfda5d	194
bab5b32a TH	195	/*
	196	* Each channel of pata_hpt366 occupies separate PCI function
	197	* as the primary channel and bit1 indicates the cable type.
	198	*/
fecfda5d	199	pci_read_config_byte(pdev, 0x5A, &ata66);
bab5b32a	200	if (ata66 & 2)
fecfda5d AC	201	return ATA_CBL_PATA40;
	202	return ATA_CBL_PATA80;
	203	}
	204
6ecb6f25 TH	205	static void hpt366_set_mode(struct ata_port ap, struct ata_device adev,
6ecb6f25 TH	206	u8 mode)
669a5db4	207	{
6ecb6f25	208	struct hpt_clock *clocks = ap->host->private_data;
669a5db4	209	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
859faa87	210	u32 addr = 0x40 + 4 * adev->devno;
6ecb6f25	211	u32 mask, reg;
85cd7251	212
6ecb6f25 TH	213	/* determine timing mask and find matching clock entry */
	214	if (mode < XFER_MW_DMA_0)
	215	mask = 0xc1f8ffff;
	216	else if (mode < XFER_UDMA_0)
	217	mask = 0x303800ff;
	218	else
	219	mask = 0x30070000;
	220
	221	while (clocks->xfer_mode) {
	222	if (clocks->xfer_mode == mode)
	223	break;
	224	clocks++;
	225	}
	226	if (!clocks->xfer_mode)
	227	BUG();
	228
	229	/*
	230	* Combine new mode bits with old config bits and disable
	231	* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	232	* problems handling I/O errors later.
	233	*/
859faa87	234	pci_read_config_dword(pdev, addr, &reg);
6ecb6f25	235	reg = ((reg & ~mask) \| (clocks->timing & mask)) & ~0xc0000000;
859faa87	236	pci_write_config_dword(pdev, addr, reg);
6ecb6f25 TH	237	}
	238
	239	/**
	240	* hpt366_set_piomode - PIO setup
	241	* @ap: ATA interface
	242	* @adev: device on the interface
	243	*
	244	* Perform PIO mode setup.
	245	*/
	246
	247	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
	248	{
	249	hpt366_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	250	}
	251
	252	/**
	253	* hpt366_set_dmamode - DMA timing setup
	254	* @ap: ATA interface
	255	* @adev: Device being configured
	256	*
	257	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	258	* PIO, load the mode number and then set MWDMA or UDMA flag.
	259	*/
85cd7251	260
669a5db4 JG	261	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	262	{
6ecb6f25	263	hpt366_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	264	}
	265
	266	static struct scsi_host_template hpt36x_sht = {
68d1d07b	267	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	268	};
	269
	270	/*
	271	* Configuration for HPT366/68
	272	*/
85cd7251	273
669a5db4	274	static struct ata_port_operations hpt366_port_ops = {
029cfd6b TH	275	.inherits = &ata_bmdma_port_ops,
	276	.cable_detect = hpt36x_cable_detect,
	277	.mode_filter = hpt366_filter,
669a5db4 JG	278	.set_piomode = hpt366_set_piomode,
669a5db4 JG	279	.set_dmamode = hpt366_set_dmamode,
85cd7251	280	};
669a5db4	281
aa54ab1e AC	282	/**
	283	* hpt36x_init_chipset - common chip setup
	284	* @dev: PCI device
	285	*
	286	* Perform the chip setup work that must be done at both init and
	287	* resume time
	288	*/
	289
	290	static void hpt36x_init_chipset(struct pci_dev *dev)
	291	{
	292	u8 drive_fast;
	293	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	294	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	295	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	296	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	297
	298	pci_read_config_byte(dev, 0x51, &drive_fast);
	299	if (drive_fast & 0x80)
	300	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	301	}
	302
669a5db4 JG	303	/**
	304	* hpt36x_init_one - Initialise an HPT366/368
	305	* @dev: PCI device
	306	* @id: Entry in match table
	307	*
	308	* Initialise an HPT36x device. There are some interesting complications
	309	* here. Firstly the chip may report 366 and be one of several variants.
	310	* Secondly all the timings depend on the clock for the chip which we must
	311	* detect and look up
	312	*
	313	* This is the known chip mappings. It may be missing a couple of later
	314	* releases.
	315	*
	316	* Chip version PCI Rev Notes
	317	* HPT366 4 (HPT366) 0 UDMA66
	318	* HPT366 4 (HPT366) 1 UDMA66
	319	* HPT368 4 (HPT366) 2 UDMA66
	320	* HPT37x/30x 4 (HPT366) 3+ Other driver
	321	*
	322	*/
85cd7251	323
669a5db4 JG	324	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	325	{
1626aeb8	326	static const struct ata_port_info info_hpt366 = {
1d2808fd	327	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	328	.pio_mask = ATA_PIO4,
14bdef98 EIB	329	.mwdma_mask = ATA_MWDMA2,
bf6263a8	330	.udma_mask = ATA_UDMA4,
669a5db4 JG	331	.port_ops = &hpt366_port_ops
669a5db4 JG	332	};
887125e3	333	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
669a5db4	334
887125e3	335	void *hpriv = NULL;
669a5db4	336	u32 reg1;
f08048e9 TH	337	int rc;
	338
	339	rc = pcim_enable_device(dev);
	340	if (rc)
	341	return rc;
669a5db4	342
669a5db4 JG	343	/* May be a later chip in disguise. Check */
669a5db4 JG	344	/* Newer chips are not in the HPT36x driver. Ignore them */
89d3b360 SS	345	if (dev->revision > 2)
89d3b360 SS	346	return -ENODEV;
669a5db4	347
aa54ab1e	348	hpt36x_init_chipset(dev);
669a5db4 JG	349
669a5db4 JG	350	pci_read_config_dword(dev, 0x40, &reg1);
85cd7251	351
669a5db4 JG	352	/* PCI clocking determines the ATA timing values to use */
669a5db4 JG	353	/* info_hpt366 is safe against re-entry so we can scribble on it */
2c136efc	354	switch((reg1 & 0x700) >> 8) {
2456eb81	355	case 9:
887125e3	356	hpriv = &hpt366_40;
669a5db4	357	break;
2456eb81	358	case 5:
887125e3	359	hpriv = &hpt366_25;
669a5db4 JG	360	break;
669a5db4 JG	361	default:
887125e3	362	hpriv = &hpt366_33;
669a5db4 JG	363	break;
	364	}
	365	/* Now kick off ATA set up */
9363c382	366	return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
669a5db4 JG	367	}
669a5db4 JG	368
438ac6d5	369	#ifdef CONFIG_PM
aa54ab1e AC	370	static int hpt36x_reinit_one(struct pci_dev *dev)
aa54ab1e AC	371	{
f08048e9 TH	372	struct ata_host *host = dev_get_drvdata(&dev->dev);
	373	int rc;
	374
	375	rc = ata_pci_device_do_resume(dev);
	376	if (rc)
	377	return rc;
aa54ab1e	378	hpt36x_init_chipset(dev);
f08048e9 TH	379	ata_host_resume(host);
f08048e9 TH	380	return 0;
aa54ab1e	381	}
438ac6d5	382	#endif
aa54ab1e	383
2d2744fc JG	384	static const struct pci_device_id hpt36x[] = {
2d2744fc JG	385	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
2d2744fc	386	{ },
669a5db4 JG	387	};
	388
	389	static struct pci_driver hpt36x_pci_driver = {
2d2744fc	390	.name = DRV_NAME,
669a5db4 JG	391	.id_table = hpt36x,
669a5db4 JG	392	.probe = hpt36x_init_one,
aa54ab1e	393	.remove = ata_pci_remove_one,
438ac6d5	394	#ifdef CONFIG_PM
aa54ab1e AC	395	.suspend = ata_pci_device_suspend,
aa54ab1e AC	396	.resume = hpt36x_reinit_one,
438ac6d5	397	#endif
669a5db4 JG	398	};
	399
	400	static int __init hpt36x_init(void)
	401	{
	402	return pci_register_driver(&hpt36x_pci_driver);
	403	}
	404
669a5db4 JG	405	static void __exit hpt36x_exit(void)
	406	{
	407	pci_unregister_driver(&hpt36x_pci_driver);
	408	}
	409
669a5db4 JG	410	MODULE_AUTHOR("Alan Cox");
	411	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
	412	MODULE_LICENSE("GPL");
	413	MODULE_DEVICE_TABLE(pci, hpt36x);
	414	MODULE_VERSION(DRV_VERSION);
	415
	416	module_init(hpt36x_init);
	417	module_exit(hpt36x_exit);