[people/ms/linux.git] / drivers / ata / pata_hpt3x2n.c

/*
 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 * Portions Copyright (C) 2005-2010	MontaVista Software, Inc.
 *
 *
 * TODO
 *	Work out best PLL policy
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt3x2n"
#define DRV_VERSION	"0.3.15"

enum {
	HPT_PCI_FAST	=	(1 << 31),
	PCI66		=	(1 << 1),
	USE_DPLL	=	(1 << 0)
};

struct hpt_clock {
	u8	xfer_speed;
	u32	timing;
};

struct hpt_chip {
	const char *name;
	struct hpt_clock *clocks[3];
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *        register access.
 * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
 * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 *        register access.
 * 28     UDMA enable.
 * 29     DMA  enable.
 * 30     PIO_MST enable. If set, the chip is in bus master mode during
 *        PIO xfer.
 * 31     FIFO enable. Only for PIO.
 */

/* 66MHz DPLL clocks */

static struct hpt_clock hpt3x2n_clocks[] = {
	{	XFER_UDMA_7,	0x1c869c62	},
	{	XFER_UDMA_6,	0x1c869c62	},
	{	XFER_UDMA_5,	0x1c8a9c62	},
	{	XFER_UDMA_4,	0x1c8a9c62	},
	{	XFER_UDMA_3,	0x1c8e9c62	},
	{	XFER_UDMA_2,	0x1c929c62	},
	{	XFER_UDMA_1,	0x1c9a9c62	},
	{	XFER_UDMA_0,	0x1c829c62	},

	{	XFER_MW_DMA_2,	0x2c829c62	},
	{	XFER_MW_DMA_1,	0x2c829c66	},
	{	XFER_MW_DMA_0,	0x2c829d2e	},

	{	XFER_PIO_4,	0x0c829c62	},
	{	XFER_PIO_3,	0x0c829c84	},
	{	XFER_PIO_2,	0x0c829ca6	},
	{	XFER_PIO_1,	0x0d029d26	},
	{	XFER_PIO_0,	0x0d029d5e	},
};

/**
 *	hpt3x2n_find_mode	-	reset the hpt3x2n bus
 *	@ap: ATA port
 *	@speed: transfer mode
 *
 *	Return the 32bit register programming information for this channel
 *	that matches the speed provided. For the moment the clocks table
 *	is hard coded but easy to change. This will be needed if we use
 *	different DPLLs
 */

static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
{
	struct hpt_clock *clocks = hpt3x2n_clocks;

	while (clocks->xfer_speed) {
		if (clocks->xfer_speed == speed)
			return clocks->timing;
		clocks++;
	}
	BUG();
	return 0xffffffffU;	/* silence compiler warning */
}

/**
 *	hpt372n_filter	-	mode selection filter
 *	@adev: ATA device
 *	@mask: mode mask
 *
 *	The Marvell bridge chips used on the HighPoint SATA cards do not seem
 *	to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
 */
static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
{
	if (ata_id_is_sata(adev->id))
		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);

	return mask;
}

/**
 *	hpt3x2n_cable_detect	-	Detect the cable type
 *	@ap: ATA port to detect on
 *
 *	Return the cable type attached to this port
 */

static int hpt3x2n_cable_detect(struct ata_port *ap)
{
	u8 scr2, ata66;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	pci_read_config_byte(pdev, 0x5B, &scr2);
	pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);

	udelay(10); /* debounce */

	/* Cable register now active */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	/* Restore state */
	pci_write_config_byte(pdev, 0x5B, scr2);

	if (ata66 & (2 >> ap->port_no))
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

/**
 *	hpt3x2n_pre_reset	-	reset the hpt3x2n bus
 *	@link: ATA link to reset
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform the initial reset handling for the 3x2n series controllers.
 *	Reset the hardware and state machine,
 */

static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	/* Reset the state machine */
	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
	udelay(100);

	return ata_sff_prereset(link, deadline);
}

static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
			     u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr1, addr2;
	u32 reg, timing, mask;
	u8 fast;

	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
	addr2 = 0x51 + 4 * ap->port_no;

	/* Fast interrupt prediction disable, hold off interrupt disable */
	pci_read_config_byte(pdev, addr2, &fast);
	fast &= ~0x07;
	pci_write_config_byte(pdev, addr2, fast);

	/* Determine timing mask and find matching mode entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xcfc3ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x31c001ff;
	else
		mask = 0x303c0000;

	timing = hpt3x2n_find_mode(ap, mode);

	pci_read_config_dword(pdev, addr1, &reg);
	reg = (reg & ~mask) | (timing & mask);
	pci_write_config_dword(pdev, addr1, reg);
}

/**
 *	hpt3x2n_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt3x2n_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt3x2n_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes.
 */

static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt3x2n_set_mode(ap, adev, adev->dma_mode);
}

/**
 *	hpt3x2n_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	Clean up after the HPT3x2n and later DMA engine
 */

static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int mscreg = 0x50 + 2 * ap->port_no;
	u8 bwsr_stat, msc_stat;

	pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
	pci_read_config_byte(pdev, mscreg, &msc_stat);
	if (bwsr_stat & (1 << ap->port_no))
		pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
	ata_bmdma_stop(qc);
}

/**
 *	hpt3x2n_set_clock	-	clock control
 *	@ap: ATA port
 *	@source: 0x21 or 0x23 for PLL or PCI sourced clock
 *
 *	Switch the ATA bus clock between the PLL and PCI clock sources
 *	while correctly isolating the bus and resetting internal logic
 *
 *	We must use the DPLL for
 *	-	writing
 *	-	second channel UDMA7 (SATA ports) or higher
 *	-	66MHz PCI
 *
 *	or we will underclock the device and get reduced performance.
 */

static void hpt3x2n_set_clock(struct ata_port *ap, int source)
{
	void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;

	/* Tristate the bus */
	iowrite8(0x80, bmdma+0x73);
	iowrite8(0x80, bmdma+0x77);

	/* Switch clock and reset channels */
	iowrite8(source, bmdma+0x7B);
	iowrite8(0xC0, bmdma+0x79);

	/* Reset state machines, avoid enabling the disabled channels */
	iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
	iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);

	/* Complete reset */
	iowrite8(0x00, bmdma+0x79);

	/* Reconnect channels to bus */
	iowrite8(0x00, bmdma+0x73);
	iowrite8(0x00, bmdma+0x77);
}

static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
{
	long flags = (long)ap->host->private_data;

	/* See if we should use the DPLL */
	if (writing)
		return USE_DPLL;	/* Needed for write */
	if (flags & PCI66)
		return USE_DPLL;	/* Needed at 66Mhz */
	return 0;
}

static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
	int rc, flags = (long)ap->host->private_data;
	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);

	/* First apply the usual rules */
	rc = ata_std_qc_defer(qc);
	if (rc != 0)
		return rc;

	if ((flags & USE_DPLL) != dpll && alt->qc_active)
		return ATA_DEFER_PORT;
	return 0;
}

static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	int flags = (long)ap->host->private_data;
	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);

	if ((flags & USE_DPLL) != dpll) {
		flags &= ~USE_DPLL;
		flags |= dpll;
		ap->host->private_data = (void *)(long)flags;

		hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
	}
	return ata_bmdma_qc_issue(qc);
}

static struct scsi_host_template hpt3x2n_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT302N/371N.
 */

static struct ata_port_operations hpt3xxn_port_ops = {
	.inherits	= &ata_bmdma_port_ops,

	.bmdma_stop	= hpt3x2n_bmdma_stop,

	.qc_defer	= hpt3x2n_qc_defer,
	.qc_issue	= hpt3x2n_qc_issue,

	.cable_detect	= hpt3x2n_cable_detect,
	.set_piomode	= hpt3x2n_set_piomode,
	.set_dmamode	= hpt3x2n_set_dmamode,
	.prereset	= hpt3x2n_pre_reset,
};

/*
 *	Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
 */

static struct ata_port_operations hpt372n_port_ops = {
	.inherits	= &hpt3xxn_port_ops,
	.mode_filter	= &hpt372n_filter,
};

/**
 *	hpt3xn_calibrate_dpll		-	Calibrate the DPLL loop
 *	@dev: PCI device
 *
 *	Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
 *	succeeds
 */

static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
{
	u8 reg5b;
	u32 reg5c;
	int tries;

	for (tries = 0; tries < 0x5000; tries++) {
		udelay(50);
		pci_read_config_byte(dev, 0x5b, &reg5b);
		if (reg5b & 0x80) {
			/* See if it stays set */
			for (tries = 0; tries < 0x1000; tries++) {
				pci_read_config_byte(dev, 0x5b, &reg5b);
				/* Failed ? */
				if ((reg5b & 0x80) == 0)
					return 0;
			}
			/* Turn off tuning, we have the DPLL set */
			pci_read_config_dword(dev, 0x5c, &reg5c);
			pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
			return 1;
		}
	}
	/* Never went stable */
	return 0;
}

static int hpt3x2n_pci_clock(struct pci_dev *pdev)
{
	unsigned long freq;
	u32 fcnt;
	unsigned long iobase = pci_resource_start(pdev, 4);

	fcnt = inl(iobase + 0x90);	/* Not PCI readable for some chips */
	if ((fcnt >> 12) != 0xABCDE) {
		int i;
		u16 sr;
		u32 total = 0;

		pr_warn("BIOS clock data not set\n");

		/* This is the process the HPT371 BIOS is reported to use */
		for (i = 0; i < 128; i++) {
			pci_read_config_word(pdev, 0x78, &sr);
			total += sr & 0x1FF;
			udelay(15);
		}
		fcnt = total / 128;
	}
	fcnt &= 0x1FF;

	freq = (fcnt * 77) / 192;

	/* Clamp to bands */
	if (freq < 40)
		return 33;
	if (freq < 45)
		return 40;
	if (freq < 55)
		return 50;
	return 66;
}

/**
 *	hpt3x2n_init_one		-	Initialise an HPT37X/302
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT3x2n device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT372			4 (HPT366)	5	Other driver
 *	HPT372N			4 (HPT366)	6	UDMA133
 *	HPT372			5 (HPT372)	1	Other driver
 *	HPT372N			5 (HPT372)	2	UDMA133
 *	HPT302			6 (HPT302)	*	Other driver
 *	HPT302N			6 (HPT302)	> 1	UDMA133
 *	HPT371			7 (HPT371)	*	Other driver
 *	HPT371N			7 (HPT371)	> 1	UDMA133
 *	HPT374			8 (HPT374)	*	Other driver
 *	HPT372N			9 (HPT372N)	*	UDMA133
 *
 *	(1) UDMA133 support depends on the bus clock
 */

static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	/* HPT372N - UDMA133 */
	static const struct ata_port_info info_hpt372n = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA6,
		.port_ops = &hpt372n_port_ops
	};
	/* HPT302N and HPT371N - UDMA133 */
	static const struct ata_port_info info_hpt3xxn = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA6,
		.port_ops = &hpt3xxn_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
	u8 rev = dev->revision;
	u8 irqmask;
	unsigned int pci_mhz;
	unsigned int f_low, f_high;
	int adjust;
	unsigned long iobase = pci_resource_start(dev, 4);
	void *hpriv = (void *)USE_DPLL;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	switch (dev->device) {
	case PCI_DEVICE_ID_TTI_HPT366:
		/* 372N if rev >= 6 */
		if (rev < 6)
			return -ENODEV;
		goto hpt372n;
	case PCI_DEVICE_ID_TTI_HPT371:
		/* 371N if rev >= 2 */
		if (rev < 2)
			return -ENODEV;
		break;
	case PCI_DEVICE_ID_TTI_HPT372:
		/* 372N if rev >= 2 */
		if (rev < 2)
			return -ENODEV;
		goto hpt372n;
	case PCI_DEVICE_ID_TTI_HPT302:
		/* 302N if rev >= 2 */
		if (rev < 2)
			return -ENODEV;
		break;
	case PCI_DEVICE_ID_TTI_HPT372N:
hpt372n:
		ppi[0] = &info_hpt372n;
		break;
	default:
		pr_err("PCI table is bogus, please report (%d)\n", dev->device);
		return -ENODEV;
	}

	/* Ok so this is a chip we support */

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x5A, &irqmask);
	irqmask &= ~0x10;
	pci_write_config_byte(dev, 0x5a, irqmask);

	/*
	 * HPT371 chips physically have only one channel, the secondary one,
	 * but the primary channel registers do exist!  Go figure...
	 * So,  we manually disable the non-existing channel here
	 * (if the BIOS hasn't done this already).
	 */
	if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
		u8 mcr1;
		pci_read_config_byte(dev, 0x50, &mcr1);
		mcr1 &= ~0x04;
		pci_write_config_byte(dev, 0x50, mcr1);
	}

	/*
	 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
	 * 50 for UDMA100. Right now we always use 66
	 */

	pci_mhz = hpt3x2n_pci_clock(dev);

	f_low = (pci_mhz * 48) / 66;	/* PCI Mhz for 66Mhz DPLL */
	f_high = f_low + 2;		/* Tolerance */

	pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
	/* PLL clock */
	pci_write_config_byte(dev, 0x5B, 0x21);

	/* Unlike the 37x we don't try jiggling the frequency */
	for (adjust = 0; adjust < 8; adjust++) {
		if (hpt3xn_calibrate_dpll(dev))
			break;
		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
	}
	if (adjust == 8) {
		pr_err("DPLL did not stabilize!\n");
		return -ENODEV;
	}

	pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);

	/*
	 * Set our private data up. We only need a few flags
	 * so we use it directly.
	 */
	if (pci_mhz > 60)
		hpriv = (void *)(PCI66 | USE_DPLL);

	/*
	 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
	 * the MISC. register to stretch the UltraDMA Tss timing.
	 * NOTE: This register is only writeable via I/O space.
	 */
	if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
		outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);

	/* Now kick off ATA set up */
	return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
}

static const struct pci_device_id hpt3x2n[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },

	{ },
};

static struct pci_driver hpt3x2n_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= hpt3x2n,
	.probe		= hpt3x2n_init_one,
	.remove		= ata_pci_remove_one
};

module_pci_driver(hpt3x2n_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt3x2n);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4	1	/*
0ca646db	2	* Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
669a5db4 JG	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
8e834c2e	11	* Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
669a5db4 JG	12	*
	13	*
	14	* TODO
669a5db4 JG	15	* Work out best PLL policy
	16	*/
	17
8d7b1c70 JP	18	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8d7b1c70 JP	19
669a5db4 JG	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/pci.h>
669a5db4 JG	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <scsi/scsi_host.h>
	26	#include <linux/libata.h>
	27
	28	#define DRV_NAME "pata_hpt3x2n"
8d7b1c70	29	#define DRV_VERSION "0.3.15"
669a5db4 JG	30
	31	enum {
	32	HPT_PCI_FAST = (1 << 31),
	33	PCI66 = (1 << 1),
	34	USE_DPLL = (1 << 0)
	35	};
	36
	37	struct hpt_clock {
	38	u8 xfer_speed;
	39	u32 timing;
	40	};
	41
	42	struct hpt_chip {
	43	const char *name;
	44	struct hpt_clock *clocks[3];
	45	};
	46
	47	/* key for bus clock timings
	48	* bit
fd5e62e2 SS	49	* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
	50	* cycles = value + 1
	51	* 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
	52	* cycles = value + 1
	53	* 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
669a5db4	54	* register access.
fd5e62e2	55	* 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
669a5db4	56	* register access.
fd5e62e2 SS	57	* 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
	58	* 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
	59	* 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
	60	* 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
669a5db4	61	* register access.
fd5e62e2 SS	62	* 28 UDMA enable.
	63	* 29 DMA enable.
	64	* 30 PIO_MST enable. If set, the chip is in bus master mode during
	65	* PIO xfer.
	66	* 31 FIFO enable. Only for PIO.
669a5db4	67	*/
85cd7251	68
669a5db4 JG	69	/* 66MHz DPLL clocks */
	70
	71	static struct hpt_clock hpt3x2n_clocks[] = {
	72	{ XFER_UDMA_7, 0x1c869c62 },
	73	{ XFER_UDMA_6, 0x1c869c62 },
	74	{ XFER_UDMA_5, 0x1c8a9c62 },
	75	{ XFER_UDMA_4, 0x1c8a9c62 },
	76	{ XFER_UDMA_3, 0x1c8e9c62 },
	77	{ XFER_UDMA_2, 0x1c929c62 },
	78	{ XFER_UDMA_1, 0x1c9a9c62 },
	79	{ XFER_UDMA_0, 0x1c829c62 },
	80
	81	{ XFER_MW_DMA_2, 0x2c829c62 },
	82	{ XFER_MW_DMA_1, 0x2c829c66 },
d413ff3e	83	{ XFER_MW_DMA_0, 0x2c829d2e },
669a5db4 JG	84
	85	{ XFER_PIO_4, 0x0c829c62 },
	86	{ XFER_PIO_3, 0x0c829c84 },
	87	{ XFER_PIO_2, 0x0c829ca6 },
	88	{ XFER_PIO_1, 0x0d029d26 },
	89	{ XFER_PIO_0, 0x0d029d5e },
669a5db4 JG	90	};
	91
	92	/**
	93	* hpt3x2n_find_mode - reset the hpt3x2n bus
	94	* @ap: ATA port
	95	* @speed: transfer mode
	96	*
	97	* Return the 32bit register programming information for this channel
	98	* that matches the speed provided. For the moment the clocks table
	99	* is hard coded but easy to change. This will be needed if we use
	100	* different DPLLs
	101	*/
85cd7251	102
669a5db4 JG	103	static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
	104	{
	105	struct hpt_clock *clocks = hpt3x2n_clocks;
85cd7251	106
b197f13b	107	while (clocks->xfer_speed) {
669a5db4 JG	108	if (clocks->xfer_speed == speed)
	109	return clocks->timing;
	110	clocks++;
	111	}
	112	BUG();
	113	return 0xffffffffU; /* silence compiler warning */
	114	}
	115
8e834c2e SS	116	/**
	117	* hpt372n_filter - mode selection filter
	118	* @adev: ATA device
	119	* @mask: mode mask
	120	*
	121	* The Marvell bridge chips used on the HighPoint SATA cards do not seem
	122	* to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
	123	*/
	124	static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
	125	{
	126	if (ata_id_is_sata(adev->id))
	127	mask &= ~((0xE << ATA_SHIFT_UDMA) \| ATA_MASK_MWDMA);
	128
	129	return mask;
	130	}
	131
669a5db4	132	/**
a0fcdc02 JG	133	* hpt3x2n_cable_detect - Detect the cable type
a0fcdc02 JG	134	* @ap: ATA port to detect on
669a5db4	135	*
a0fcdc02	136	* Return the cable type attached to this port
669a5db4	137	*/
85cd7251	138
a0fcdc02	139	static int hpt3x2n_cable_detect(struct ata_port *ap)
669a5db4 JG	140	{
	141	u8 scr2, ata66;
	142	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	143
669a5db4 JG	144	pci_read_config_byte(pdev, 0x5B, &scr2);
669a5db4 JG	145	pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
10a9c969 BZ	146
	147	udelay(10); /* debounce */
	148
669a5db4 JG	149	/* Cable register now active */
	150	pci_read_config_byte(pdev, 0x5A, &ata66);
	151	/* Restore state */
	152	pci_write_config_byte(pdev, 0x5B, scr2);
85cd7251	153
f3b1cf40	154	if (ata66 & (2 >> ap->port_no))
a0fcdc02	155	return ATA_CBL_PATA40;
669a5db4	156	else
a0fcdc02 JG	157	return ATA_CBL_PATA80;
	158	}
	159
	160	/**
	161	* hpt3x2n_pre_reset - reset the hpt3x2n bus
cc0680a5	162	* @link: ATA link to reset
28e21c8c	163	* @deadline: deadline jiffies for the operation
a0fcdc02 JG	164	*
	165	* Perform the initial reset handling for the 3x2n series controllers.
	166	* Reset the hardware and state machine,
	167	*/
669a5db4	168
a1efdaba	169	static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
a0fcdc02	170	{
cc0680a5	171	struct ata_port *ap = link->ap;
a0fcdc02	172	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
b197f13b	173
669a5db4	174	/* Reset the state machine */
28e21c8c	175	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
669a5db4	176	udelay(100);
d4b2bab4	177
9363c382	178	return ata_sff_prereset(link, deadline);
669a5db4	179	}
85cd7251	180
1a1b172b SS	181	static void hpt3x2n_set_mode(struct ata_port ap, struct ata_device adev,
1a1b172b SS	182	u8 mode)
669a5db4 JG	183	{
	184	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	185	u32 addr1, addr2;
1a1b172b	186	u32 reg, timing, mask;
669a5db4 JG	187	u8 fast;
	188
	189	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
	190	addr2 = 0x51 + 4 * ap->port_no;
85cd7251	191
669a5db4 JG	192	/* Fast interrupt prediction disable, hold off interrupt disable */
	193	pci_read_config_byte(pdev, addr2, &fast);
	194	fast &= ~0x07;
	195	pci_write_config_byte(pdev, addr2, fast);
85cd7251	196
1a1b172b SS	197	/* Determine timing mask and find matching mode entry */
	198	if (mode < XFER_MW_DMA_0)
	199	mask = 0xcfc3ffff;
	200	else if (mode < XFER_UDMA_0)
	201	mask = 0x31c001ff;
	202	else
	203	mask = 0x303c0000;
	204
	205	timing = hpt3x2n_find_mode(ap, mode);
	206
669a5db4	207	pci_read_config_dword(pdev, addr1, &reg);
1a1b172b SS	208	reg = (reg & ~mask) \| (timing & mask);
	209	pci_write_config_dword(pdev, addr1, reg);
	210	}
	211
	212	/**
	213	* hpt3x2n_set_piomode - PIO setup
	214	* @ap: ATA interface
	215	* @adev: device on the interface
	216	*
	217	* Perform PIO mode setup.
	218	*/
	219
	220	static void hpt3x2n_set_piomode(struct ata_port ap, struct ata_device adev)
	221	{
	222	hpt3x2n_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	223	}
	224
	225	/**
	226	* hpt3x2n_set_dmamode - DMA timing setup
	227	* @ap: ATA interface
	228	* @adev: Device being configured
	229	*
1a1b172b	230	* Set up the channel for MWDMA or UDMA modes.
669a5db4	231	*/
85cd7251	232
669a5db4 JG	233	static void hpt3x2n_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	234	{
1a1b172b	235	hpt3x2n_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	236	}
	237
	238	/**
	239	* hpt3x2n_bmdma_end - DMA engine stop
	240	* @qc: ATA command
	241	*
	242	* Clean up after the HPT3x2n and later DMA engine
	243	*/
85cd7251	244
669a5db4 JG	245	static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
	246	{
	247	struct ata_port *ap = qc->ap;
	248	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	249	int mscreg = 0x50 + 2 * ap->port_no;
	250	u8 bwsr_stat, msc_stat;
85cd7251	251
669a5db4 JG	252	pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
	253	pci_read_config_byte(pdev, mscreg, &msc_stat);
	254	if (bwsr_stat & (1 << ap->port_no))
	255	pci_write_config_byte(pdev, mscreg, msc_stat \| 0x30);
	256	ata_bmdma_stop(qc);
	257	}
	258
	259	/**
	260	* hpt3x2n_set_clock - clock control
	261	* @ap: ATA port
	262	* @source: 0x21 or 0x23 for PLL or PCI sourced clock
	263	*
	264	* Switch the ATA bus clock between the PLL and PCI clock sources
	265	* while correctly isolating the bus and resetting internal logic
	266	*
	267	* We must use the DPLL for
	268	* - writing
	269	* - second channel UDMA7 (SATA ports) or higher
	270	* - 66MHz PCI
85cd7251	271	*
669a5db4 JG	272	* or we will underclock the device and get reduced performance.
669a5db4 JG	273	*/
85cd7251	274
669a5db4 JG	275	static void hpt3x2n_set_clock(struct ata_port *ap, int source)
669a5db4 JG	276	{
256ace9b	277	void __iomem bmdma = ap->ioaddr.bmdma_addr - ap->port_no 8;
85cd7251	278
669a5db4	279	/* Tristate the bus */
0d5ff566 TH	280	iowrite8(0x80, bmdma+0x73);
0d5ff566 TH	281	iowrite8(0x80, bmdma+0x77);
85cd7251	282
669a5db4	283	/* Switch clock and reset channels */
0d5ff566 TH	284	iowrite8(source, bmdma+0x7B);
0d5ff566 TH	285	iowrite8(0xC0, bmdma+0x79);
85cd7251	286
256ace9b SS	287	/* Reset state machines, avoid enabling the disabled channels */
	288	iowrite8(ioread8(bmdma+0x70) \| 0x32, bmdma+0x70);
	289	iowrite8(ioread8(bmdma+0x74) \| 0x32, bmdma+0x74);
85cd7251	290
669a5db4	291	/* Complete reset */
0d5ff566	292	iowrite8(0x00, bmdma+0x79);
85cd7251	293
669a5db4	294	/* Reconnect channels to bus */
0d5ff566 TH	295	iowrite8(0x00, bmdma+0x73);
0d5ff566 TH	296	iowrite8(0x00, bmdma+0x77);
669a5db4 JG	297	}
669a5db4 JG	298
a52865c2	299	static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
669a5db4 JG	300	{
669a5db4 JG	301	long flags = (long)ap->host->private_data;
256ace9b	302
669a5db4	303	/* See if we should use the DPLL */
a52865c2	304	if (writing)
669a5db4 JG	305	return USE_DPLL; /* Needed for write */
	306	if (flags & PCI66)
	307	return USE_DPLL; /* Needed at 66Mhz */
85cd7251	308	return 0;
669a5db4 JG	309	}
669a5db4 JG	310
256ace9b SS	311	static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
	312	{
	313	struct ata_port *ap = qc->ap;
	314	struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
	315	int rc, flags = (long)ap->host->private_data;
	316	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
	317
	318	/* First apply the usual rules */
	319	rc = ata_std_qc_defer(qc);
	320	if (rc != 0)
	321	return rc;
	322
	323	if ((flags & USE_DPLL) != dpll && alt->qc_active)
	324	return ATA_DEFER_PORT;
	325	return 0;
	326	}
	327
9363c382	328	static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
669a5db4	329	{
669a5db4 JG	330	struct ata_port *ap = qc->ap;
669a5db4 JG	331	int flags = (long)ap->host->private_data;
256ace9b	332	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
85cd7251	333
256ace9b SS	334	if ((flags & USE_DPLL) != dpll) {
	335	flags &= ~USE_DPLL;
	336	flags \|= dpll;
	337	ap->host->private_data = (void *)(long)flags;
	338
	339	hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
669a5db4	340	}
360ff783	341	return ata_bmdma_qc_issue(qc);
669a5db4 JG	342	}
	343
	344	static struct scsi_host_template hpt3x2n_sht = {
68d1d07b	345	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	346	};
	347
	348	/*
8e834c2e	349	* Configuration for HPT302N/371N.
669a5db4	350	*/
85cd7251	351
8e834c2e	352	static struct ata_port_operations hpt3xxn_port_ops = {
029cfd6b	353	.inherits = &ata_bmdma_port_ops,
85cd7251	354
669a5db4	355	.bmdma_stop = hpt3x2n_bmdma_stop,
256ace9b SS	356
256ace9b SS	357	.qc_defer = hpt3x2n_qc_defer,
9363c382	358	.qc_issue = hpt3x2n_qc_issue,
bda30288	359
029cfd6b TH	360	.cable_detect = hpt3x2n_cable_detect,
	361	.set_piomode = hpt3x2n_set_piomode,
	362	.set_dmamode = hpt3x2n_set_dmamode,
a1efdaba	363	.prereset = hpt3x2n_pre_reset,
85cd7251	364	};
669a5db4	365
8e834c2e SS	366	/*
	367	* Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
	368	*/
	369
	370	static struct ata_port_operations hpt372n_port_ops = {
	371	.inherits = &hpt3xxn_port_ops,
	372	.mode_filter = &hpt372n_filter,
	373	};
	374
669a5db4 JG	375	/**
669a5db4 JG	376	* hpt3xn_calibrate_dpll - Calibrate the DPLL loop
85cd7251	377	* @dev: PCI device
669a5db4 JG	378	*
	379	* Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
	380	* succeeds
	381	*/
	382
	383	static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
	384	{
	385	u8 reg5b;
	386	u32 reg5c;
	387	int tries;
85cd7251	388
b197f13b	389	for (tries = 0; tries < 0x5000; tries++) {
669a5db4 JG	390	udelay(50);
	391	pci_read_config_byte(dev, 0x5b, &reg5b);
	392	if (reg5b & 0x80) {
	393	/* See if it stays set */
b197f13b	394	for (tries = 0; tries < 0x1000; tries++) {
669a5db4 JG	395	pci_read_config_byte(dev, 0x5b, &reg5b);
	396	/* Failed ? */
	397	if ((reg5b & 0x80) == 0)
	398	return 0;
	399	}
	400	/* Turn off tuning, we have the DPLL set */
	401	pci_read_config_dword(dev, 0x5c, &reg5c);
b197f13b	402	pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
669a5db4 JG	403	return 1;
	404	}
	405	}
	406	/* Never went stable */
	407	return 0;
	408	}
	409
	410	static int hpt3x2n_pci_clock(struct pci_dev *pdev)
	411	{
	412	unsigned long freq;
	413	u32 fcnt;
28e21c8c	414	unsigned long iobase = pci_resource_start(pdev, 4);
85cd7251	415
28e21c8c	416	fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
669a5db4	417	if ((fcnt >> 12) != 0xABCDE) {
dfc7e3e3 SS	418	int i;
	419	u16 sr;
	420	u32 total = 0;
	421
8d7b1c70	422	pr_warn("BIOS clock data not set\n");
dfc7e3e3 SS	423
	424	/* This is the process the HPT371 BIOS is reported to use */
	425	for (i = 0; i < 128; i++) {
	426	pci_read_config_word(pdev, 0x78, &sr);
	427	total += sr & 0x1FF;
	428	udelay(15);
	429	}
	430	fcnt = total / 128;
669a5db4 JG	431	}
669a5db4 JG	432	fcnt &= 0x1FF;
85cd7251	433
669a5db4	434	freq = (fcnt * 77) / 192;
85cd7251	435
669a5db4 JG	436	/* Clamp to bands */
	437	if (freq < 40)
	438	return 33;
	439	if (freq < 45)
	440	return 40;
	441	if (freq < 55)
	442	return 50;
	443	return 66;
	444	}
	445
	446	/**
	447	* hpt3x2n_init_one - Initialise an HPT37X/302
	448	* @dev: PCI device
	449	* @id: Entry in match table
	450	*
	451	* Initialise an HPT3x2n device. There are some interesting complications
	452	* here. Firstly the chip may report 366 and be one of several variants.
	453	* Secondly all the timings depend on the clock for the chip which we must
	454	* detect and look up
	455	*
	456	* This is the known chip mappings. It may be missing a couple of later
	457	* releases.
	458	*
	459	* Chip version PCI Rev Notes
	460	* HPT372 4 (HPT366) 5 Other driver
	461	* HPT372N 4 (HPT366) 6 UDMA133
	462	* HPT372 5 (HPT372) 1 Other driver
	463	* HPT372N 5 (HPT372) 2 UDMA133
	464	* HPT302 6 (HPT302) * Other driver
	465	* HPT302N 6 (HPT302) > 1 UDMA133
	466	* HPT371 7 (HPT371) * Other driver
	467	* HPT371N 7 (HPT371) > 1 UDMA133
	468	* HPT374 8 (HPT374) * Other driver
	469	* HPT372N 9 (HPT372N) * UDMA133
	470	*
	471	* (1) UDMA133 support depends on the bus clock
669a5db4	472	*/
85cd7251	473
669a5db4 JG	474	static int hpt3x2n_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	475	{
8e834c2e SS	476	/* HPT372N - UDMA133 */
8e834c2e SS	477	static const struct ata_port_info info_hpt372n = {
1d2808fd	478	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	479	.pio_mask = ATA_PIO4,
14bdef98 EIB	480	.mwdma_mask = ATA_MWDMA2,
bf6263a8	481	.udma_mask = ATA_UDMA6,
8e834c2e	482	.port_ops = &hpt372n_port_ops
669a5db4	483	};
8e834c2e SS	484	/* HPT302N and HPT371N - UDMA133 */
	485	static const struct ata_port_info info_hpt3xxn = {
	486	.flags = ATA_FLAG_SLAVE_POSS,
	487	.pio_mask = ATA_PIO4,
	488	.mwdma_mask = ATA_MWDMA2,
	489	.udma_mask = ATA_UDMA6,
	490	.port_ops = &hpt3xxn_port_ops
	491	};
	492	const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
89d3b360	493	u8 rev = dev->revision;
669a5db4	494	u8 irqmask;
669a5db4 JG	495	unsigned int pci_mhz;
	496	unsigned int f_low, f_high;
	497	int adjust;
28e21c8c	498	unsigned long iobase = pci_resource_start(dev, 4);
256ace9b	499	void hpriv = (void )USE_DPLL;
f08048e9 TH	500	int rc;
	501
	502	rc = pcim_enable_device(dev);
	503	if (rc)
	504	return rc;
85cd7251	505
b197f13b SS	506	switch (dev->device) {
	507	case PCI_DEVICE_ID_TTI_HPT366:
	508	/* 372N if rev >= 6 */
	509	if (rev < 6)
	510	return -ENODEV;
	511	goto hpt372n;
	512	case PCI_DEVICE_ID_TTI_HPT371:
	513	/* 371N if rev >= 2 */
	514	if (rev < 2)
	515	return -ENODEV;
	516	break;
	517	case PCI_DEVICE_ID_TTI_HPT372:
	518	/* 372N if rev >= 2 */
	519	if (rev < 2)
	520	return -ENODEV;
	521	goto hpt372n;
	522	case PCI_DEVICE_ID_TTI_HPT302:
	523	/* 302N if rev >= 2 */
	524	if (rev < 2)
669a5db4	525	return -ENODEV;
b197f13b SS	526	break;
	527	case PCI_DEVICE_ID_TTI_HPT372N:
	528	hpt372n:
	529	ppi[0] = &info_hpt372n;
	530	break;
	531	default:
8d7b1c70	532	pr_err("PCI table is bogus, please report (%d)\n", dev->device);
b197f13b	533	return -ENODEV;
669a5db4 JG	534	}
	535
	536	/* Ok so this is a chip we support */
	537
	538	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	539	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	540	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	541	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	542
	543	pci_read_config_byte(dev, 0x5A, &irqmask);
	544	irqmask &= ~0x10;
	545	pci_write_config_byte(dev, 0x5a, irqmask);
	546
28e21c8c AC	547	/*
	548	* HPT371 chips physically have only one channel, the secondary one,
	549	* but the primary channel registers do exist! Go figure...
	550	* So, we manually disable the non-existing channel here
	551	* (if the BIOS hasn't done this already).
	552	*/
	553	if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
	554	u8 mcr1;
	555	pci_read_config_byte(dev, 0x50, &mcr1);
	556	mcr1 &= ~0x04;
	557	pci_write_config_byte(dev, 0x50, mcr1);
	558	}
	559
b197f13b SS	560	/*
	561	* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
	562	* 50 for UDMA100. Right now we always use 66
	563	*/
85cd7251	564
669a5db4	565	pci_mhz = hpt3x2n_pci_clock(dev);
85cd7251	566
669a5db4 JG	567	f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
669a5db4 JG	568	f_high = f_low + 2; /* Tolerance */
85cd7251	569
669a5db4 JG	570	pci_write_config_dword(dev, 0x5C, (f_high << 16) \| f_low \| 0x100);
	571	/* PLL clock */
	572	pci_write_config_byte(dev, 0x5B, 0x21);
85cd7251	573
669a5db4	574	/* Unlike the 37x we don't try jiggling the frequency */
b197f13b	575	for (adjust = 0; adjust < 8; adjust++) {
669a5db4 JG	576	if (hpt3xn_calibrate_dpll(dev))
	577	break;
	578	pci_write_config_dword(dev, 0x5C, (f_high << 16) \| f_low);
	579	}
28e21c8c	580	if (adjust == 8) {
8d7b1c70	581	pr_err("DPLL did not stabilize!\n");
28e21c8c AC	582	return -ENODEV;
28e21c8c AC	583	}
669a5db4	584
8d7b1c70	585	pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
b197f13b SS	586
	587	/*
	588	* Set our private data up. We only need a few flags
	589	* so we use it directly.
	590	*/
60661933	591	if (pci_mhz > 60)
256ace9b	592	hpriv = (void *)(PCI66 \| USE_DPLL);
60661933 SS	593
	594	/*
	595	* On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
	596	* the MISC. register to stretch the UltraDMA Tss timing.
	597	* NOTE: This register is only writeable via I/O space.
	598	*/
	599	if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
	600	outb(inb(iobase + 0x9c) \| 0x04, iobase + 0x9c);
85cd7251	601
669a5db4	602	/* Now kick off ATA set up */
1c5afdf7	603	return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
669a5db4 JG	604	}
669a5db4 JG	605
2d2744fc JG	606	static const struct pci_device_id hpt3x2n[] = {
2d2744fc JG	607	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
28e21c8c	608	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
2d2744fc JG	609	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
	610	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
	611	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
	612
	613	{ },
669a5db4 JG	614	};
	615
	616	static struct pci_driver hpt3x2n_pci_driver = {
b197f13b	617	.name = DRV_NAME,
669a5db4	618	.id_table = hpt3x2n,
b197f13b	619	.probe = hpt3x2n_init_one,
669a5db4 JG	620	.remove = ata_pci_remove_one
	621	};
	622
2fc75da0	623	module_pci_driver(hpt3x2n_pci_driver);
669a5db4	624
669a5db4	625	MODULE_AUTHOR("Alan Cox");
0ca646db	626	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
669a5db4 JG	627	MODULE_LICENSE("GPL");
	628	MODULE_DEVICE_TABLE(pci, hpt3x2n);
	629	MODULE_VERSION(DRV_VERSION);